[PATCH v4 4/6] devicetree: bindings: Document Krait L1/L2 EDAC

Stephen Boyd
2013-12-30T20:14:15Z

The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 72 ++++++++++++++++++++++++++
1 file changed, 72 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..54de94b 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,35 @@ nodes to be present and contain the properties described below.
property identifying a 64-bit zero-initialised
memory location.

+ - interrupts
+ Usage: required for cpus with compatible string "qcom,krait".
+ Value type: <prop-encoded-array>
+ Definition: L1/CPU error interrupt
+
+ - next-level-cache
+ Usage: optional
+ Value type: <phandle>
+ Definition: phandle pointing to the next level cache
+
+- cache node
+
+ Description: Describes a cache in an ARM based system
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: shall contain at least "cache"
+
+ - cache-level
+ Usage: required
+ Value type: <u32>
+ Definition: level in the cache heirachy
+
+ - interrupts
+ Usage: required for cpus with compatible string "qcom,krait"
+ Value type: <prop-encoded-array>
+ Definition: the L2 error interrupt
+
Example 1 (dual-cluster big.LITTLE system 32-bit):

cpus {
@@ -382,3 +411,46 @@ cpus {
cpu-release-addr = <0 0x20000000>;
};
};
+
+
+Example 5 (Krait 32-bit system):
+
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <1 9 0xf04>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 2 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu at 3 {
+ device_type = "cpu";
+ compatible = "qcom,krait";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ interrupts = <0 2 0x4>;
+ };
+};
--
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