[PATCH] arm: Add Arm Erratum 773769 for Large data RAM latency.

[linux@arm.linux.org.uk (Russell King - ARM Linux)]

On Wed, Jan 08, 2014 at 11:43:29AM -0800, Doug Anderson wrote:
> Olof came up with the idea that you could update the RW firmware
> (affects initial boot) and then cache away the value and restore it in
> the kernel after resume.  That would still require a kernel patch but
> perhaps a less objectionable one.  ...of course if writing this
> register is a problem in secure mode then maybe that patch would be
> NAKed anyway.

It's not a problem in secure mode, since secure mode will have access
to the register.  It's the non-secure mode where various registers
either ignore writes, or they trigger an exception that are the problem.

Consider what would happen if an exception were to be triggered when no
exception handlers were installed (eg, because the MMU is not enabled.)

> That's one I didn't think about, you're right.  ...but we're really
> getting into hypothetical situations here.  Are there any r2p0
> products that have such a fix (and thus require a latency of >= 4)?

Really, we can't know, because this kind of information is dependent on
the SoC, and probably such customisations are only knowable via NDAs.

However, I do know of some A9 CPUs where exactly this kind of thing has
happened - where various selected silicon bugs have been fixed but the
revision still reports the same as one with all those bugs.

-- 
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Estimate before purchase was "up to 13.2Mbit".