* [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros
@ 2014-01-25 16:43 Shawn Guo
2014-01-25 16:43 ` [PATCH 1/9] ARM: dts: imx6qdl: " Shawn Guo
` (10 more replies)
0 siblings, 11 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rob,
In order to solve a pinctrl data efficiency problem, we introduced
pingrp macros [1] in this development cycle as the base of board dts
support. The whole imx-dt-3.14 pull request has been held by Olof for
a few weeks because he wants to get a general approval from DT folks
on this change. But unfortunately it appears that you are not fond of
this change.
I just spent the day to create a patch series against imx-dt-3.14 to
remove these pingrp macros. May I get your nod on this quick
turn-around, so that we do not miss the merge window?
Hi Olof,
I guess we do not have to shut the door for imx-dt-3.14 if you and DT
folks are happy with this patch series, which is a quite straight
forward search&replace change?
Shawn
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/275912/
Shawn Guo (9):
ARM: dts: imx6qdl: remove the use of pingrp macros
ARM: dts: imx6sl: remove the use of pingrp macros
ARM: dts: imx53: remove the use of pingrp macros
ARM: dts: imx51: remove the use of pingrp macros
ARM: dts: imx50: remove the use of pingrp macros
ARM: dts: imx35: remove the use of pingrp macros
ARM: dts: imx25: remove the use of pingrp macros
ARM: dts: imx27: remove the use of pingrp macros
ARM: dts: vf610: remove the use of pingrp macros
arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | 17 +-
.../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 56 ++-
arch/arm/boot/dts/imx25-pingrp.h | 81 ---
arch/arm/boot/dts/imx25.dtsi | 2 +-
arch/arm/boot/dts/imx27-apf27.dts | 26 +-
arch/arm/boot/dts/imx27-apf27dev.dts | 65 ++-
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 27 +-
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 26 +-
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 23 +-
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 38 +-
arch/arm/boot/dts/imx27-pingrp.h | 151 ------
arch/arm/boot/dts/imx27.dtsi | 2 +-
arch/arm/boot/dts/imx35-pingrp.h | 104 ----
arch/arm/boot/dts/imx35.dtsi | 1 -
arch/arm/boot/dts/imx50-evk.dts | 28 +-
arch/arm/boot/dts/imx50-pingrp.h | 146 ------
arch/arm/boot/dts/imx50.dtsi | 2 +-
arch/arm/boot/dts/imx51-apf51.dts | 26 +-
arch/arm/boot/dts/imx51-apf51dev.dts | 64 ++-
arch/arm/boot/dts/imx51-babbage.dts | 142 +++++-
arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | 26 +-
.../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 31 +-
arch/arm/boot/dts/imx51-pingrp.h | 249 ---------
arch/arm/boot/dts/imx51.dtsi | 2 +-
arch/arm/boot/dts/imx53-ard.dts | 18 +-
arch/arm/boot/dts/imx53-evk.dts | 51 +-
arch/arm/boot/dts/imx53-m53evk.dts | 128 ++++-
arch/arm/boot/dts/imx53-pingrp.h | 352 -------------
arch/arm/boot/dts/imx53-qsb.dts | 88 +++-
arch/arm/boot/dts/imx53-smd.dts | 77 ++-
arch/arm/boot/dts/imx53-tqma53.dtsi | 89 +++-
arch/arm/boot/dts/imx53-voipac-bsb.dts | 21 +-
arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 47 +-
arch/arm/boot/dts/imx53.dtsi | 2 +-
arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
arch/arm/boot/dts/imx6dl.dtsi | 1 -
arch/arm/boot/dts/imx6q-arm2.dts | 81 ++-
arch/arm/boot/dts/imx6q-cm-fx6.dts | 44 +-
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 47 +-
arch/arm/boot/dts/imx6q-gw5400-a.dts | 75 ++-
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 53 +-
arch/arm/boot/dts/imx6q-sbc6x.dts | 37 +-
arch/arm/boot/dts/imx6q-udoo.dts | 33 +-
arch/arm/boot/dts/imx6q.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 77 ++-
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 88 +++-
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 93 +++-
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 93 +++-
arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 56 ++-
arch/arm/boot/dts/imx6qdl-pingrp.h | 532 --------------------
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 139 ++++-
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 56 ++-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 86 +++-
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 78 ++-
arch/arm/boot/dts/imx6sl-evk.dts | 120 ++++-
arch/arm/boot/dts/imx6sl-pingrp.h | 148 ------
arch/arm/boot/dts/imx6sl.dtsi | 1 -
arch/arm/boot/dts/vf610-cosmic.dts | 17 +-
arch/arm/boot/dts/vf610-pingrp.h | 127 -----
arch/arm/boot/dts/vf610-twr.dts | 42 +-
arch/arm/boot/dts/vf610.dtsi | 2 +-
62 files changed, 2163 insertions(+), 2182 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx25-pingrp.h
delete mode 100644 arch/arm/boot/dts/imx27-pingrp.h
delete mode 100644 arch/arm/boot/dts/imx35-pingrp.h
delete mode 100644 arch/arm/boot/dts/imx50-pingrp.h
delete mode 100644 arch/arm/boot/dts/imx51-pingrp.h
delete mode 100644 arch/arm/boot/dts/imx53-pingrp.h
delete mode 100644 arch/arm/boot/dts/imx6qdl-pingrp.h
delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
delete mode 100644 arch/arm/boot/dts/vf610-pingrp.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/9] ARM: dts: imx6qdl: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-27 14:37 ` Russell King - ARM Linux
2014-01-25 16:43 ` [PATCH 2/9] ARM: dts: imx6sl: " Shawn Guo
` (9 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in imx6qdl-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
arch/arm/boot/dts/imx6dl.dtsi | 1 -
arch/arm/boot/dts/imx6q-arm2.dts | 81 ++++-
arch/arm/boot/dts/imx6q-cm-fx6.dts | 44 ++-
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 47 ++-
arch/arm/boot/dts/imx6q-gw5400-a.dts | 75 +++-
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 53 ++-
arch/arm/boot/dts/imx6q-sbc6x.dts | 37 +-
arch/arm/boot/dts/imx6q-udoo.dts | 33 +-
arch/arm/boot/dts/imx6q.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 77 +++-
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 88 ++++-
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 93 ++++-
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 93 ++++-
arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 56 ++-
arch/arm/boot/dts/imx6qdl-pingrp.h | 532 ----------------------------
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 139 +++++++-
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 56 ++-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 86 ++++-
arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 78 +++-
21 files changed, 1013 insertions(+), 667 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx6qdl-pingrp.h
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index a3513fc..26dbb3e 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -60,7 +60,10 @@
};
pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_hummingboard_spdif: hummingboard-spdif {
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index e2ec0fb..9c4942f 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -10,7 +10,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl-pinfunc.h"
-#include "imx6qdl-pingrp.h"
#include "imx6qdl.dtsi"
/ {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 631a426..de3babd 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -75,27 +75,83 @@
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP2_GPIO6>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
};
pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
+ >;
};
pinctrl_uart4: uart4grp {
- fsl,pins = <MX6QDL_UART4_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
};
pinctrl_usdhc3_cdwp: usdhc3cdwp {
@@ -106,7 +162,18 @@
};
pinctrl_usdhc4: usdhc4grp {
- fsl,pins = <MX6QDL_USDHC4_PINGRP_D8>;
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index 1a8ee79..99b46f8 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -49,15 +49,53 @@
&iomuxc {
imx6q-cm-fx6 {
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
};
pinctrl_uart4: uart4grp {
- fsl,pins = <MX6QDL_UART4_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index 84f5143..f81ea0e0 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -115,11 +115,31 @@
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX6QDL_I2C2_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
};
pinctrl_stmpe: stmpegrp {
@@ -127,19 +147,34 @@
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 5f76342..902f983 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -387,47 +387,100 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX6QDL_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
+ >;
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX6QDL_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ >;
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX6QDL_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX6QDL_I2C3_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart5: uart5grp {
- fsl,pins = <MX6QDL_UART5_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index 05b4796..1745e59 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -138,27 +138,68 @@
};
pinctrl_ecspi3: ecspi3grp {
- fsl,pins = <MX6QDL_ECSPI3_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ >;
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_uart4: uart4grp {
- fsl,pins = <MX6QDL_UART4_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
pinctrl_usdhc3_cdwp: usdhc3cdwp {
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
index 852675a..7b63bcf 100644
--- a/arch/arm/boot/dts/imx6q-sbc6x.dts
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -28,19 +28,48 @@
&iomuxc {
imx6q-sbc6x {
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index 47a5eda..ed397d1 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -31,15 +31,42 @@
&iomuxc {
imx6q-udoo {
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 021e0cb..6295fa8 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -10,7 +10,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
-#include "imx6qdl-pingrp.h"
#include "imx6qdl.dtsi"
/ {
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index fb29da0..98a4221 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -234,43 +234,100 @@
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1_NODQS>;
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX6QDL_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX6QDL_I2C3_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart3: uart3grp {
- fsl,pins = <MX6QDL_UART3_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart5: uart5grp {
- fsl,pins = <MX6QDL_UART5_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index a6c77b5..8e99c9a 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -323,47 +323,113 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX6QDL_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
+ >;
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1_NODQS>;
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX6QDL_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX6QDL_I2C3_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart5: uart5grp {
- fsl,pins = <MX6QDL_UART5_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 35028a5..c8e5ae0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -356,51 +356,120 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX6QDL_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
+ >;
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <MX6QDL_FLEXCAN1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+ >;
};
pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1_NODQS>;
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX6QDL_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX6QDL_I2C3_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart5: uart5grp {
- fsl,pins = <MX6QDL_UART5_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 34b26b9..2795dfc 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -378,51 +378,120 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX6QDL_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
+ >;
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <MX6QDL_FLEXCAN1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+ >;
};
pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1_NODQS>;
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX6QDL_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX6QDL_I2C3_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart5: uart5grp {
- fsl,pins = <MX6QDL_UART5_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index 524c169..c9ec334 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -57,7 +57,10 @@
};
pinctrl_microsom_uart1: microsom-uart1 {
- fsl,pins = <MX6QDL_UART1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_microsom_usbotg: microsom-usbotg {
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index e83ffc7..358d867 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -198,19 +198,40 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
- MX6QDL_ECSPI1_PINGRP1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
- MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
/* Phy reset */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
@@ -235,7 +256,10 @@
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_pwm1: pwm1grp {
@@ -257,11 +281,17 @@
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
@@ -275,14 +305,24 @@
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
- MX6QDL_USDHC3_PINGRP_D4
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
- MX6QDL_USDHC4_PINGRP_D4
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-pingrp.h b/arch/arm/boot/dts/imx6qdl-pingrp.h
deleted file mode 100644
index 082f0df..0000000
--- a/arch/arm/boot/dts/imx6qdl-pingrp.h
+++ /dev/null
@@ -1,532 +0,0 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX6QDL_PINGRP_H
-#define __DTS_IMX6QDL_PINGRP_H
-
-#define MX6QDL_AUDMUX_PINGRP1 \
- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 \
- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 \
- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 \
- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
-
-#define MX6QDL_AUDMUX_PINGRP2 \
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 \
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 \
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 \
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
-
-#define MX6QDL_AUDMUX_PINGRP3 \
- MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 \
- MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 \
- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 \
-
-#define MX6QDL_AUDMUX_PINGRP4 \
- MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 \
- MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 \
- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
-
-#define MX6QDL_AUDMUX_PINGRP5 \
- MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 \
- MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 \
- MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 \
- MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
-
-#define MX6QDL_ECSPI1_PINGRP1 \
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 \
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 \
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
-
-#define MX6QDL_ECSPI1_PINGRP2 \
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 \
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 \
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
-
-#define MX6QDL_ECSPI3_PINGRP1 \
- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 \
- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 \
- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
-
-#define MX6QDL_ENET_PINGRP_RGMII(rx_pad, tx_pad) \
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC rx_pad \
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 rx_pad \
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 rx_pad \
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 rx_pad \
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 rx_pad \
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL rx_pad \
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC tx_pad \
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 tx_pad \
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 tx_pad \
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 tx_pad \
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 tx_pad \
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL tx_pad \
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK tx_pad
-
-#define MX6QDL_ENET_PINGRP_RGMII_MD(rx_pad, tx_pad) \
- MX6QDL_ENET_PINGRP_RGMII(rx_pad, tx_pad) \
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO tx_pad \
- MX6QDL_PAD_ENET_MDC__ENET_MDC tx_pad
-
-#define MX6QDL_ENET_PINGRP1 \
- MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0) \
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
-
-#define MX6QDL_ENET_PINGRP2 \
- MX6QDL_ENET_PINGRP_RGMII(0x1b0b0, 0x1b0b0) \
- MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 \
- MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
-
-#define MX6QDL_ENET_PINGRP3 \
- MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0) \
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
-
-#define MX6QDL_ENET_PINGRP4 \
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 \
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 \
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 \
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 \
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 \
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 \
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 \
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 \
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
-
-#define MX6QDL_ENET_PINGRP1_GPIO6 MX6QDL_ENET_PINGRP1 \
- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
-
-#define MX6QDL_ENET_PINGRP2_GPIO6 MX6QDL_ENET_PINGRP2 \
- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
-
-#define MX6QDL_ENET_PINGRP3_GPIO6 MX6QDL_ENET_PINGRP3 \
- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
-
-#define MX6QDL_ESAI_PINGRP1 \
- MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 \
- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
- MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 \
- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
- MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 \
- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
-
-#define MX6QDL_ESAI_PINGRP2 \
- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
- MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 \
- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
- MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 \
- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 \
- MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 \
- MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
-
-#define MX6QDL_FLEXCAN1_PINGRP1 \
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 \
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
-
-#define MX6QDL_FLEXCAN1_PINGRP2 \
- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 \
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
-
-#define MX6QDL_FLEXCAN2_PINGRP1 \
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 \
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
-
-#define MX6QDL_GPMI_NAND_PINGRP1 \
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 \
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
-
-#define MX6QDL_GPMI_NAND_PINGRP1_NODQS \
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
-
-#define MX6QDL_HDMI_HDCP_PINGRP1 \
- MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 \
- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
-
-#define MX6QDL_HDMI_HDCP_PINGRP2 \
- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
- MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
-
-#define MX6QDL_HDMI_HDCP_PINGRP3 \
- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
-
-#define MX6QDL_HDMI_CEC_PINGRP1 \
- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
-
-#define MX6QDL_HDMI_CEC_PINGRP2 \
- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
-
-#define MX6QDL_I2C1_PINGRP1 \
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 \
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
-
-#define MX6QDL_I2C1_PINGRP2 \
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 \
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
-
-#define MX6QDL_I2C2_PINGRP1 \
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
-
-#define MX6QDL_I2C2_PINGRP2 \
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 \
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-
-#define MX6QDL_I2C2_PINGRP3 \
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-
-#define MX6QDL_I2C3_PINGRP1 \
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 \
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
-
-#define MX6QDL_I2C3_PINGRP2 \
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
-
-#define MX6QDL_I2C3_PINGRP3 \
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 \
- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
-
-#define MX6QDL_I2C3_PINGRP4 \
- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
-
-#define MX6QDL_IPU1_PINGRP1 \
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 \
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 \
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 \
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 \
- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 \
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 \
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 \
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 \
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 \
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 \
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 \
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 \
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 \
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 \
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 \
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 \
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 \
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 \
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 \
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 \
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 \
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 \
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 \
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 \
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 \
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 \
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 \
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 \
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
-
-/* parallel camera */
-#define MX6QDL_IPU1_PINGRP2 \
- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
- MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 \
- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
-
-/* parallel port 16-bit */
-#define MX6QDL_IPU1_PINGRP3 \
- MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 \
- MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 \
- MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 \
- MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 \
- MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 \
- MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 \
- MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 \
- MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 \
- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
-
-#define MX6QDL_MLB_PINGRP1 \
- MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 \
- MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
- MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
-
-#define MX6QDL_MLB_PINGRP2 \
- MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 \
- MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
- MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
-
-#define MX6QDL_PWM1_PINGRP1 \
- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
-
-#define MX6QDL_PWM3_PINGRP1 \
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
-
-#define MX6QDL_SPDIF_PINGRP1 \
- MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
-
-#define MX6QDL_SPDIF_PINGRP2 \
- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 \
- MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
-
-#define MX6QDL_SPDIF_PINGRP3 \
- MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
-
-#define MX6QDL_UART1_PINGRP1 \
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
-
-#define MX6QDL_UART1_PINGRP2 \
- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
-
-#define MX6QDL_UART2_PINGRP1 \
- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
-
-/* DTE mode */
-#define MX6QDL_UART2_PINGRP2 \
- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 \
- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 \
- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
-
-#define MX6QDL_UART2_PINGRP3 \
- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
-
-#define MX6QDL_UART3_PINGRP1 \
- MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 \
- MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 \
- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
-
-#define MX6QDL_UART3_PINGRP2 \
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 \
- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 \
- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
-
-#define MX6QDL_UART3_PINGRP3 \
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
-
-#define MX6QDL_UART4_PINGRP1 \
- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
-
-#define MX6QDL_UART5_PINGRP1 \
- MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 \
- MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
-
-#define MX6QDL_USBOTG_PINGRP1 \
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
-
-#define MX6QDL_USBOTG_PINGRP2 \
- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
-
-#define MX6QDL_USBH2_PINGRP1 \
- MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 \
- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
-
-#define MX6QDL_USBH2_PINGRP2 \
- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
-
-#define MX6QDL_USBH3_PINGRP1 \
- MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 \
- MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
-
-#define MX6QDL_USBH3_PINGRP2 \
- MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
-
-#define MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
- MX6QDL_PAD_SD1_CMD__SD1_CMD pad \
- MX6QDL_PAD_SD1_CLK__SD1_CLK pad_clk \
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 pad \
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 pad \
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 pad \
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 pad_data3
-
-#define MX6QDL_USDHC1_D8(pad, pad_data3, pad_clk) \
- MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
- MX6QDL_PAD_NANDF_D0__SD1_DATA4 pad \
- MX6QDL_PAD_NANDF_D1__SD1_DATA5 pad \
- MX6QDL_PAD_NANDF_D2__SD1_DATA6 pad \
- MX6QDL_PAD_NANDF_D3__SD1_DATA7 pad
-
-#define MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
- MX6QDL_PAD_SD2_CMD__SD2_CMD pad \
- MX6QDL_PAD_SD2_CLK__SD2_CLK pad_clk \
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 pad \
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 pad \
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 pad \
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 pad_data3
-
-#define MX6QDL_USDHC2_D8(pad, pad_data3, pad_clk) \
- MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
- MX6QDL_PAD_NANDF_D4__SD2_DATA4 pad \
- MX6QDL_PAD_NANDF_D5__SD2_DATA5 pad \
- MX6QDL_PAD_NANDF_D6__SD2_DATA6 pad \
- MX6QDL_PAD_NANDF_D7__SD2_DATA7 pad
-
-#define MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
- MX6QDL_PAD_SD3_CMD__SD3_CMD pad \
- MX6QDL_PAD_SD3_CLK__SD3_CLK pad_clk \
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 pad \
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 pad \
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 pad \
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 pad_data3
-
-#define MX6QDL_USDHC3_D8(pad, pad_data3, pad_clk) \
- MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 pad \
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 pad \
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 pad \
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 pad
-
-#define MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
- MX6QDL_PAD_SD4_CMD__SD4_CMD pad \
- MX6QDL_PAD_SD4_CLK__SD4_CLK pad_clk \
- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 pad \
- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 pad \
- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 pad \
- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 pad_data3
-
-#define MX6QDL_USDHC4_D8(pad, pad_data3, pad_clk) \
- MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 pad \
- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 pad \
- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 pad \
- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 pad
-
-#define MX6QDL_USDHC1_PINGRP_D4 MX6QDL_USDHC1_D4(0x17059,0x17059,0x10059)
-#define MX6QDL_USDHC1_PINGRP_D4_100MHZ MX6QDL_USDHC1_D4(0x170b9,0x170b9,0x100b9)
-#define MX6QDL_USDHC1_PINGRP_D4_200MHZ MX6QDL_USDHC1_D4(0x170f9,0x170f9,0x100f9)
-#define MX6QDL_USDHC1_PINGRP_D8 MX6QDL_USDHC1_D8(0x17059,0x17059,0x10059)
-#define MX6QDL_USDHC1_PINGRP_D8_100MHZ MX6QDL_USDHC1_D8(0x170b9,0x170b9,0x100b9)
-#define MX6QDL_USDHC1_PINGRP_D8_200MHZ MX6QDL_USDHC1_D8(0x170f9,0x170f9,0x100f9)
-
-#define MX6QDL_USDHC2_PINGRP_D4 MX6QDL_USDHC2_D4(0x17059,0x17059,0x10059)
-#define MX6QDL_USDHC2_PINGRP_D4_100MHZ MX6QDL_USDHC2_D4(0x170b9,0x170b9,0x100b9)
-#define MX6QDL_USDHC2_PINGRP_D4_200MHZ MX6QDL_USDHC2_D4(0x170f9,0x170f9,0x100f9)
-#define MX6QDL_USDHC2_PINGRP_D8 MX6QDL_USDHC2_D8(0x17059,0x17059,0x10059)
-#define MX6QDL_USDHC2_PINGRP_D8_100MHZ MX6QDL_USDHC2_D8(0x170b9,0x170b9,0x100b9)
-#define MX6QDL_USDHC2_PINGRP_D8_200MHZ MX6QDL_USDHC2_D8(0x170f9,0x170f9,0x100f9)
-
-#define MX6QDL_USDHC3_PINGRP_D4 MX6QDL_USDHC3_D4(0x17059,0x17059,0x10059)
-#define MX6QDL_USDHC3_PINGRP_D4_100MHZ MX6QDL_USDHC3_D4(0x170b9,0x170b9,0x100b9)
-#define MX6QDL_USDHC3_PINGRP_D4_200MHZ MX6QDL_USDHC3_D4(0x170f9,0x170f9,0x100f9)
-#define MX6QDL_USDHC3_PINGRP_D8 MX6QDL_USDHC3_D8(0x17059,0x17059,0x10059)
-#define MX6QDL_USDHC3_PINGRP_D8_100MHZ MX6QDL_USDHC3_D8(0x170b9,0x170b9,0x100b9)
-#define MX6QDL_USDHC3_PINGRP_D8_200MHZ MX6QDL_USDHC3_D8(0x170f9,0x170f9,0x100f9)
-
-#define MX6QDL_USDHC4_PINGRP_D4 MX6QDL_USDHC4_D4(0x17059,0x17059,0x10059)
-#define MX6QDL_USDHC4_PINGRP_D4_100MHZ MX6QDL_USDHC4_D4(0x170b9,0x170b9,0x100b9)
-#define MX6QDL_USDHC4_PINGRP_D4_200MHZ MX6QDL_USDHC4_D4(0x170f9,0x170f9,0x100f9)
-#define MX6QDL_USDHC4_PINGRP_D8 MX6QDL_USDHC4_D8(0x17059,0x17059,0x10059)
-#define MX6QDL_USDHC4_PINGRP_D8_100MHZ MX6QDL_USDHC4_D8(0x170b9,0x170b9,0x100b9)
-#define MX6QDL_USDHC4_PINGRP_D8_200MHZ MX6QDL_USDHC4_D8(0x170f9,0x170f9,0x100f9)
-
-#define MX6QDL_WEIM_CS0_PINGRP1 \
- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
-
-#define MX6QDL_WEIM_NOR_PINGRP1 \
- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 \
- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 \
- MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 \
- MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 \
- MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 \
- MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 \
- MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 \
- MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 \
- MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 \
- MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 \
- MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 \
- MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 \
- MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 \
- MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 \
- MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 \
- MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 \
- MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 \
- MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 \
- MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 \
- MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 \
- MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 \
- MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 \
- MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 \
- MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 \
- MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 \
- MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 \
- MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 \
- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 \
- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 \
- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 \
- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 \
- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 \
- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 \
- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 \
- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 \
- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 \
- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 \
- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 \
- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 \
- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 \
- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 \
- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 \
- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
-
-#endif /* __DTS_IMX6QDL_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 088b0d2..7fa5e40 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -69,7 +69,11 @@
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX6QDL_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ >;
};
pinctrl_ecspi1_cs: ecspi1cs {
@@ -79,11 +83,46 @@
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP2_GPIO6>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
+ >;
};
pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
};
pinctrl_spdif: spdifgrp {
@@ -93,27 +132,109 @@
};
pinctrl_uart4: uart4grp {
- fsl,pins = <MX6QDL_UART4_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D8_100MHZ>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
+ >;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D8_200MHZ>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
+ >;
};
pinctrl_weim_cs0: weimcs0grp {
- fsl,pins = <MX6QDL_WEIM_CS0_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+ >;
};
pinctrl_weim_nor: weimnorgrp {
- fsl,pins = <MX6QDL_WEIM_NOR_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+ MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+ MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+ MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+ MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+ MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+ MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+ MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+ MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+ MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+ MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+ MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+ MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+ MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+ MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+ MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+ MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+ MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+ MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+ MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+ MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+ MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+ MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+ MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+ MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index e8cbcd7..52e3813 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -197,19 +197,40 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX6QDL_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
+ >;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
- MX6QDL_ECSPI1_PINGRP1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
- MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
@@ -234,7 +255,10 @@
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
};
pinctrl_pwm1: pwm1grp {
@@ -256,11 +280,17 @@
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX6QDL_UART2_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 \
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
@@ -274,7 +304,12 @@
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
- MX6QDL_USDHC3_PINGRP_D4
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
>;
@@ -282,7 +317,12 @@
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
- MX6QDL_USDHC4_PINGRP_D4
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 91e5dd4..d6dc7ac 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -306,15 +306,41 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX6QDL_ECSPI1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ >;
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_gpio_keys: gpio_keysgrp {
@@ -326,35 +352,73 @@
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX6QDL_I2C1_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX6QDL_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX6QDL_I2C3_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
};
pinctrl_pwm1: pwm1grp {
- fsl,pins = <MX6QDL_PWM1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <MX6QDL_USDHC2_PINGRP_D8>;
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 88894b1..d050888 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -97,43 +97,101 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
};
pinctrl_enet: enetgrp {
- fsl,pins = <MX6QDL_ENET_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX6QDL_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
};
pinctrl_spdif: spdifgrp {
- fsl,pins = <MX6QDL_SPDIF_PINGRP3>;
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6QDL_UART1_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
};
pinctrl_uart3: uart3grp {
- fsl,pins = <MX6QDL_UART3_PINGRP2>;
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+ >;
};
pinctrl_usbotg: usbotggrp {
- fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
};
pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <MX6QDL_USDHC1_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ >;
};
pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 2/9] ARM: dts: imx6sl: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
2014-01-25 16:43 ` [PATCH 1/9] ARM: dts: imx6qdl: " Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-28 10:17 ` Heiko Stübner
2014-01-25 16:43 ` [PATCH 3/9] ARM: dts: imx53: " Shawn Guo
` (8 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in imx6sl-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx6sl-evk.dts | 120 ++++++++++++++++++++++++++----
arch/arm/boot/dts/imx6sl-pingrp.h | 148 -------------------------------------
arch/arm/boot/dts/imx6sl.dtsi | 1 -
3 files changed, 107 insertions(+), 162 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index f5e4513..8594d13 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -86,55 +86,149 @@
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX6SL_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
+ MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
+ MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX6SL_FEC_PINGRP1>;
+ fsl,pins = <
+ MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
+ MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
+ MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
+ MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
+ MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
+ MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
+ MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
+ MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
+ MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX6SL_UART1_PINGRP1>;
+ fsl,pins = <
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ >;
};
pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <MX6SL_USBOTG1_PINGRP1>;
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
};
pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <MX6SL_USDHC1_PINGRP_D8>;
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+ >;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <MX6SL_USDHC1_PINGRP_D8_100MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
+ >;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <MX6SL_USDHC1_PINGRP_D8_200MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
+ >;
};
pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <MX6SL_USDHC2_PINGRP_D4>;
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
- fsl,pins = <MX6SL_USDHC2_PINGRP_D4_100MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
- fsl,pins = <MX6SL_USDHC2_PINGRP_D4_200MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
};
pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <MX6SL_USDHC3_PINGRP_D4>;
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
- fsl,pins = <MX6SL_USDHC3_PINGRP_D4_100MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
- fsl,pins = <MX6SL_USDHC3_PINGRP_D4_200MHZ>;
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx6sl-pingrp.h b/arch/arm/boot/dts/imx6sl-pingrp.h
deleted file mode 100644
index ead26d4..0000000
--- a/arch/arm/boot/dts/imx6sl-pingrp.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX6SL_PINGRP_H
-#define __DTS_IMX6SL_PINGRP_H
-
-#define MX6SL_ECSPI1_PINGRP1 \
- MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 \
- MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 \
- MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
-
-#define MX6SL_FEC_PINGRP1 \
- MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 \
- MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 \
- MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 \
- MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 \
- MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 \
- MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 \
- MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 \
- MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 \
- MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
-
-#define MX6SL_UART1_PINGRP1 \
- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 \
- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
-
-#define MX6SL_USBOTG1_PINGRP1 \
- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG1_PINGRP2 \
- MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG1_PINGRP3 \
- MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG1_PINGRP4 \
- MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG1_PINGRP5 \
- MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
-
-#define MX6SL_USBOTG2_PINGRP1 \
- MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
-
-#define MX6SL_USBOTG2_PINGRP2 \
- MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
-
-#define MX6SL_USBOTG2_PINGRP3 \
- MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
-
-#define MX6SL_USBOTG2_PINGRP4 \
- MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
-
-#define MX6SL_USDHC1_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD1_CMD__SD1_CMD pad \
- MX6SL_PAD_SD1_CLK__SD1_CLK pad_clk \
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 pad \
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 pad \
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 pad \
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 pad_data3
-
-#define MX6SL_USDHC1_D8(pad, pad_data3, pad_clk) \
- MX6SL_USDHC1_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 pad \
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 pad \
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 pad \
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 pad
-
-#define MX6SL_USDHC2_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD2_CMD__SD2_CMD pad \
- MX6SL_PAD_SD2_CLK__SD2_CLK pad_clk \
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 pad \
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 pad \
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 pad \
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 pad_data3
-
-#define MX6SL_USDHC2_D8(pad, pad_data3, pad_clk) \
- MX6SL_USDHC2_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD2_DAT4__SD2_DATA4 pad \
- MX6SL_PAD_SD2_DAT5__SD2_DATA5 pad \
- MX6SL_PAD_SD2_DAT6__SD2_DATA6 pad \
- MX6SL_PAD_SD2_DAT7__SD2_DATA7 pad
-
-#define MX6SL_USDHC3_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD3_CMD__SD3_CMD pad \
- MX6SL_PAD_SD3_CLK__SD3_CLK pad_clk \
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 pad \
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 pad \
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 pad \
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 pad_data3
-
-#define MX6SL_USDHC3_D8(pad, pad_data3, pad_clk) \
- MX6SL_USDHC3_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_SD2_DAT4__SD3_DATA4 pad \
- MX6SL_PAD_SD2_DAT5__SD3_DATA5 pad \
- MX6SL_PAD_SD2_DAT6__SD3_DATA6 pad \
- MX6SL_PAD_SD2_DAT7__SD3_DATA7 pad
-
-#define MX6SL_USDHC4_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_EPDC_BDR1__SD4_CMD pad \
- MX6SL_PAD_EPDC_BDR0__SD4_CLK pad_clk \
- MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 pad \
- MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 pad \
- MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 pad \
- MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 pad_data3
-
-#define MX6SL_USDHC4_D8(pad, pad_data3, pad_clk) \
- MX6SL_USDHC4_D4(pad, pad_data3, pad_clk) \
- MX6SL_PAD_KEY_COL7__SD4_DATA4 pad \
- MX6SL_PAD_KEY_ROW7__SD4_DATA5 pad \
- MX6SL_PAD_KEY_COL3__SD4_DATA6 pad \
- MX6SL_PAD_KEY_ROW3__SD4_DATA7 pad
-
-#define MX6SL_USDHC1_PINGRP_D4 MX6SL_USDHC1_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC1_PINGRP_D4_100MHZ MX6SL_USDHC1_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC1_PINGRP_D4_200MHZ MX6SL_USDHC1_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC1_PINGRP_D8 MX6SL_USDHC1_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC1_PINGRP_D8_100MHZ MX6SL_USDHC1_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC1_PINGRP_D8_200MHZ MX6SL_USDHC1_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC2_PINGRP_D4 MX6SL_USDHC2_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC2_PINGRP_D4_100MHZ MX6SL_USDHC2_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC2_PINGRP_D4_200MHZ MX6SL_USDHC2_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC2_PINGRP_D8 MX6SL_USDHC2_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC2_PINGRP_D8_100MHZ MX6SL_USDHC2_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC2_PINGRP_D8_200MHZ MX6SL_USDHC2_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC3_PINGRP_D4 MX6SL_USDHC3_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC3_PINGRP_D4_100MHZ MX6SL_USDHC3_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC3_PINGRP_D4_200MHZ MX6SL_USDHC3_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC3_PINGRP_D8 MX6SL_USDHC3_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC3_PINGRP_D8_100MHZ MX6SL_USDHC3_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC3_PINGRP_D8_200MHZ MX6SL_USDHC3_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC4_PINGRP_D4 MX6SL_USDHC4_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC4_PINGRP_D4_100MHZ MX6SL_USDHC4_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC4_PINGRP_D4_200MHZ MX6SL_USDHC4_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC4_PINGRP_D8 MX6SL_USDHC4_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC4_PINGRP_D8_100MHZ MX6SL_USDHC4_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC4_PINGRP_D8_200MHZ MX6SL_USDHC4_D8(0x170f9, 0x170f9, 0x100f9)
-
-#endif /* __DTS_IMX6SL_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 2ed687c..2b7641a 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -10,7 +10,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
-#include "imx6sl-pingrp.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/9] ARM: dts: imx53: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
2014-01-25 16:43 ` [PATCH 1/9] ARM: dts: imx6qdl: " Shawn Guo
2014-01-25 16:43 ` [PATCH 2/9] ARM: dts: imx6sl: " Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-25 16:43 ` [PATCH 4/9] ARM: dts: imx51: " Shawn Guo
` (7 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in imx53-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx53-ard.dts | 18 +-
arch/arm/boot/dts/imx53-evk.dts | 51 +++-
arch/arm/boot/dts/imx53-m53evk.dts | 128 ++++++++--
arch/arm/boot/dts/imx53-pingrp.h | 352 ---------------------------
arch/arm/boot/dts/imx53-qsb.dts | 88 ++++++-
arch/arm/boot/dts/imx53-smd.dts | 77 +++++-
arch/arm/boot/dts/imx53-tqma53.dtsi | 89 ++++++-
arch/arm/boot/dts/imx53-voipac-bsb.dts | 21 +-
arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 47 +++-
arch/arm/boot/dts/imx53.dtsi | 2 +-
10 files changed, 459 insertions(+), 414 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx53-pingrp.h
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 2bd97c3..e9337ad 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -153,11 +153,25 @@
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX53_ESDHC1_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
+ MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
+ MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
+ MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX53_UART1_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 214ac2e..2727a6f 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -94,27 +94,66 @@
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX53_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
+ MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
+ MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
+ >;
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX53_ESDHC1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ >;
};
pinctrl_esdhc3: esdhc3grp {
- fsl,pins = <MX53_ESDHC3_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX53_FEC_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX53_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX53_UART1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
+ MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index c623774..7100d08 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -244,59 +244,159 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX53_AUDMUX_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
+ MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
+ MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
+ MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
+ >;
};
pinctrl_can1: can1grp {
- fsl,pins = <MX53_CAN1_PINGRP3>;
+ fsl,pins = <
+ MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
+ MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
+ >;
};
pinctrl_can2: can2grp {
- fsl,pins = <MX53_CAN2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
+ MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
+ >;
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX53_ESDHC1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX53_FEC_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX53_I2C1_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
+ MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX53_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
+ MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX53_I2C3_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
+ MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
+ >;
};
pinctrl_ipu_disp1: ipudisp1grp {
- fsl,pins = <MX53_IPU_DISP1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
+ MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
+ MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
+ MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
+ MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
+ MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
+ MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
+ MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
+ MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
+ MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
+ MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
+ MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
+ MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
+ MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
+ MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
+ MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
+ MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
+ MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
+ MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
+ MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
+ MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
+ MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
+ MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
+ MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
+ MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
+ MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
+ MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
+ MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
+ MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
+ MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
+ MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
+ MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
+ >;
};
pinctrl_nand: nandgrp {
- fsl,pins = <MX53_NAND_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
+ MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
+ MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
+ MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
+ MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
+ MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
+ MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
+ MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
+ MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
+ MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
+ MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
+ MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
+ MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
+ MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
+ MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
+ >;
};
pinctrl_pwm1: pwm1grp {
- fsl,pins = <MX53_PWM1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX53_UART1_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX53_UART2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+ >;
};
pinctrl_uart3: uart3grp {
- fsl,pins = <MX53_UART3_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
+ MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
+ MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx53-pingrp.h b/arch/arm/boot/dts/imx53-pingrp.h
deleted file mode 100644
index ac8e73d..0000000
--- a/arch/arm/boot/dts/imx53-pingrp.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX53_PINGRP_H
-#define __DTS_IMX53_PINGRP_H
-
-#include "imx53-pinfunc.h"
-
-#define MX53_AUDMUX_PINGRP1 \
- MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 \
- MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 \
- MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 \
- MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
-
-#define MX53_AUDMUX_PINGRP2 \
- MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 \
- MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 \
- MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 \
- MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
-
-#define MX53_AUDMUX_PINGRP3 \
- MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 \
- MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 \
- MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 \
- MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
-
-#define MX53_CAN1_PINGRP1 \
- MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000 \
- MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
-
-#define MX53_CAN1_PINGRP2 \
- MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 \
- MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
-
-#define MX53_CAN1_PINGRP3 \
- MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 \
- MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
-
-#define MX53_CAN2_PINGRP1 \
- MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 \
- MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
-
-
-#define MX53_CSI_PINGRP1 \
- MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5 \
- MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 \
- MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 \
- MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 \
- MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 \
- MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 \
- MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 \
- MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 \
- MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 \
- MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 \
- MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 \
- MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 \
- MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5 \
- MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5 \
- MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5 \
- MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5 \
- MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5 \
- MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5 \
- MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5 \
- MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5 \
- MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
-
-#define MX53_CSI_PINGRP2 \
- MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 \
- MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 \
- MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 \
- MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 \
- MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 \
- MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 \
- MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 \
- MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 \
- MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 \
- MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 \
- MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
-
-#define MX53_CSPI_PINGRP1 \
- MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 \
- MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 \
- MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
-
-#define MX53_CSPI_PINGRP2 \
- MX53_PAD_EIM_D22__CSPI_MISO 0x1d5 \
- MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5 \
- MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
-
-#define MX53_ECSPI1_PINGRP1 \
- MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 \
- MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 \
- MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
-
-#define MX53_ECSPI1_PINGRP2 \
- MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 \
- MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 \
- MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 \
- MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 \
- MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 \
- MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
-
-#define MX53_ECSPI2_PINGRP1 \
- MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000 \
- MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000 \
- MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
-
-#define MX53_ESDHC1_PINGRP1 \
- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 \
- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 \
- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 \
- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 \
- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 \
- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
-
-#define MX53_ESDHC1_PINGRP2 \
- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 \
- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 \
- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 \
- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 \
- MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 \
- MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 \
- MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 \
- MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 \
- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 \
- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
-
-#define MX53_ESDHC2_PINGRP1 \
- MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 \
- MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 \
- MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 \
- MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 \
- MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 \
- MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
-
-#define MX53_ESDHC3_PINGRP1 \
- MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 \
- MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 \
- MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 \
- MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 \
- MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 \
- MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 \
- MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 \
- MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 \
- MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 \
- MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
-
-#define MX53_FEC_PINGRP1 \
- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 \
- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 \
- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 \
- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 \
- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 \
- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 \
- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 \
- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 \
- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 \
- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
-
-#define MX53_FEC_PINGRP2 \
- MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 \
- MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 \
- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 \
- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 \
- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 \
- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 \
- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 \
- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 \
- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 \
- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 \
- MX53_PAD_KEY_ROW1__FEC_COL 0x80000000 \
- MX53_PAD_KEY_COL3__FEC_CRS 0x80000000 \
- MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000 \
- MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000 \
- MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000 \
- MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000 \
- MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000 \
- MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
-
-#define MX53_I2C1_PINGRP1 \
- MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 \
- MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
-
-#define MX53_I2C1_PINGRP2 \
- MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 \
- MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
-
-#define MX53_I2C2_PINGRP1 \
- MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 \
- MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
-
-#define MX53_I2C2_PINGRP2 \
- MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 \
- MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
-
-#define MX53_I2C3_PINGRP1 \
- MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 \
- MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
-
-#define MX53_I2C3_PINGRP2 \
- MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000 \
- MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
-
-#define MX53_IPU_DISP0_PINGRP1 \
- MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 \
- MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 \
- MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 \
- MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 \
- MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 \
- MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 \
- MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 \
- MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 \
- MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 \
- MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 \
- MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 \
- MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 \
- MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 \
- MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 \
- MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 \
- MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 \
- MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 \
- MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 \
- MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 \
- MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 \
- MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 \
- MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 \
- MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 \
- MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 \
- MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 \
- MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 \
- MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 \
- MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
-
-#define MX53_IPU_DISP1_PINGRP1 \
- MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 \
- MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 \
- MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 \
- MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 \
- MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 \
- MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 \
- MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 \
- MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 \
- MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 \
- MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 \
- MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 \
- MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 \
- MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 \
- MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 \
- MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 \
- MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 \
- MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 \
- MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 \
- MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 \
- MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 \
- MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 \
- MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 \
- MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 \
- MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 \
- MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 \
- MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 \
- MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 \
- MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 \
- MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 \
- MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 \
- MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 \
- MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
-
-#define MX53_IPU_DISP2_PINGRP1 \
- MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 \
- MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 \
- MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 \
- MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 \
- MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 \
- MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 \
- MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 \
- MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 \
- MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 \
- MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
-
-#define MX53_NAND_PINGRP1 \
- MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 \
- MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 \
- MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 \
- MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 \
- MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 \
- MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 \
- MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 \
- MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 \
- MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 \
- MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 \
- MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 \
- MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 \
- MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 \
- MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 \
- MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
-
-#define MX53_OWIRE_PINGRP1 \
- MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
-
-#define MX53_PWM1_PINGRP1 \
- MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
-
-#define MX53_PWM2_PINGRP1 \
- MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
-
-#define MX53_UART1_PINGRP1 \
- MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 \
- MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
-
-#define MX53_UART1_PINGRP2 \
- MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 \
- MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
-
-#define MX53_UART1_PINGRP3 \
- MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 \
- MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
-
-#define MX53_UART2_PINGRP1 \
- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 \
- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
-
-#define MX53_UART2_PINGRP2 \
- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 \
- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 \
- MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 \
- MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
-
-#define MX53_UART3_PINGRP1 \
- MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 \
- MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 \
- MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 \
- MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
-
-#define MX53_UART3_PINGRP2 \
- MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 \
- MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
-
-#define MX53_UART4_PINGRP1 \
- MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 \
- MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
-
-#define MX53_UART5_PINGRP1 \
- MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4 \
- MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
-
-#endif /* __DTS_IMX53_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 4c04459..8595169 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -170,35 +170,107 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX53_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
+ MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
+ MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
+ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
+ >;
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX53_ESDHC1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ >;
};
pinctrl_esdhc3: esdhc3grp {
- fsl,pins = <MX53_ESDHC3_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX53_FEC_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX53_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
+ MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX53_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
+ >;
};
pinctrl_ipu_disp0: ipudisp0grp {
- fsl,pins = <MX53_IPU_DISP0_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX53_UART1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
+ MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index e84decf..5ec1590 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -118,43 +118,100 @@
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX53_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
+ MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
+ MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
+ >;
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX53_ESDHC1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ >;
};
pinctrl_esdhc2: esdhc2grp {
- fsl,pins = <MX53_ESDHC2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
+ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
+ >;
};
pinctrl_esdhc3: esdhc3grp {
- fsl,pins = <MX53_ESDHC3_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX53_FEC_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX53_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
+ MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX53_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX53_UART1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
+ MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX53_UART2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+ >;
};
pinctrl_uart3: uart3grp {
- fsl,pins = <MX53_UART3_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
+ MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
+ MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index b6483c9..4f1f0e2 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -92,27 +92,53 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX53_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
+ MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
+ MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
+ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
+ >;
};
pinctrl_can1: can1grp {
- fsl,pins = <MX53_CAN1_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
+ MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
+ >;
};
pinctrl_can2: can2grp {
- fsl,pins = <MX53_CAN2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
+ MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
+ >;
};
pinctrl_cspi: cspigrp {
- fsl,pins = <MX53_CSPI_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
+ MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
+ MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
+ >;
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX53_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
+ MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
+ MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
+ >;
};
pinctrl_esdhc2: esdhc2grp {
- fsl,pins = <MX53_ESDHC2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
+ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
+ >;
};
pinctrl_esdhc2_cdwp: esdhc2cdwp {
@@ -123,31 +149,68 @@
};
pinctrl_esdhc3: esdhc3grp {
- fsl,pins = <MX53_ESDHC3_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX53_FEC_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX53_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX53_I2C3_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
+ MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX53_UART1_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX53_UART2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+ >;
};
pinctrl_uart3: uart3grp {
- fsl,ps = <MX53_UART3_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts
index 61244cf..7f6711a 100644
--- a/arch/arm/boot/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -82,15 +82,30 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX53_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
+ MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
+ MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
+ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
+ >;
};
pinctrl_esdhc2: esdhc2grp {
- fsl,pins = <MX53_ESDHC2_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
+ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
+ >;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX53_I2C3_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
+ MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
index 04a2895..ba689fb 100644
--- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
+++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
@@ -68,23 +68,60 @@
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX53_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
+ MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
+ MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX53_FEC_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX53_I2C1_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
+ MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX53_UART1_PINGRP2>;
+ fsl,pins = <
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
+ >;
};
pinctrl_nand: nandgrp {
- fsl,pins = <MX53_NAND_PINGRP1>;
+ fsl,pins = <
+ MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
+ MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
+ MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
+ MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
+ MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
+ MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
+ MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
+ MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
+ MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
+ MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
+ MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
+ MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
+ MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
+ MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
+ MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 90359da..0e5c466 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -11,8 +11,8 @@
*/
#include "skeleton.dtsi"
-#include "imx53-pingrp.h"
#include <dt-bindings/clock/imx5-clock.h>
+#include "imx53-pinfunc.h"
/ {
aliases {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/9] ARM: dts: imx51: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
` (2 preceding siblings ...)
2014-01-25 16:43 ` [PATCH 3/9] ARM: dts: imx53: " Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-25 16:43 ` [PATCH 5/9] ARM: dts: imx50: " Shawn Guo
` (6 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in imx51-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx51-apf51.dts | 26 +-
arch/arm/boot/dts/imx51-apf51dev.dts | 64 ++++-
arch/arm/boot/dts/imx51-babbage.dts | 142 +++++++++--
arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | 26 +-
.../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 31 ++-
arch/arm/boot/dts/imx51-pingrp.h | 249 --------------------
arch/arm/boot/dts/imx51.dtsi | 2 +-
7 files changed, 261 insertions(+), 279 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx51-pingrp.h
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 80840da..e88b2a6 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -44,11 +44,33 @@
&iomuxc {
imx51-apf51 {
pinctrl_fec: fecgrp {
- fsl,pins = <MX51_FEC_PINGRP2>;
+ fsl,pins = <
+ MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
+ MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
+ MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
+ MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
+ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
+ MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
+ MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
+ MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
+ MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
+ MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
+ MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
+ MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
+ MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
+ MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
+ MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
+ MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
+ MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
+ >;
};
pinctrl_uart3: uart3grp {
- fsl,pins = <MX51_UART3_PINGRP2>;
+ fsl,pins = <
+ MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
+ MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index f36a3aa..c29cfa9 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -124,27 +124,79 @@
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX51_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
+ >;
};
pinctrl_ecspi2: ecspi2grp {
- fsl,pins = <MX51_ECSPI2_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
+ MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
+ MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
+ >;
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX51_ESDHC1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
+ MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
+ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
+ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
+ MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
+ MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+ >;
};
pinctrl_esdhc2: esdhc2grp {
- fsl,pins = <MX51_ESDHC2_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
+ MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
+ MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
+ MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
+ MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
+ MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX51_I2C2_PINGRP2>;
+ fsl,pins = <
+ MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
+ MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
+ >;
};
pinctrl_ipu_disp1: ipudisp1grp {
- fsl,pins = <MX51_IPU_DISP1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
+ MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
+ MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
+ MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
+ MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
+ MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
+ MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
+ MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
+ MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
+ MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
+ MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
+ MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
+ MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
+ MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
+ MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
+ MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
+ MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
+ MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
+ MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
+ MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
+ MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
+ MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
+ MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
+ MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
+ MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
+ MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 483178a..56e97d8 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -283,62 +283,176 @@
};
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX51_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
+ MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
+ MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
+ MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
+ >;
};
pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <MX51_ECSPI1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
+ >;
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX51_ESDHC1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
+ MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
+ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
+ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
+ MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
+ MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+ >;
};
pinctrl_esdhc2: esdhc2grp {
- fsl,pins = <MX51_ESDHC2_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
+ MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
+ MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
+ MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
+ MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
+ MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
+ >;
};
pinctrl_fec: fecgrp {
fsl,pins = <
- MX51_FEC_PINGRP1
+ MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
+ MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
+ MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
+ MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
+ MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
+ MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
+ MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
+ MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
+ MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
+ MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
+ MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
+ MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
+ MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
+ MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
+ MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
>;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX51_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
+ MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
+ >;
};
pinctrl_ipu_disp1: ipudisp1grp {
- fsl,pins = <MX51_IPU_DISP1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
+ MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
+ MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
+ MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
+ MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
+ MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
+ MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
+ MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
+ MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
+ MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
+ MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
+ MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
+ MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
+ MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
+ MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
+ MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
+ MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
+ MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
+ MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
+ MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
+ MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
+ MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
+ MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
+ MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
+ MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
+ MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
+ >;
};
pinctrl_ipu_disp2: ipudisp2grp {
- fsl,pins = <MX51_IPU_DISP2_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
+ MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
+ MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
+ MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
+ MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
+ MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
+ MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
+ MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
+ MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
+ MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
+ MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
+ MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
+ MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
+ MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
+ MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
+ MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
+ MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
+ MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
+ MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
+ MX51_PAD_DI_GP4__DI2_PIN15 0x5
+ >;
};
pinctrl_kpp: kppgrp {
- fsl,pins = <MX51_KPP_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
+ MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
+ MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
+ MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
+ MX51_PAD_KEY_COL0__KEY_COL0 0xe8
+ MX51_PAD_KEY_COL1__KEY_COL1 0xe8
+ MX51_PAD_KEY_COL2__KEY_COL2 0xe8
+ MX51_PAD_KEY_COL3__KEY_COL3 0xe8
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX51_UART1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
+ MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+ >;
};
pinctrl_uart1_rtscts: uart1rtsctsgrp {
- fsl,pins = <MX51_UART1_RTSCTS_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
+ MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX51_UART2_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
+ MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
+ >;
};
pinctrl_uart3: uart3grp {
- fsl,pins = <MX51_UART3_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_EIM_D25__UART3_RXD 0x1c5
+ MX51_PAD_EIM_D26__UART3_TXD 0x1c5
+ >;
};
pinctrl_uart3_rtscts: uart3rtsctsgrp {
- fsl,pins = <MX51_UART3_RTSCTS_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_EIM_D27__UART3_RTS 0x1c5
+ MX51_PAD_EIM_D24__UART3_CTS 0x1c5
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
index b22841a..9b3acf6 100644
--- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
+++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
@@ -54,11 +54,33 @@
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX51_FEC_PINGRP2>;
+ fsl,pins = <
+ MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
+ MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
+ MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
+ MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
+ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
+ MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
+ MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
+ MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
+ MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
+ MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
+ MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
+ MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
+ MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
+ MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
+ MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
+ MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
+ MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX51_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed
+ MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index 6774c66..62c67cd9 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -81,23 +81,44 @@
&iomuxc {
imx51-eukrea {
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX51_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
+ MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
+ MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
+ MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
+ >;
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX51_ESDHC1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
+ MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
+ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
+ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
+ MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
+ MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX51_UART1_PINGRP1>;
+ fsl,pins = <
+ MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
+ MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+ >;
};
pinctrl_uart3: uart3grp {
- fsl,pins = <MX51_UART3_PINGRP2>;
+ fsl,pins = <
+ MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
+ MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
+ >;
};
pinctrl_uart3_rtscts: uart3rtsctsgrp {
- fsl,pins = <MX51_UART3_RTSCTS_PINGRP2>;
+ fsl,pins = <
+ MX51_PAD_KEY_COL4__UART3_RTS 0x1c5
+ MX51_PAD_KEY_COL5__UART3_CTS 0x1c5
+ >;
};
pinctrl_backlight_1: backlightgrp-1 {
diff --git a/arch/arm/boot/dts/imx51-pingrp.h b/arch/arm/boot/dts/imx51-pingrp.h
deleted file mode 100644
index f63267b..0000000
--- a/arch/arm/boot/dts/imx51-pingrp.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX51_PINGRP_H
-#define __DTS_IMX51_PINGRP_H
-
-#include "imx51-pinfunc.h"
-
-#define MX51_AUDMUX_PINGRP1 \
- MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 \
- MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 \
- MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 \
- MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
-
-#define MX51_FEC_PINGRP1 \
- MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 \
- MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 \
- MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 \
- MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 \
- MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 \
- MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 \
- MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 \
- MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 \
- MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 \
- MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 \
- MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 \
- MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 \
- MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 \
- MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 \
- MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 \
- MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 \
- MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
-
-#define MX51_FEC_PINGRP2 \
- MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 \
- MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 \
- MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 \
- MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 \
- MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 \
- MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 \
- MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 \
- MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 \
- MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 \
- MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 \
- MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 \
- MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 \
- MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 \
- MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 \
- MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 \
- MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 \
- MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 \
- MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
-
-#define MX51_ECSPI1_PINGRP1 \
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 \
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 \
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
-
-#define MX51_ECSPI2_PINGRP1 \
- MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 \
- MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 \
- MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
-
-#define MX51_ESDHC1_PINGRP1 \
- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 \
- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 \
- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 \
- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 \
- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 \
- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
-
-#define MX51_ESDHC2_PINGRP1 \
- MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 \
- MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 \
- MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 \
- MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 \
- MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 \
- MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
-
-#define MX51_I2C1_PINGRP1 \
- MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed \
- MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
-
-#define MX51_I2C2_PINGRP1 \
- MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed \
- MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
-
-#define MX51_I2C2_PINGRP2 \
- MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed \
- MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
-
-#define MX51_I2C2_PINGRP3 \
- MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed \
- MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
-
-#define MX51_IPU_DISP1_PINGRP1 \
- MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 \
- MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 \
- MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 \
- MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 \
- MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 \
- MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 \
- MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 \
- MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 \
- MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 \
- MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 \
- MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 \
- MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 \
- MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 \
- MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 \
- MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 \
- MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 \
- MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 \
- MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 \
- MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 \
- MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 \
- MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 \
- MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 \
- MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 \
- MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 \
- MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 \
- MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
-
-#define MX51_IPU_DISP2_PINGRP1 \
- MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 \
- MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 \
- MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 \
- MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 \
- MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 \
- MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 \
- MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 \
- MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 \
- MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 \
- MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 \
- MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 \
- MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 \
- MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 \
- MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 \
- MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 \
- MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 \
- MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 \
- MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 \
- MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 \
- MX51_PAD_DI_GP4__DI2_PIN15 0x5
-
-#define MX51_KPP_PINGRP1 \
- MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 \
- MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 \
- MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 \
- MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 \
- MX51_PAD_KEY_COL0__KEY_COL0 0xe8 \
- MX51_PAD_KEY_COL1__KEY_COL1 0xe8 \
- MX51_PAD_KEY_COL2__KEY_COL2 0xe8 \
- MX51_PAD_KEY_COL3__KEY_COL3 0xe8
-
-#define MX51_PATA_PINGRP1 \
- MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 \
- MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 \
- MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 \
- MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 \
- MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 \
- MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 \
- MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 \
- MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 \
- MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 \
- MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 \
- MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 \
- MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 \
- MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 \
- MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 \
- MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 \
- MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 \
- MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 \
- MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 \
- MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 \
- MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 \
- MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 \
- MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 \
- MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 \
- MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 \
- MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 \
- MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 \
- MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 \
- MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 \
- MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
-
-#define MX51_UART1_PINGRP1 \
- MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 \
- MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
-
-#define MX51_UART1_RTSCTS_PINGRP1 \
- MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 \
- MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
-
-#define MX51_UART2_PINGRP1 \
- MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 \
- MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
-
-#define MX51_UART3_PINGRP1 \
- MX51_PAD_EIM_D25__UART3_RXD 0x1c5 \
- MX51_PAD_EIM_D26__UART3_TXD 0x1c5
-
-#define MX51_UART3_RTSCTS_PINGRP1 \
- MX51_PAD_EIM_D27__UART3_RTS 0x1c5 \
- MX51_PAD_EIM_D24__UART3_CTS 0x1c5
-
-#define MX51_UART3_PINGRP2 \
- MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 \
- MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
-
-#define MX51_UART3_RTSCTS_PINGRP2 \
- MX51_PAD_KEY_COL4__UART3_RTS 0x1c5 \
- MX51_PAD_KEY_COL5__UART3_CTS 0x1c5
-
-#define MX51_USBH1_PINGRP1 \
- MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 \
- MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 \
- MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 \
- MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 \
- MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 \
- MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 \
- MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 \
- MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 \
- MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 \
- MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 \
- MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 \
- MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
-
-#define MX51_USBH2_PINGRP1 \
- MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 \
- MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 \
- MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 \
- MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 \
- MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 \
- MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 \
- MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 \
- MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 \
- MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 \
- MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 \
- MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 \
- MX51_PAD_EIM_A26__USBH2_STP 0x1e5
-
-#endif /* __DTS_IMX51_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 3291e55..f10d213 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -11,7 +11,7 @@
*/
#include "skeleton.dtsi"
-#include "imx51-pingrp.h"
+#include "imx51-pinfunc.h"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 5/9] ARM: dts: imx50: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
` (3 preceding siblings ...)
2014-01-25 16:43 ` [PATCH 4/9] ARM: dts: imx51: " Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-25 16:43 ` [PATCH 6/9] ARM: dts: imx35: " Shawn Guo
` (5 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in imx50-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx50-evk.dts | 28 +++++++-
arch/arm/boot/dts/imx50-pingrp.h | 146 --------------------------------------
arch/arm/boot/dts/imx50.dtsi | 2 +-
3 files changed, 26 insertions(+), 150 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx50-pingrp.h
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
index a859264..1b22512 100644
--- a/arch/arm/boot/dts/imx50-evk.dts
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -61,15 +61,37 @@
&iomuxc {
imx50-evk {
pinctrl_cspi: cspigrp {
- fsl,pins = <MX50_CSPI_PINGRP1>;
+ fsl,pins = <
+ MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
+ MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
+ MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
+ MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
+ MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4
+ >;
};
pinctrl_fec: fecgrp {
- fsl,pins = <MX50_FEC_PINGRP1>;
+ fsl,pins = <
+ MX50_PAD_SSI_RXFS__FEC_MDC 0x80
+ MX50_PAD_SSI_RXC__FEC_MDIO 0x80
+ MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
+ MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
+ MX50_PAD_DISP_D2__FEC_RX_DV 0x80
+ MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
+ MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
+ MX50_PAD_DISP_D5__FEC_TX_EN 0x80
+ MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
+ MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX50_UART1_PINGRP1>;
+ fsl,pins = <
+ MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
+ MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
+ MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
+ MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx50-pingrp.h b/arch/arm/boot/dts/imx50-pingrp.h
deleted file mode 100644
index 0f4ce8c..0000000
--- a/arch/arm/boot/dts/imx50-pingrp.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX50_PINGRP_H
-#define __DTS_IMX50_PINGRP_H
-
-#include "imx50-pinfunc.h"
-
-#define MX50_CSPI_PINGRP1 \
- MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00 \
- MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 \
- MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 \
- MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 \
- MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4
-
-#define MX50_ECSPI1_PINGRP1 \
- MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x00 \
- MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x00 \
- MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x00 \
- MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x00
-
-#define MX50_ESDHC1_PINGRP1 \
- MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4 \
- MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4 \
- MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4 \
- MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4 \
- MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 \
- MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4
-
-#define MX50_ESDHC1_PINGRP2 \
- MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4 \
- MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4 \
- MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4 \
- MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4 \
- MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x1d4 \
- MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x1d4 \
- MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x1d4 \
- MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x1d4 \
- MX50_PAD_SD1_CMD__ESDHC1_CMD 0x14 \
- MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4
-
-#define MX50_ESDHC2_PINGRP1 \
- MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 \
- MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 \
- MX50_PAD_SD2_D0__ESDHC2_DAT0 0x1d4 \
- MX50_PAD_SD2_D1__ESDHC2_DAT1 0x1d4 \
- MX50_PAD_SD2_D2__ESDHC2_DAT2 0x1d4 \
- MX50_PAD_SD2_D3__ESDHC2_DAT3 0x1d4 \
- MX50_PAD_SD2_D4__ESDHC2_DAT4 0x1d4 \
- MX50_PAD_SD2_D5__ESDHC2_DAT5 0x1d4 \
- MX50_PAD_SD2_D6__ESDHC2_DAT6 0x1d4 \
- MX50_PAD_SD2_D7__ESDHC2_DAT7 0x1d4
-
-#define MX50_ESDHC3_PINGRP1 \
- MX50_PAD_SD3_D0__ESDHC3_DAT0 0x1d4 \
- MX50_PAD_SD3_D1__ESDHC3_DAT1 0x1d4 \
- MX50_PAD_SD3_D2__ESDHC3_DAT2 0x1d4 \
- MX50_PAD_SD3_D3__ESDHC3_DAT3 0x1d4 \
- MX50_PAD_SD3_D4__ESDHC3_DAT4 0x1d4 \
- MX50_PAD_SD3_D5__ESDHC3_DAT5 0x1d4 \
- MX50_PAD_SD3_D6__ESDHC3_DAT6 0x1d4 \
- MX50_PAD_SD3_D7__ESDHC3_DAT7 0x1d4 \
- MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 \
- MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4
-
-#define MX50_FEC_PINGRP1 \
- MX50_PAD_SSI_RXFS__FEC_MDC 0x80 \
- MX50_PAD_SSI_RXC__FEC_MDIO 0x80 \
- MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 \
- MX50_PAD_DISP_D1__FEC_RX_ERR 0x80 \
- MX50_PAD_DISP_D2__FEC_RX_DV 0x80 \
- MX50_PAD_DISP_D3__FEC_RDATA_1 0x80 \
- MX50_PAD_DISP_D4__FEC_RDATA_0 0x80 \
- MX50_PAD_DISP_D5__FEC_TX_EN 0x80 \
- MX50_PAD_DISP_D6__FEC_TDATA_1 0x80 \
- MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
-
-#define MX50_FEC_PINGRP2 \
- MX50_PAD_I2C3_SCL__FEC_MDC 0x80 \
- MX50_PAD_I2C3_SDA__FEC_MDIO 0x80 \
- MX50_PAD_DISP_D0__FEC_TX_CLK 0x80 \
- MX50_PAD_DISP_D10__FEC_RX_DV 0x80 \
- MX50_PAD_DISP_D11__FEC_RDATA_1 0x80 \
- MX50_PAD_DISP_D12__FEC_RDATA_0 0x80 \
- MX50_PAD_DISP_D13__FEC_TX_EN 0x80 \
- MX50_PAD_DISP_D14__FEC_TDATA_1 0x80 \
- MX50_PAD_DISP_D15__FEC_TDATA_0 0x80
-
-#define MX50_I2C1_PINGRP1 \
- MX50_PAD_I2C1_SDA__I2C1_SDA 0x12c \
- MX50_PAD_I2C1_SCL__I2C1_SCL 0x12c
-
-#define MX50_I2C2_PINGRP1 \
- MX50_PAD_I2C2_SDA__I2C2_SDA 0x12c \
- MX50_PAD_I2C2_SCL__I2C2_SCL 0x12c
-
-#define MX50_I2C3_PINGRP1 \
- MX50_PAD_I2C3_SDA__I2C3_SDA 0x12c \
- MX50_PAD_I2C3_SCL__I2C3_SCL 0x12c
-
-#define MX50_OWIRE_PINGRP1 \
- MX50_PAD_OWIRE__OWIRE_LINE 0x84
-
-#define MX50_UART1_PINGRP1 \
- MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4 \
- MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4 \
- MX50_PAD_UART1_RTS__UART1_RTS 0x1e4 \
- MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
-
-#define MX50_UART2_PINGRP1 \
- MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 \
- MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 \
- MX50_PAD_UART2_RTS__UART2_RTS 0x1e4 \
- MX50_PAD_UART2_CTS__UART2_CTS 0x1e4
-
-#define MX50_UART2_PINGRP2 \
- MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x1e4 \
- MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x1e4 \
- MX50_PAD_I2C2_SDA__UART2_RTS 0x1e4 \
- MX50_PAD_I2C2_SCL__UART2_CTS 0x1e4
-
-#define MX50_UART3_PINGRP1 \
- MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x1e4 \
- MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x1e4 \
- MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x1e4 \
- MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x1e4
-
-#define MX50_UART4_PINGRP1 \
- MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x1e4 \
- MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x1e4 \
- MX50_PAD_ECSPI1_MISO__UART4_RTS 0x1e4 \
- MX50_PAD_ECSPI1_SS0__UART4_CTS 0x1e4
-
-#define MX50_UART5_PINGRP1 \
- MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x1e4 \
- MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x1e4 \
- MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x1e4 \
- MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x1e4
-
-#endif /* __DTS_IMX50_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 01c0499..7152472 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -12,7 +12,7 @@
*/
#include "skeleton.dtsi"
-#include "imx50-pingrp.h"
+#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
/ {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 6/9] ARM: dts: imx35: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
` (4 preceding siblings ...)
2014-01-25 16:43 ` [PATCH 5/9] ARM: dts: imx50: " Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-25 16:43 ` [PATCH 7/9] ARM: dts: imx25: " Shawn Guo
` (4 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in imx35-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx35-pingrp.h | 104 --------------------------------------
arch/arm/boot/dts/imx35.dtsi | 1 -
2 files changed, 105 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx35-pingrp.h
diff --git a/arch/arm/boot/dts/imx35-pingrp.h b/arch/arm/boot/dts/imx35-pingrp.h
deleted file mode 100644
index 2406e7e..0000000
--- a/arch/arm/boot/dts/imx35-pingrp.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright 2013 Eukr?a Electromatique <denis@eukrea.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX35_PINGRP_H
-#define __DTS_IMX35_PINGRP_H
-
-#define MX35_AUDMUX_PINGRP1 \
- MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000 \
- MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000 \
- MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000 \
- MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000
-
-#define MX35_CAN1_PINGRP1 \
- MX35_PAD_I2C2_CLK__CAN1_TXCAN 0x1c0 \
- MX35_PAD_I2C2_DAT__CAN1_RXCAN 0x1c0
-
-#define MX35_CAN2_PINGRP1 \
- MX35_PAD_TX5_RX0__CAN2_TXCAN 0x1c0 \
- MX35_PAD_TX4_RX1__CAN2_RXCAN 0x1c0
-
-#define MX35_ESDHC1_PINGRP1 \
- MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 \
- MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 \
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 \
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 \
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 \
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
-
-#define MX35_FEC_PINGRP1 \
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 \
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000 \
- MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 \
- MX35_PAD_FEC_COL__FEC_COL 0x80000000 \
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000 \
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000 \
- MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 \
- MX35_PAD_FEC_MDC__FEC_MDC 0x80000000 \
- MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000 \
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000 \
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000 \
- MX35_PAD_FEC_CRS__FEC_CRS 0x80000000 \
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000 \
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000 \
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000 \
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000 \
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000 \
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000
-
-#define MX35_I2C1_PINGRP1 \
- MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000 \
- MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000
-
-#define MX35_I2C3_PINGRP1 \
- MX35_PAD_ATA_DATA12__I2C3_SCL 0x80000000 \
- MX35_PAD_ATA_DATA13__I2C3_SDA 0x80000000
-
-#define MX35_IPU_PINGRP1 \
- MX35_PAD_LD0__IPU_DISPB_DAT_0 0x80000000 \
- MX35_PAD_LD1__IPU_DISPB_DAT_1 0x80000000 \
- MX35_PAD_LD2__IPU_DISPB_DAT_2 0x80000000 \
- MX35_PAD_LD3__IPU_DISPB_DAT_3 0x80000000 \
- MX35_PAD_LD4__IPU_DISPB_DAT_4 0x80000000 \
- MX35_PAD_LD5__IPU_DISPB_DAT_5 0x80000000 \
- MX35_PAD_LD6__IPU_DISPB_DAT_6 0x80000000 \
- MX35_PAD_LD7__IPU_DISPB_DAT_7 0x80000000 \
- MX35_PAD_LD8__IPU_DISPB_DAT_8 0x80000000 \
- MX35_PAD_LD9__IPU_DISPB_DAT_9 0x80000000 \
- MX35_PAD_LD10__IPU_DISPB_DAT_10 0x80000000 \
- MX35_PAD_LD11__IPU_DISPB_DAT_11 0x80000000 \
- MX35_PAD_LD12__IPU_DISPB_DAT_12 0x80000000 \
- MX35_PAD_LD13__IPU_DISPB_DAT_13 0x80000000 \
- MX35_PAD_LD14__IPU_DISPB_DAT_14 0x80000000 \
- MX35_PAD_LD15__IPU_DISPB_DAT_15 0x80000000 \
- MX35_PAD_LD16__IPU_DISPB_DAT_16 0x80000000 \
- MX35_PAD_LD17__IPU_DISPB_DAT_17 0x80000000 \
- MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x80000000 \
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x80000000 \
- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x80000000 \
- MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x80000000 \
- MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x80000000
-
-#define MX35_UART1_PINGRP1 \
- MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 \
- MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
-
-#define MX35_UART1_RTSCTS_PINGRP1 \
- MX35_PAD_CTS1__UART1_CTS 0x1c5 \
- MX35_PAD_RTS1__UART1_RTS 0x1c5
-
-#define MX35_UART2_PINGRP1 \
- MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5 \
- MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5
-
-#define MX35_UART2_RTSCTS_PINGRP1 \
- MX35_PAD_RTS2__UART2_RTS 0x1c5 \
- MX35_PAD_CTS2__UART2_CTS 0x1c5
-
-#endif /* __DTS_IMX35_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index a198b92..88b218f 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -10,7 +10,6 @@
#include "skeleton.dtsi"
#include "imx35-pinfunc.h"
-#include "imx35-pingrp.h"
/ {
aliases {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 7/9] ARM: dts: imx25: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
` (5 preceding siblings ...)
2014-01-25 16:43 ` [PATCH 6/9] ARM: dts: imx35: " Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-25 16:43 ` [PATCH 8/9] ARM: dts: imx27: " Shawn Guo
` (3 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in imx25-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | 17 +++-
.../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 56 ++++++++++++--
arch/arm/boot/dts/imx25-pingrp.h | 81 --------------------
arch/arm/boot/dts/imx25.dtsi | 2 +-
4 files changed, 67 insertions(+), 89 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx25-pingrp.h
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
index 8abd45a..d6f2764 100644
--- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
+++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
@@ -43,11 +43,24 @@
&iomuxc {
imx25-eukrea-cpuimx25 {
pinctrl_fec: fecgrp {
- fsl,pins = <MX25_FEC_PINGRP1>;
+ fsl,pins = <
+ MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
+ MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
+ MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
+ MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
+ MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX25_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
+ MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 30073f8..62fb3da 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -78,11 +78,23 @@
&iomuxc {
imx25-eukrea-mbimxsd25-baseboard {
pinctrl_audmux: audmuxgrp {
- fsl,pins = <MX25_AUDMUX_PINGRP1>;
+ fsl,pins = <
+ MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0
+ MX25_PAD_KPP_COL2__AUD5_TXC 0xe0
+ MX25_PAD_KPP_COL1__AUD5_RXD 0xe0
+ MX25_PAD_KPP_COL0__AUD5_TXD 0xe0
+ >;
};
pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <MX25_ESDHC1_PINGRP1>;
+ fsl,pins = <
+ MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0
+ MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0
+ MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0
+ MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0
+ MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0
+ MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0
+ >;
};
pinctrl_gpiokeys: gpiokeysgrp {
@@ -94,15 +106,49 @@
};
pinctrl_lcdc: lcdcgrp {
- fsl,pins = <MX25_LCDC_PINGRP1>;
+ fsl,pins = <
+ MX25_PAD_LD0__LD0 0x1
+ MX25_PAD_LD1__LD1 0x1
+ MX25_PAD_LD2__LD2 0x1
+ MX25_PAD_LD3__LD3 0x1
+ MX25_PAD_LD4__LD4 0x1
+ MX25_PAD_LD5__LD5 0x1
+ MX25_PAD_LD6__LD6 0x1
+ MX25_PAD_LD7__LD7 0x1
+ MX25_PAD_LD8__LD8 0x1
+ MX25_PAD_LD9__LD9 0x1
+ MX25_PAD_LD10__LD10 0x1
+ MX25_PAD_LD11__LD11 0x1
+ MX25_PAD_LD12__LD12 0x1
+ MX25_PAD_LD13__LD13 0x1
+ MX25_PAD_LD14__LD14 0x1
+ MX25_PAD_LD15__LD15 0x1
+ MX25_PAD_GPIO_E__LD16 0x1
+ MX25_PAD_GPIO_F__LD17 0x1
+ MX25_PAD_HSYNC__HSYNC 0x80000000
+ MX25_PAD_VSYNC__VSYNC 0x80000000
+ MX25_PAD_LSCLK__LSCLK 0x80000000
+ MX25_PAD_OE_ACD__OE_ACD 0x80000000
+ MX25_PAD_CONTRAST__CONTRAST 0x80000000
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX25_UART1_PINGRP1>;
+ fsl,pins = <
+ MX25_PAD_UART1_RTS__UART1_RTS 0xe0
+ MX25_PAD_UART1_CTS__UART1_CTS 0xe0
+ MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
+ MX25_PAD_UART1_RXD__UART1_RXD 0xc0
+ >;
};
pinctrl_uart2: uart2grp {
- fsl,pins = <MX25_UART2_PINGRP1>;
+ fsl,pins = <
+ MX25_PAD_UART2_RXD__UART2_RXD 0x80000000
+ MX25_PAD_UART2_TXD__UART2_TXD 0x80000000
+ MX25_PAD_UART2_RTS__UART2_RTS 0x80000000
+ MX25_PAD_UART2_CTS__UART2_CTS 0x80000000
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx25-pingrp.h b/arch/arm/boot/dts/imx25-pingrp.h
deleted file mode 100644
index 4a35a63..0000000
--- a/arch/arm/boot/dts/imx25-pingrp.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2013 Eukr?a Electromatique <denis@eukrea.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX25_PINGRP_H
-#define __DTS_IMX25_PINGRP_H
-
-#include "imx25-pinfunc.h"
-
-#define MX25_AUDMUX_PINGRP1 \
- MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 \
- MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 \
- MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 \
- MX25_PAD_KPP_COL0__AUD5_TXD 0xe0
-
-#define MX25_ESDHC1_PINGRP1 \
- MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0 \
- MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0 \
- MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0 \
- MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0 \
- MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0 \
- MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0
-
-#define MX25_FEC_PINGRP1 \
- MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 \
- MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 \
- MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 \
- MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 \
- MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 \
- MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 \
- MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 \
- MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 \
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
-
-#define MX25_I2C1_PINGRP1 \
- MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 \
- MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
-
-#define MX25_LCDC_PINGRP1 \
- MX25_PAD_LD0__LD0 0x1 \
- MX25_PAD_LD1__LD1 0x1 \
- MX25_PAD_LD2__LD2 0x1 \
- MX25_PAD_LD3__LD3 0x1 \
- MX25_PAD_LD4__LD4 0x1 \
- MX25_PAD_LD5__LD5 0x1 \
- MX25_PAD_LD6__LD6 0x1 \
- MX25_PAD_LD7__LD7 0x1 \
- MX25_PAD_LD8__LD8 0x1 \
- MX25_PAD_LD9__LD9 0x1 \
- MX25_PAD_LD10__LD10 0x1 \
- MX25_PAD_LD11__LD11 0x1 \
- MX25_PAD_LD12__LD12 0x1 \
- MX25_PAD_LD13__LD13 0x1 \
- MX25_PAD_LD14__LD14 0x1 \
- MX25_PAD_LD15__LD15 0x1 \
- MX25_PAD_GPIO_E__LD16 0x1 \
- MX25_PAD_GPIO_F__LD17 0x1 \
- MX25_PAD_HSYNC__HSYNC 0x80000000 \
- MX25_PAD_VSYNC__VSYNC 0x80000000 \
- MX25_PAD_LSCLK__LSCLK 0x80000000 \
- MX25_PAD_OE_ACD__OE_ACD 0x80000000 \
- MX25_PAD_CONTRAST__CONTRAST 0x80000000
-
-#define MX25_UART1_PINGRP1 \
- MX25_PAD_UART1_RTS__UART1_RTS 0xe0 \
- MX25_PAD_UART1_CTS__UART1_CTS 0xe0 \
- MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 \
- MX25_PAD_UART1_RXD__UART1_RXD 0xc0
-
-#define MX25_UART2_PINGRP1 \
- MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 \
- MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 \
- MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 \
- MX25_PAD_UART2_CTS__UART2_CTS 0x80000000
-
-#endif /* __DTS_IMX25_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 9e9e3b8..32f760e 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -10,7 +10,7 @@
*/
#include "skeleton.dtsi"
-#include "imx25-pingrp.h"
+#include "imx25-pinfunc.h"
/ {
aliases {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 8/9] ARM: dts: imx27: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
` (6 preceding siblings ...)
2014-01-25 16:43 ` [PATCH 7/9] ARM: dts: imx25: " Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-25 16:43 ` [PATCH 9/9] ARM: dts: vf610: " Shawn Guo
` (2 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in imx27-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/imx27-apf27.dts | 26 +++-
arch/arm/boot/dts/imx27-apf27dev.dts | 65 +++++++++-
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 27 ++--
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 26 +++-
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 23 +++-
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 38 +++++-
arch/arm/boot/dts/imx27-pingrp.h | 151 ----------------------
arch/arm/boot/dts/imx27.dtsi | 2 +-
8 files changed, 177 insertions(+), 181 deletions(-)
delete mode 100644 arch/arm/boot/dts/imx27-pingrp.h
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index 8bc75c7..09f57b3 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -37,11 +37,33 @@
&iomuxc {
imx27-apf27 {
pinctrl_fec1: fec1grp {
- fsl,pins = <MX27_FEC1_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+ MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+ MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+ MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+ MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+ MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+ MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+ MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+ MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+ MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+ MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+ MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+ MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+ MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+ MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+ MX27_PAD_ATA_DATA13__FEC_COL 0x0
+ MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+ MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <MX27_UART1_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 2555d80..2b6d489 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -108,7 +108,11 @@
&iomuxc {
imx27-apf27dev {
pinctrl_cspi1: cspi1grp {
- fsl,pins = <MX27_CSPI1_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
+ MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
+ MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
+ >;
};
pinctrl_cspi1_cs: cspi1csgrp {
@@ -116,7 +120,11 @@
};
pinctrl_cspi2: cspi2grp {
- fsl,pins = <MX27_CSPI2_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
+ MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
+ MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
+ >;
};
pinctrl_cspi2_cs: cspi2csgrp {
@@ -136,23 +144,66 @@
};
pinctrl_imxfb1: imxfbgrp {
- fsl,pins = <MX27_FB_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_CLS__CLS 0x0
+ MX27_PAD_CONTRAST__CONTRAST 0x0
+ MX27_PAD_LD0__LD0 0x0
+ MX27_PAD_LD1__LD1 0x0
+ MX27_PAD_LD2__LD2 0x0
+ MX27_PAD_LD3__LD3 0x0
+ MX27_PAD_LD4__LD4 0x0
+ MX27_PAD_LD5__LD5 0x0
+ MX27_PAD_LD6__LD6 0x0
+ MX27_PAD_LD7__LD7 0x0
+ MX27_PAD_LD8__LD8 0x0
+ MX27_PAD_LD9__LD9 0x0
+ MX27_PAD_LD10__LD10 0x0
+ MX27_PAD_LD11__LD11 0x0
+ MX27_PAD_LD12__LD12 0x0
+ MX27_PAD_LD13__LD13 0x0
+ MX27_PAD_LD14__LD14 0x0
+ MX27_PAD_LD15__LD15 0x0
+ MX27_PAD_LD16__LD16 0x0
+ MX27_PAD_LD17__LD17 0x0
+ MX27_PAD_LSCLK__LSCLK 0x0
+ MX27_PAD_OE_ACD__OE_ACD 0x0
+ MX27_PAD_PS__PS 0x0
+ MX27_PAD_REV__REV 0x0
+ MX27_PAD_SPL_SPR__SPL_SPR 0x0
+ MX27_PAD_HSYNC__HSYNC 0x0
+ MX27_PAD_VSYNC__VSYNC 0x0
+ >;
};
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX27_I2C1_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_I2C_DATA__I2C_DATA 0x0
+ MX27_PAD_I2C_CLK__I2C_CLK 0x0
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX27_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+ >;
};
pinctrl_pwm: pwmgrp {
- fsl,pins = <MX27_PWM_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_PWMO__PWMO 0x0
+ >;
};
pinctrl_sdhc2: sdhc2grp {
- fsl,pins = <MX27_SDHC2_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_SD2_CLK__SD2_CLK 0x0
+ MX27_PAD_SD2_CMD__SD2_CMD 0x0
+ MX27_PAD_SD2_D0__SD2_D0 0x0
+ MX27_PAD_SD2_D1__SD2_D1 0x0
+ MX27_PAD_SD2_D2__SD2_D2 0x0
+ MX27_PAD_SD2_D3__SD2_D3 0x0
+ >;
};
pinctrl_sdhc2_cd: sdhc2cdgrp {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 0d65023..04cadfc 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -76,31 +76,42 @@
&iomuxc {
imx27-phycard-s-rdk {
pinctrl_i2c1: i2c1grp {
- fsl,pins = <MX27_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+ >;
};
pinctrl_owire1: owire1grp {
- fsl,pins = <MX27_OWIRE1_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_RTCK__OWIRE 0x0
+ >;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX27_UART1_PINGRP1
- MX27_UART1_RTSCTS_PINGRP1
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX27_UART2_PINGRP1
- MX27_UART2_RTSCTS_PINGRP1
+ MX27_PAD_UART2_TXD__UART2_TXD 0x0
+ MX27_PAD_UART2_RXD__UART2_RXD 0x0
+ MX27_PAD_UART2_CTS__UART2_CTS 0x0
+ MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
- MX27_UART3_PINGRP1
- MX27_UART3_RTSCTS_PINGRP1
+ MX27_PAD_UART3_TXD__UART3_TXD 0x0
+ MX27_PAD_UART3_RXD__UART3_RXD 0x0
+ MX27_PAD_UART3_CTS__UART3_CTS 0x0
+ MX27_PAD_UART3_RTS__UART3_RTS 0x0
>;
};
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
index db8c095..e51e550 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
@@ -32,11 +32,33 @@
&iomuxc {
imx27-phycard-s-som {
pinctrl_fec1: fec1grp {
- fsl,pins = <MX27_FEC1_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+ MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+ MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+ MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+ MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+ MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+ MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+ MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+ MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+ MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+ MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+ MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+ MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+ MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+ MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+ MX27_PAD_ATA_DATA13__FEC_COL 0x0
+ MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+ MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+ >;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX27_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index eaaff00..9f8ad51 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -45,12 +45,19 @@
};
pinctrl_owire1: owire1grp {
- fsl,pins = <MX27_OWIRE1_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_RTCK__OWIRE 0x0
+ >;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
- MX27_SDHC2_PINGRP1
+ MX27_PAD_SD2_CLK__SD2_CLK 0x0
+ MX27_PAD_SD2_CMD__SD2_CMD 0x0
+ MX27_PAD_SD2_D0__SD2_D0 0x0
+ MX27_PAD_SD2_D1__SD2_D1 0x0
+ MX27_PAD_SD2_D2__SD2_D2 0x0
+ MX27_PAD_SD2_D3__SD2_D3 0x0
MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
>;
@@ -58,15 +65,19 @@
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX27_UART1_PINGRP1
- MX27_UART1_RTSCTS_PINGRP1
+ MX27_PAD_UART1_TXD__UART1_TXD 0x0
+ MX27_PAD_UART1_RXD__UART1_RXD 0x0
+ MX27_PAD_UART1_CTS__UART1_CTS 0x0
+ MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX27_UART2_PINGRP1
- MX27_UART2_RTSCTS_PINGRP1
+ MX27_PAD_UART2_TXD__UART2_TXD 0x0
+ MX27_PAD_UART2_RXD__UART2_RXD 0x0
+ MX27_PAD_UART2_CTS__UART2_CTS 0x0
+ MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index c934999..230cfaf 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -186,7 +186,9 @@
imx27_phycore_som {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
- MX27_CSPI1_PINGRP1
+ MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
+ MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
+ MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
>;
@@ -194,17 +196,45 @@
pinctrl_fec1: fec1grp {
fsl,pins = <
- MX27_FEC1_PINGRP1
+ MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+ MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+ MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+ MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+ MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+ MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+ MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+ MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+ MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+ MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+ MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+ MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+ MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+ MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+ MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+ MX27_PAD_ATA_DATA13__FEC_COL 0x0
+ MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+ MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
>;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX27_I2C2_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+ MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+ >;
};
pinctrl_nfc: nfcgrp {
- fsl,pins = <MX27_NFC_PINGRP1>;
+ fsl,pins = <
+ MX27_PAD_NFRB__NFRB 0x0
+ MX27_PAD_NFCLE__NFCLE 0x0
+ MX27_PAD_NFWP_B__NFWP_B 0x0
+ MX27_PAD_NFCE_B__NFCE_B 0x0
+ MX27_PAD_NFALE__NFALE 0x0
+ MX27_PAD_NFRE_B__NFRE_B 0x0
+ MX27_PAD_NFWE_B__NFWE_B 0x0
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/imx27-pingrp.h b/arch/arm/boot/dts/imx27-pingrp.h
deleted file mode 100644
index 57ca02f..0000000
--- a/arch/arm/boot/dts/imx27-pingrp.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __DTS_IMX27_PINGRP_H
-#define __DTS_IMX27_PINGRP_H
-
-#include "imx27-pinfunc.h"
-
-#define MX27_CSPI1_PINGRP1 \
- MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 \
- MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 \
- MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
-
-#define MX27_CSPI2_PINGRP1 \
- MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 \
- MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 \
- MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
-
-#define MX27_CSPI3_PINGRP1 \
- MX27_PAD_SD1_CLK__CSPI3_SCLK 0x0 \
- MX27_PAD_SD1_D0__CSPI3_MISO 0x0 \
- MX27_PAD_SD1_CMD__CSPI3_MOSI 0x0
-
-#define MX27_FB_PINGRP1 \
- MX27_PAD_CLS__CLS 0x0 \
- MX27_PAD_CONTRAST__CONTRAST 0x0 \
- MX27_PAD_LD0__LD0 0x0 \
- MX27_PAD_LD1__LD1 0x0 \
- MX27_PAD_LD2__LD2 0x0 \
- MX27_PAD_LD3__LD3 0x0 \
- MX27_PAD_LD4__LD4 0x0 \
- MX27_PAD_LD5__LD5 0x0 \
- MX27_PAD_LD6__LD6 0x0 \
- MX27_PAD_LD7__LD7 0x0 \
- MX27_PAD_LD8__LD8 0x0 \
- MX27_PAD_LD9__LD9 0x0 \
- MX27_PAD_LD10__LD10 0x0 \
- MX27_PAD_LD11__LD11 0x0 \
- MX27_PAD_LD12__LD12 0x0 \
- MX27_PAD_LD13__LD13 0x0 \
- MX27_PAD_LD14__LD14 0x0 \
- MX27_PAD_LD15__LD15 0x0 \
- MX27_PAD_LD16__LD16 0x0 \
- MX27_PAD_LD17__LD17 0x0 \
- MX27_PAD_LSCLK__LSCLK 0x0 \
- MX27_PAD_OE_ACD__OE_ACD 0x0 \
- MX27_PAD_PS__PS 0x0 \
- MX27_PAD_REV__REV 0x0 \
- MX27_PAD_SPL_SPR__SPL_SPR 0x0 \
- MX27_PAD_HSYNC__HSYNC 0x0 \
- MX27_PAD_VSYNC__VSYNC 0x0
-
-#define MX27_FEC1_PINGRP1 \
- MX27_PAD_SD3_CMD__FEC_TXD0 0x0 \
- MX27_PAD_SD3_CLK__FEC_TXD1 0x0 \
- MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 \
- MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 \
- MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 \
- MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 \
- MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 \
- MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 \
- MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 \
- MX27_PAD_ATA_DATA7__FEC_MDC 0x0 \
- MX27_PAD_ATA_DATA8__FEC_CRS 0x0 \
- MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 \
- MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 \
- MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 \
- MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 \
- MX27_PAD_ATA_DATA13__FEC_COL 0x0 \
- MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 \
- MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-
-#define MX27_I2C1_PINGRP1 \
- MX27_PAD_I2C_DATA__I2C_DATA 0x0 \
- MX27_PAD_I2C_CLK__I2C_CLK 0x0
-
-#define MX27_I2C2_PINGRP1 \
- MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 \
- MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-
-#define MX27_NFC_PINGRP1 \
- MX27_PAD_NFRB__NFRB 0x0 \
- MX27_PAD_NFCLE__NFCLE 0x0 \
- MX27_PAD_NFWP_B__NFWP_B 0x0 \
- MX27_PAD_NFCE_B__NFCE_B 0x0 \
- MX27_PAD_NFALE__NFALE 0x0 \
- MX27_PAD_NFRE_B__NFRE_B 0x0 \
- MX27_PAD_NFWE_B__NFWE_B 0x0
-
-#define MX27_OWIRE1_PINGRP1 \
- MX27_PAD_RTCK__OWIRE 0x0
-
-#define MX27_PWM_PINGRP1 \
- MX27_PAD_PWMO__PWMO 0x0
-
-#define MX27_SDHC1_PINGRP1 \
- MX27_PAD_SD1_CLK__SD1_CLK 0x0 \
- MX27_PAD_SD1_CMD__SD1_CMD 0x0 \
- MX27_PAD_SD1_D0__SD1_D0 0x0 \
- MX27_PAD_SD1_D1__SD1_D1 0x0 \
- MX27_PAD_SD1_D2__SD1_D2 0x0 \
- MX27_PAD_SD1_D3__SD1_D3 0x0
-
-#define MX27_SDHC2_PINGRP1 \
- MX27_PAD_SD2_CLK__SD2_CLK 0x0 \
- MX27_PAD_SD2_CMD__SD2_CMD 0x0 \
- MX27_PAD_SD2_D0__SD2_D0 0x0 \
- MX27_PAD_SD2_D1__SD2_D1 0x0 \
- MX27_PAD_SD2_D2__SD2_D2 0x0 \
- MX27_PAD_SD2_D3__SD2_D3 0x0
-
-#define MX27_SDHC3_PINGRP1 \
- MX27_PAD_SD3_CLK__SD3_CLK 0x0 \
- MX27_PAD_SD3_CMD__SD3_CMD 0x0 \
- MX27_PAD_SD3_D0__SD3_D0 0x0 \
- MX27_PAD_SD3_D1__SD3_D1 0x0 \
- MX27_PAD_SD3_D2__SD3_D2 0x0 \
- MX27_PAD_SD3_D3__SD3_D3 0x0
-
-#define MX27_UART1_PINGRP1 \
- MX27_PAD_UART1_TXD__UART1_TXD 0x0 \
- MX27_PAD_UART1_RXD__UART1_RXD 0x0
-
-#define MX27_UART1_RTSCTS_PINGRP1 \
- MX27_PAD_UART1_CTS__UART1_CTS 0x0 \
- MX27_PAD_UART1_RTS__UART1_RTS 0x0
-
-#define MX27_UART2_PINGRP1 \
- MX27_PAD_UART2_TXD__UART2_TXD 0x0 \
- MX27_PAD_UART2_RXD__UART2_RXD 0x0
-
-#define MX27_UART2_RTSCTS_PINGRP1 \
- MX27_PAD_UART2_CTS__UART2_CTS 0x0 \
- MX27_PAD_UART2_RTS__UART2_RTS 0x0
-
-#define MX27_UART3_PINGRP1 \
- MX27_PAD_UART3_TXD__UART3_TXD 0x0 \
- MX27_PAD_UART3_RXD__UART3_RXD 0x0
-
-#define MX27_UART3_RTSCTS_PINGRP1 \
- MX27_PAD_UART3_CTS__UART3_CTS 0x0 \
- MX27_PAD_UART3_RTS__UART3_RTS 0x0
-
-#endif /* __DTS_IMX27_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 63b1b32..1af8fcf 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -10,7 +10,7 @@
*/
#include "skeleton.dtsi"
-#include "imx27-pingrp.h"
+#include "imx27-pinfunc.h"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 9/9] ARM: dts: vf610: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
` (7 preceding siblings ...)
2014-01-25 16:43 ` [PATCH 8/9] ARM: dts: imx27: " Shawn Guo
@ 2014-01-25 16:43 ` Shawn Guo
2014-01-27 14:04 ` [PATCH 0/9] ARM: dts: imx: " Rob Herring
2014-01-27 17:47 ` Olof Johansson
10 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
We created the pingrp macros in vf610-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards. However, DT maintainers
take it as an abuse of DTC macro support. So let's get rid of it to
make the pins used by given device more intuitive.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/vf610-cosmic.dts | 17 ++++-
arch/arm/boot/dts/vf610-pingrp.h | 127 ------------------------------------
arch/arm/boot/dts/vf610-twr.dts | 42 ++++++++++--
arch/arm/boot/dts/vf610.dtsi | 2 +-
4 files changed, 53 insertions(+), 135 deletions(-)
delete mode 100644 arch/arm/boot/dts/vf610-pingrp.h
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index 432960a..3fd1b74 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -43,11 +43,24 @@
&iomuxc {
vf610-cosmic {
pinctrl_fec1: fec1grp {
- fsl,pins = <VF610_FEC1_PINGRP1>;
+ fsl,pins = <
+ VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
+ VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
+ VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
+ VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
+ VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
+ VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
+ VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
+ VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
+ VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <VF610_UART1_PINGRP1>;
+ fsl,pins = <
+ VF610_PAD_PTB4__UART1_TX 0x21a2
+ VF610_PAD_PTB5__UART1_RX 0x21a1
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/vf610-pingrp.h b/arch/arm/boot/dts/vf610-pingrp.h
deleted file mode 100644
index 0858f4f..0000000
--- a/arch/arm/boot/dts/vf610-pingrp.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_VF610_PINGRP_H
-#define __DTS_VF610_PINGRP_H
-
-#include "vf610-pinfunc.h"
-
-#define VF610_DCU0_PINGRP1 \
- VF610_PAD_PTB8__GPIO_30 0x42 \
- VF610_PAD_PTE0__DCU0_HSYNC 0x42 \
- VF610_PAD_PTE1__DCU0_VSYNC 0x42 \
- VF610_PAD_PTE2__DCU0_PCLK 0x42 \
- VF610_PAD_PTE4__DCU0_DE 0x42 \
- VF610_PAD_PTE5__DCU0_R0 0x42 \
- VF610_PAD_PTE6__DCU0_R1 0x42 \
- VF610_PAD_PTE7__DCU0_R2 0x42 \
- VF610_PAD_PTE8__DCU0_R3 0x42 \
- VF610_PAD_PTE9__DCU0_R4 0x42 \
- VF610_PAD_PTE10__DCU0_R5 0x42 \
- VF610_PAD_PTE11__DCU0_R6 0x42 \
- VF610_PAD_PTE12__DCU0_R7 0x42 \
- VF610_PAD_PTE13__DCU0_G0 0x42 \
- VF610_PAD_PTE14__DCU0_G1 0x42 \
- VF610_PAD_PTE15__DCU0_G2 0x42 \
- VF610_PAD_PTE16__DCU0_G3 0x42 \
- VF610_PAD_PTE17__DCU0_G4 0x42 \
- VF610_PAD_PTE18__DCU0_G5 0x42 \
- VF610_PAD_PTE19__DCU0_G6 0x42 \
- VF610_PAD_PTE20__DCU0_G7 0x42 \
- VF610_PAD_PTE21__DCU0_B0 0x42 \
- VF610_PAD_PTE22__DCU0_B1 0x42 \
- VF610_PAD_PTE23__DCU0_B2 0x42 \
- VF610_PAD_PTE24__DCU0_B3 0x42 \
- VF610_PAD_PTE25__DCU0_B4 0x42 \
- VF610_PAD_PTE26__DCU0_B5 0x42 \
- VF610_PAD_PTE27__DCU0_B6 0x42 \
- VF610_PAD_PTE28__DCU0_B7 0x42
-
-#define VF610_DSPI0_PINGRP1 \
- VF610_PAD_PTB19__DSPI0_CS0 0x1182 \
- VF610_PAD_PTB20__DSPI0_SIN 0x1181 \
- VF610_PAD_PTB21__DSPI0_SOUT 0x1182 \
- VF610_PAD_PTB22__DSPI0_SCK 0x1182
-
-#define VF610_ESDHC1_PINGRP1 \
- VF610_PAD_PTA24__ESDHC1_CLK 0x31ef \
- VF610_PAD_PTA25__ESDHC1_CMD 0x31ef \
- VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef \
- VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef \
- VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef \
- VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef \
- VF610_PAD_PTA7__GPIO_134 0x219d
-
-#define VF610_FEC0_PINGRP1 \
- VF610_PAD_PTA6__RMII_CLKIN 0x30d1 \
- VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 \
- VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 \
- VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 \
- VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 \
- VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 \
- VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 \
- VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 \
- VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 \
- VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
-
-#define VF610_FEC1_PINGRP1 \
- VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 \
- VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 \
- VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 \
- VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 \
- VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 \
- VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 \
- VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 \
- VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 \
- VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 \
-
-#define VF610_I2C0_PINGRP1 \
- VF610_PAD_PTB14__I2C0_SCL 0x30d3 \
- VF610_PAD_PTB15__I2C0_SDA 0x30d3 \
-
-#define VF610_PWM0_PINGRP1 \
- VF610_PAD_PTB0__FTM0_CH0 0x1582 \
- VF610_PAD_PTB1__FTM0_CH1 0x1582 \
- VF610_PAD_PTB2__FTM0_CH2 0x1582 \
- VF610_PAD_PTB3__FTM0_CH3 0x1582 \
- VF610_PAD_PTB6__FTM0_CH6 0x1582 \
- VF610_PAD_PTB7__FTM0_CH7 0x1582
-
-#define VF610_QSPI0_PINGRP1 \
- VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b \
- VF610_PAD_PTD1__QSPI0_A_CS0 0x307f \
- VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073 \
- VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073 \
- VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073 \
- VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b \
- VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b \
- VF610_PAD_PTD8__QSPI0_B_CS0 0x307f \
- VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073 \
- VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073 \
- VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073 \
- VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b
-
-#define VF610_SAI2_PINGRP1 \
- VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed \
- VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee \
- VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed \
- VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed \
- VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed \
- VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed \
- VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
-
-#define VF610_UART1_PINGRP1 \
- VF610_PAD_PTB4__UART1_TX 0x21a2 \
- VF610_PAD_PTB5__UART1_RX 0x21a1
-
-#define VF610_USBVBUS_PINGRP1 \
- VF610_PAD_PTA24__USB1_VBUS_EN 0x219c \
- VF610_PAD_PTA16__USB0_VBUS_EN 0x219c
-
-#endif /* __DTS_VF610_PINGRP_H */
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 80db14e..e3a3805 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -77,23 +77,55 @@
&iomuxc {
vf610-twr {
pinctrl_dspi0: dspi0grp {
- fsl,pins = <VF610_DSPI0_PINGRP1>;
+ fsl,pins = <
+ VF610_PAD_PTB19__DSPI0_CS0 0x1182
+ VF610_PAD_PTB20__DSPI0_SIN 0x1181
+ VF610_PAD_PTB21__DSPI0_SOUT 0x1182
+ VF610_PAD_PTB22__DSPI0_SCK 0x1182
+ >;
};
pinctrl_fec0: fec0grp {
- fsl,pins = <VF610_FEC0_PINGRP1>;
+ fsl,pins = <
+ VF610_PAD_PTA6__RMII_CLKIN 0x30d1
+ VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
+ VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
+ VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
+ VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
+ VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
+ VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
+ VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
+ VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
+ VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
+ >;
};
pinctrl_fec1: fec1grp {
- fsl,pins = <VF610_FEC1_PINGRP1>;
+ fsl,pins = <
+ VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
+ VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
+ VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
+ VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
+ VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
+ VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
+ VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
+ VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
+ VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
+ >;
};
pinctrl_i2c0: i2c0grp {
- fsl,pins = <VF610_I2C0_PINGRP1>;
+ fsl,pins = <
+ VF610_PAD_PTB14__I2C0_SCL 0x30d3
+ VF610_PAD_PTB15__I2C0_SDA 0x30d3
+ >;
};
pinctrl_uart1: uart1grp {
- fsl,pins = <VF610_UART1_PINGRP1>;
+ fsl,pins = <
+ VF610_PAD_PTB4__UART1_TX 0x21a2
+ VF610_PAD_PTB5__UART1_RX 0x21a1
+ >;
};
};
};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index ef8a0ee..183943e 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -8,7 +8,7 @@
*/
#include "skeleton.dtsi"
-#include "vf610-pingrp.h"
+#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
/ {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
` (8 preceding siblings ...)
2014-01-25 16:43 ` [PATCH 9/9] ARM: dts: vf610: " Shawn Guo
@ 2014-01-27 14:04 ` Rob Herring
2014-01-27 17:47 ` Olof Johansson
10 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2014-01-27 14:04 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Jan 25, 2014 at 10:43 AM, Shawn Guo <shawn.guo@linaro.org> wrote:
> Hi Rob,
>
> In order to solve a pinctrl data efficiency problem, we introduced
> pingrp macros [1] in this development cycle as the base of board dts
> support. The whole imx-dt-3.14 pull request has been held by Olof for
> a few weeks because he wants to get a general approval from DT folks
> on this change. But unfortunately it appears that you are not fond of
> this change.
>
> I just spent the day to create a patch series against imx-dt-3.14 to
> remove these pingrp macros. May I get your nod on this quick
> turn-around, so that we do not miss the merge window?
I've only skimmed thru some of the patches, but in general it looks fine to me:
Acked-by: Rob Herring <robh@kernel.org>
Rob
> Hi Olof,
>
> I guess we do not have to shut the door for imx-dt-3.14 if you and DT
> folks are happy with this patch series, which is a quite straight
> forward search&replace change?
>
> Shawn
>
> [1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/275912/
>
> Shawn Guo (9):
> ARM: dts: imx6qdl: remove the use of pingrp macros
> ARM: dts: imx6sl: remove the use of pingrp macros
> ARM: dts: imx53: remove the use of pingrp macros
> ARM: dts: imx51: remove the use of pingrp macros
> ARM: dts: imx50: remove the use of pingrp macros
> ARM: dts: imx35: remove the use of pingrp macros
> ARM: dts: imx25: remove the use of pingrp macros
> ARM: dts: imx27: remove the use of pingrp macros
> ARM: dts: vf610: remove the use of pingrp macros
>
> arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | 17 +-
> .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 56 ++-
> arch/arm/boot/dts/imx25-pingrp.h | 81 ---
> arch/arm/boot/dts/imx25.dtsi | 2 +-
> arch/arm/boot/dts/imx27-apf27.dts | 26 +-
> arch/arm/boot/dts/imx27-apf27dev.dts | 65 ++-
> arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 27 +-
> arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 26 +-
> arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 23 +-
> arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 38 +-
> arch/arm/boot/dts/imx27-pingrp.h | 151 ------
> arch/arm/boot/dts/imx27.dtsi | 2 +-
> arch/arm/boot/dts/imx35-pingrp.h | 104 ----
> arch/arm/boot/dts/imx35.dtsi | 1 -
> arch/arm/boot/dts/imx50-evk.dts | 28 +-
> arch/arm/boot/dts/imx50-pingrp.h | 146 ------
> arch/arm/boot/dts/imx50.dtsi | 2 +-
> arch/arm/boot/dts/imx51-apf51.dts | 26 +-
> arch/arm/boot/dts/imx51-apf51dev.dts | 64 ++-
> arch/arm/boot/dts/imx51-babbage.dts | 142 +++++-
> arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | 26 +-
> .../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 31 +-
> arch/arm/boot/dts/imx51-pingrp.h | 249 ---------
> arch/arm/boot/dts/imx51.dtsi | 2 +-
> arch/arm/boot/dts/imx53-ard.dts | 18 +-
> arch/arm/boot/dts/imx53-evk.dts | 51 +-
> arch/arm/boot/dts/imx53-m53evk.dts | 128 ++++-
> arch/arm/boot/dts/imx53-pingrp.h | 352 -------------
> arch/arm/boot/dts/imx53-qsb.dts | 88 +++-
> arch/arm/boot/dts/imx53-smd.dts | 77 ++-
> arch/arm/boot/dts/imx53-tqma53.dtsi | 89 +++-
> arch/arm/boot/dts/imx53-voipac-bsb.dts | 21 +-
> arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 47 +-
> arch/arm/boot/dts/imx53.dtsi | 2 +-
> arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
> arch/arm/boot/dts/imx6dl.dtsi | 1 -
> arch/arm/boot/dts/imx6q-arm2.dts | 81 ++-
> arch/arm/boot/dts/imx6q-cm-fx6.dts | 44 +-
> arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 47 +-
> arch/arm/boot/dts/imx6q-gw5400-a.dts | 75 ++-
> arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 53 +-
> arch/arm/boot/dts/imx6q-sbc6x.dts | 37 +-
> arch/arm/boot/dts/imx6q-udoo.dts | 33 +-
> arch/arm/boot/dts/imx6q.dtsi | 1 -
> arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 77 ++-
> arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 88 +++-
> arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 93 +++-
> arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 93 +++-
> arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
> arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 56 ++-
> arch/arm/boot/dts/imx6qdl-pingrp.h | 532 --------------------
> arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 139 ++++-
> arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 56 ++-
> arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 86 +++-
> arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 78 ++-
> arch/arm/boot/dts/imx6sl-evk.dts | 120 ++++-
> arch/arm/boot/dts/imx6sl-pingrp.h | 148 ------
> arch/arm/boot/dts/imx6sl.dtsi | 1 -
> arch/arm/boot/dts/vf610-cosmic.dts | 17 +-
> arch/arm/boot/dts/vf610-pingrp.h | 127 -----
> arch/arm/boot/dts/vf610-twr.dts | 42 +-
> arch/arm/boot/dts/vf610.dtsi | 2 +-
> 62 files changed, 2163 insertions(+), 2182 deletions(-)
> delete mode 100644 arch/arm/boot/dts/imx25-pingrp.h
> delete mode 100644 arch/arm/boot/dts/imx27-pingrp.h
> delete mode 100644 arch/arm/boot/dts/imx35-pingrp.h
> delete mode 100644 arch/arm/boot/dts/imx50-pingrp.h
> delete mode 100644 arch/arm/boot/dts/imx51-pingrp.h
> delete mode 100644 arch/arm/boot/dts/imx53-pingrp.h
> delete mode 100644 arch/arm/boot/dts/imx6qdl-pingrp.h
> delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
> delete mode 100644 arch/arm/boot/dts/vf610-pingrp.h
>
> --
> 1.7.9.5
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/9] ARM: dts: imx6qdl: remove the use of pingrp macros
2014-01-25 16:43 ` [PATCH 1/9] ARM: dts: imx6qdl: " Shawn Guo
@ 2014-01-27 14:37 ` Russell King - ARM Linux
2014-01-27 15:05 ` Shawn Guo
2014-01-28 10:30 ` Shawn Guo
0 siblings, 2 replies; 21+ messages in thread
From: Russell King - ARM Linux @ 2014-01-27 14:37 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Jan 26, 2014 at 12:43:03AM +0800, Shawn Guo wrote:
> arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
> arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
I've merged your changes here into my local copy of these just to reduce
the conflicts - unfortunately, it's taken soo long to deal with the above
that the cubox-i has now been released, which has prompted some
reorganisation between the above two files.
I would much rather you dropped these two entirely, and let me push them
upstream, rather than having some nasty conflicts which result from this.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/9] ARM: dts: imx6qdl: remove the use of pingrp macros
2014-01-27 14:37 ` Russell King - ARM Linux
@ 2014-01-27 15:05 ` Shawn Guo
2014-01-27 15:16 ` Russell King - ARM Linux
2014-01-28 10:30 ` Shawn Guo
1 sibling, 1 reply; 21+ messages in thread
From: Shawn Guo @ 2014-01-27 15:05 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 27, 2014 at 02:37:45PM +0000, Russell King - ARM Linux wrote:
> On Sun, Jan 26, 2014 at 12:43:03AM +0800, Shawn Guo wrote:
> > arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
> > arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
>
> I've merged your changes here into my local copy of these just to reduce
> the conflicts - unfortunately, it's taken soo long to deal with the above
> that the cubox-i has now been released, which has prompted some
> reorganisation between the above two files.
>
> I would much rather you dropped these two entirely, and let me push them
> upstream, rather than having some nasty conflicts which result from this.
So you're basically asking me to drop patch [1] from imx/dt branch (tag
imx-dt-3.14), which I have sent to Olof for 3.14 inclusion. Yes, I
still hope Olof can pull it with this turn-around series applied on top.
So please let's wait for Olof's word to see if we can make it. If it's
still a NO for some reason, I will be certainly fine with you pushing
hummingboard stuff upstream, and will drop it from my tree.
Shawn
[1] https://git.linaro.org/people/shawn.guo/linux-2.6.git/commit/8544f6c92801b1ba70f790cc17f543f7aa13f17f
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/9] ARM: dts: imx6qdl: remove the use of pingrp macros
2014-01-27 15:05 ` Shawn Guo
@ 2014-01-27 15:16 ` Russell King - ARM Linux
2014-01-27 15:22 ` Shawn Guo
0 siblings, 1 reply; 21+ messages in thread
From: Russell King - ARM Linux @ 2014-01-27 15:16 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 27, 2014 at 11:05:11PM +0800, Shawn Guo wrote:
> On Mon, Jan 27, 2014 at 02:37:45PM +0000, Russell King - ARM Linux wrote:
> > On Sun, Jan 26, 2014 at 12:43:03AM +0800, Shawn Guo wrote:
> > > arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
> > > arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
> >
> > I've merged your changes here into my local copy of these just to reduce
> > the conflicts - unfortunately, it's taken soo long to deal with the above
> > that the cubox-i has now been released, which has prompted some
> > reorganisation between the above two files.
> >
> > I would much rather you dropped these two entirely, and let me push them
> > upstream, rather than having some nasty conflicts which result from this.
>
> So you're basically asking me to drop patch [1] from imx/dt branch (tag
> imx-dt-3.14), which I have sent to Olof for 3.14 inclusion. Yes, I
> still hope Olof can pull it with this turn-around series applied on top.
> So please let's wait for Olof's word to see if we can make it. If it's
> still a NO for some reason, I will be certainly fine with you pushing
> hummingboard stuff upstream, and will drop it from my tree.
My point is that the DT files I _now_ have are quite different in
organisation to the ones I submitted to you, so there's going to be
conflicts if your version goes in.
Moreover, I don't want the old ones in 3.14 as-is, because I don't want
declarations which should not have been in the microsom file but in the
hummingboard file being in a final release of the mainline kernel.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/9] ARM: dts: imx6qdl: remove the use of pingrp macros
2014-01-27 15:16 ` Russell King - ARM Linux
@ 2014-01-27 15:22 ` Shawn Guo
0 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-27 15:22 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 27, 2014 at 03:16:39PM +0000, Russell King - ARM Linux wrote:
> On Mon, Jan 27, 2014 at 11:05:11PM +0800, Shawn Guo wrote:
> > On Mon, Jan 27, 2014 at 02:37:45PM +0000, Russell King - ARM Linux wrote:
> > > On Sun, Jan 26, 2014 at 12:43:03AM +0800, Shawn Guo wrote:
> > > > arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
> > > > arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
> > >
> > > I've merged your changes here into my local copy of these just to reduce
> > > the conflicts - unfortunately, it's taken soo long to deal with the above
> > > that the cubox-i has now been released, which has prompted some
> > > reorganisation between the above two files.
> > >
> > > I would much rather you dropped these two entirely, and let me push them
> > > upstream, rather than having some nasty conflicts which result from this.
> >
> > So you're basically asking me to drop patch [1] from imx/dt branch (tag
> > imx-dt-3.14), which I have sent to Olof for 3.14 inclusion. Yes, I
> > still hope Olof can pull it with this turn-around series applied on top.
> > So please let's wait for Olof's word to see if we can make it. If it's
> > still a NO for some reason, I will be certainly fine with you pushing
> > hummingboard stuff upstream, and will drop it from my tree.
>
> My point is that the DT files I _now_ have are quite different in
> organisation to the ones I submitted to you, so there's going to be
> conflicts if your version goes in.
>
> Moreover, I don't want the old ones in 3.14 as-is, because I don't want
> declarations which should not have been in the microsom file but in the
> hummingboard file being in a final release of the mainline kernel.
We can take care of them with incremental patches during early -rc.
Shawn
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
` (9 preceding siblings ...)
2014-01-27 14:04 ` [PATCH 0/9] ARM: dts: imx: " Rob Herring
@ 2014-01-27 17:47 ` Olof Johansson
10 siblings, 0 replies; 21+ messages in thread
From: Olof Johansson @ 2014-01-27 17:47 UTC (permalink / raw)
To: linux-arm-kernel
Shawn,
On Sat, Jan 25, 2014 at 8:43 AM, Shawn Guo <shawn.guo@linaro.org> wrote:
> Hi Rob,
>
> In order to solve a pinctrl data efficiency problem, we introduced
> pingrp macros [1] in this development cycle as the base of board dts
> support. The whole imx-dt-3.14 pull request has been held by Olof for
> a few weeks because he wants to get a general approval from DT folks
> on this change. But unfortunately it appears that you are not fond of
> this change.
>
> I just spent the day to create a patch series against imx-dt-3.14 to
> remove these pingrp macros. May I get your nod on this quick
> turn-around, so that we do not miss the merge window?
>
> Hi Olof,
>
> I guess we do not have to shut the door for imx-dt-3.14 if you and DT
> folks are happy with this patch series, which is a quite straight
> forward search&replace change?
The merge window is halfway over already, the time for us to pick up
large branches like these are long past.
Please rebase (since this is a partial revert of some of the earlier
patches in your dt branch, I think?), and resend after -rc1 for 3.15
inclusion.
Thanks,
-Olof
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 2/9] ARM: dts: imx6sl: remove the use of pingrp macros
2014-01-25 16:43 ` [PATCH 2/9] ARM: dts: imx6sl: " Shawn Guo
@ 2014-01-28 10:17 ` Heiko Stübner
2014-01-28 11:03 ` Sascha Hauer
2014-01-28 11:20 ` Shawn Guo
0 siblings, 2 replies; 21+ messages in thread
From: Heiko Stübner @ 2014-01-28 10:17 UTC (permalink / raw)
To: linux-arm-kernel
Hi Shawn,
On Sunday, 26. January 2014 00:43:04 Shawn Guo wrote:
> We created the pingrp macros in imx6sl-pingrp.h for purpose of less LOC
> when same pin group is used by multiple boards. However, DT maintainers
> take it as an abuse of DTC macro support. So let's get rid of it to
> make the pins used by given device more intuitive.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
> arch/arm/boot/dts/imx6sl-evk.dts | 120 ++++++++++++++++++++++++++----
> arch/arm/boot/dts/imx6sl-pingrp.h | 148
> ------------------------------------- arch/arm/boot/dts/imx6sl.dtsi |
> 1 -
> 3 files changed, 107 insertions(+), 162 deletions(-)
> delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
>
> diff --git a/arch/arm/boot/dts/imx6sl-evk.dts
> b/arch/arm/boot/dts/imx6sl-evk.dts index f5e4513..8594d13 100644
> --- a/arch/arm/boot/dts/imx6sl-evk.dts
> +++ b/arch/arm/boot/dts/imx6sl-evk.dts
> @@ -86,55 +86,149 @@
> };
>
> pinctrl_ecspi1: ecspi1grp {
> - fsl,pins = <MX6SL_ECSPI1_PINGRP1>;
> + fsl,pins = <
> + MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
> + MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
> + MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
> + >;
> };
>
> pinctrl_fec: fecgrp {
> - fsl,pins = <MX6SL_FEC_PINGRP1>;
> + fsl,pins = <
> + MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
> + MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
> + MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
> + MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
> + MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
> + MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
> + MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
> + MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
> + MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
> + >;
> };
[... and so on for the other groups ... ]
I'm confused now :-) . Current linux-next [0] shows the pin-settings as part
of imx6sl.dtsi - a way a lot of other architectures organize their pingroups
too, with the board file only referencing the relevant pingroups from the
predefined ones of the soc.
So I guess your move to the pingrp-header moved them out of the imx6sl.dtsi to
the .h and is not part of linux-next; but this patch (and the others in this
series) now moves the definitions into the individual board files. Can't you
just move them back to the soc-dtsi files to prevent each board duplicating
them?
Or I've simply missed previous discussions about this ;-) .
Thanks
Heiko
[0] https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/imx6sl.dtsi#n640
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/9] ARM: dts: imx6qdl: remove the use of pingrp macros
2014-01-27 14:37 ` Russell King - ARM Linux
2014-01-27 15:05 ` Shawn Guo
@ 2014-01-28 10:30 ` Shawn Guo
1 sibling, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2014-01-28 10:30 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 27, 2014 at 02:37:45PM +0000, Russell King - ARM Linux wrote:
> On Sun, Jan 26, 2014 at 12:43:03AM +0800, Shawn Guo wrote:
> > arch/arm/boot/dts/imx6dl-hummingboard.dts | 5 +-
> > arch/arm/boot/dts/imx6qdl-microsom.dtsi | 5 +-
>
> I've merged your changes here into my local copy of these just to reduce
> the conflicts - unfortunately, it's taken soo long to deal with the above
> that the cubox-i has now been released, which has prompted some
> reorganisation between the above two files.
>
> I would much rather you dropped these two entirely, and let me push them
> upstream, rather than having some nasty conflicts which result from this.
Dropped hummingboard from my tree.
Shawn
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 2/9] ARM: dts: imx6sl: remove the use of pingrp macros
2014-01-28 10:17 ` Heiko Stübner
@ 2014-01-28 11:03 ` Sascha Hauer
2014-01-28 11:20 ` Shawn Guo
1 sibling, 0 replies; 21+ messages in thread
From: Sascha Hauer @ 2014-01-28 11:03 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 28, 2014 at 11:17:22AM +0100, Heiko St?bner wrote:
> Hi Shawn,
>
> On Sunday, 26. January 2014 00:43:04 Shawn Guo wrote:
> > We created the pingrp macros in imx6sl-pingrp.h for purpose of less LOC
> > when same pin group is used by multiple boards. However, DT maintainers
> > take it as an abuse of DTC macro support. So let's get rid of it to
> > make the pins used by given device more intuitive.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> > arch/arm/boot/dts/imx6sl-evk.dts | 120 ++++++++++++++++++++++++++----
> > arch/arm/boot/dts/imx6sl-pingrp.h | 148
> > ------------------------------------- arch/arm/boot/dts/imx6sl.dtsi |
> > 1 -
> > 3 files changed, 107 insertions(+), 162 deletions(-)
> > delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
> >
> > diff --git a/arch/arm/boot/dts/imx6sl-evk.dts
> > b/arch/arm/boot/dts/imx6sl-evk.dts index f5e4513..8594d13 100644
> > --- a/arch/arm/boot/dts/imx6sl-evk.dts
> > +++ b/arch/arm/boot/dts/imx6sl-evk.dts
> > @@ -86,55 +86,149 @@
> > };
> >
> > pinctrl_ecspi1: ecspi1grp {
> > - fsl,pins = <MX6SL_ECSPI1_PINGRP1>;
> > + fsl,pins = <
> > + MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
> > + MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
> > + MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
> > + >;
> > };
> >
> > pinctrl_fec: fecgrp {
> > - fsl,pins = <MX6SL_FEC_PINGRP1>;
> > + fsl,pins = <
> > + MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
> > + MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
> > + MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
> > + MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
> > + MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
> > + MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
> > + MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
> > + MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
> > + MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
> > + >;
> > };
>
> [... and so on for the other groups ... ]
>
> I'm confused now :-) . Current linux-next [0] shows the pin-settings as part
> of imx6sl.dtsi - a way a lot of other architectures organize their pingroups
> too, with the board file only referencing the relevant pingroups from the
> predefined ones of the soc.
Current mainline has all groups under the iomux node which has the
effect that all possible groups are compiled into every dtb resulting in
very bloated dtbs. So Shawn changed it to what's currently in next, but
this hasn't been accepted by the dt maintainers. Now this series tries
to address the concerns of the dt maintainers by not using macros that
expand to other macros.
Sascha
--
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 2/9] ARM: dts: imx6sl: remove the use of pingrp macros
2014-01-28 10:17 ` Heiko Stübner
2014-01-28 11:03 ` Sascha Hauer
@ 2014-01-28 11:20 ` Shawn Guo
2014-01-29 10:42 ` Heiko Stübner
1 sibling, 1 reply; 21+ messages in thread
From: Shawn Guo @ 2014-01-28 11:20 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 28, 2014 at 11:17:22AM +0100, Heiko St?bner wrote:
> [... and so on for the other groups ... ]
>
> I'm confused now :-) . Current linux-next [0] shows the pin-settings as part
> of imx6sl.dtsi - a way a lot of other architectures organize their pingroups
> too, with the board file only referencing the relevant pingroups from the
> predefined ones of the soc.
>
> So I guess your move to the pingrp-header moved them out of the imx6sl.dtsi to
> the .h and is not part of linux-next;
Yes, my for-next branch was excluded from linux-next temporarily for
some reason. I will ask Stephen to add it back once v3.14-rc1 is out.
That said, you can see nothing we developed in this cycle on linux-next
for now.
> but this patch (and the others in this
> series) now moves the definitions into the individual board files. Can't you
> just move them back to the soc-dtsi files to prevent each board duplicating
> them?
No. That will bring back the problem we try to solve from the
beginning [1].
Shawn
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/275912/
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 2/9] ARM: dts: imx6sl: remove the use of pingrp macros
2014-01-28 11:20 ` Shawn Guo
@ 2014-01-29 10:42 ` Heiko Stübner
0 siblings, 0 replies; 21+ messages in thread
From: Heiko Stübner @ 2014-01-29 10:42 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday, 28. January 2014 19:20:49 Shawn Guo wrote:
> On Tue, Jan 28, 2014 at 11:17:22AM +0100, Heiko St?bner wrote:
> > [... and so on for the other groups ... ]
> >
> > I'm confused now :-) . Current linux-next [0] shows the pin-settings as
> > part of imx6sl.dtsi - a way a lot of other architectures organize their
> > pingroups too, with the board file only referencing the relevant
> > pingroups from the predefined ones of the soc.
> >
> > So I guess your move to the pingrp-header moved them out of the
> > imx6sl.dtsi to the .h and is not part of linux-next;
>
> Yes, my for-next branch was excluded from linux-next temporarily for
> some reason. I will ask Stephen to add it back once v3.14-rc1 is out.
> That said, you can see nothing we developed in this cycle on linux-next
> for now.
>
> > but this patch (and the others in this
> > series) now moves the definitions into the individual board files. Can't
> > you just move them back to the soc-dtsi files to prevent each board
> > duplicating them?
>
> No. That will bring back the problem we try to solve from the
> beginning [1].
>
> [1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/275912/
Thanks for the pointer, I think I understand the issue now :-) .
So for the short term, I should probably also define the pingroups in my board-
dts then.
But as an insane idea that I just had, because the issue will probably affect
more architectures at some point when their pingroups or other common-nodes
grow, how about introducing something like a "/delete-if-unreferenced/" prefix
in dtc?
As I could see in [0], adding something to dtc is not as far off as I thought.
In essence one would add the pingroups to the soc dtsi, like
ecspi1 {
/delete-if-unreferenced/ pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
>;
};
};
and dtc would then be tasked with checking if the node gets referenced in a
phandle somewhere in the dts and if not removing it.
I don't know if this is at all sane to think about or doable in dtc.
Heiko
[0] http://www.spinics.net/lists/arm-kernel/msg300936.html
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2014-01-29 10:42 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-01-25 16:43 [PATCH 0/9] ARM: dts: imx: remove the use of pingrp macros Shawn Guo
2014-01-25 16:43 ` [PATCH 1/9] ARM: dts: imx6qdl: " Shawn Guo
2014-01-27 14:37 ` Russell King - ARM Linux
2014-01-27 15:05 ` Shawn Guo
2014-01-27 15:16 ` Russell King - ARM Linux
2014-01-27 15:22 ` Shawn Guo
2014-01-28 10:30 ` Shawn Guo
2014-01-25 16:43 ` [PATCH 2/9] ARM: dts: imx6sl: " Shawn Guo
2014-01-28 10:17 ` Heiko Stübner
2014-01-28 11:03 ` Sascha Hauer
2014-01-28 11:20 ` Shawn Guo
2014-01-29 10:42 ` Heiko Stübner
2014-01-25 16:43 ` [PATCH 3/9] ARM: dts: imx53: " Shawn Guo
2014-01-25 16:43 ` [PATCH 4/9] ARM: dts: imx51: " Shawn Guo
2014-01-25 16:43 ` [PATCH 5/9] ARM: dts: imx50: " Shawn Guo
2014-01-25 16:43 ` [PATCH 6/9] ARM: dts: imx35: " Shawn Guo
2014-01-25 16:43 ` [PATCH 7/9] ARM: dts: imx25: " Shawn Guo
2014-01-25 16:43 ` [PATCH 8/9] ARM: dts: imx27: " Shawn Guo
2014-01-25 16:43 ` [PATCH 9/9] ARM: dts: vf610: " Shawn Guo
2014-01-27 14:04 ` [PATCH 0/9] ARM: dts: imx: " Rob Herring
2014-01-27 17:47 ` Olof Johansson
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