From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [Q] L1_CACHE_BYTES on flush_pfn_alias function.
Date: Mon, 27 Jan 2014 16:43:37 +0000 [thread overview]
Message-ID: <20140127164337.GB8358@arm.com> (raw)
In-Reply-To: <003c01cf1a55$623979f0$26ac6dd0$@samsung.com>
Please do not top-post.
On Sun, Jan 26, 2014 at 05:13:43AM +0000, Jungseung Lee wrote:
> Not to flush some more bytes. In the scenario, they can *omit* to flush last 32 bytes.
>
> L1_CACHE_BYTES = 64 (ARM v7, CA9)
>
> asm( "mcrr p15, 0, %1, %0, c14\n"
> " mcr p15, 0, %2, c7, c10, 4"
> :
> : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
> : "cc");
Ah, I got it now. I think this should be (to + PAGE_SIZE - 1). My
reading of the ARM ARM is that the bottom bits of the address are
ignored by mcrr.
--
Catalin
prev parent reply other threads:[~2014-01-27 16:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-17 9:54 [Q] L1_CACHE_BYTES on flush_pfn_alias function 이정승
2014-01-24 15:43 ` Catalin Marinas
2014-01-26 5:13 ` Jungseung Lee
2014-01-27 16:43 ` Catalin Marinas [this message]
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