From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] ARM: mm: Fix stage-2 device memory attributes
Date: Mon, 27 Jan 2014 16:57:31 +0000 [thread overview]
Message-ID: <20140127165730.GC8358@arm.com> (raw)
In-Reply-To: <52E64029.6000201@arm.com>
On Mon, Jan 27, 2014 at 11:16:57AM +0000, Marc Zyngier wrote:
> On 24/01/14 23:37, Christoffer Dall wrote:
> > On Sat, Jan 04, 2014 at 08:27:23AM -0800, Christoffer Dall wrote:
> >> --- a/arch/arm/include/asm/pgtable-3level.h
> >> +++ b/arch/arm/include/asm/pgtable-3level.h
> >> @@ -120,13 +120,19 @@
> >> /*
> >> * 2nd stage PTE definitions for LPAE.
> >> */
> >> -#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
> >> -#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
> >> -#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
> >> -#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
> >> -#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
> >> -
> >> -#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
> >> +#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
> >> +#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
> >> +#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
> >> +#define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */
> >> +#define L_PTE_S2_MT_DEV_NONSHARED (_AT(pteval_t, 0x1) << 2) /* device */
> >> +#define L_PTE_S2_MT_DEV_WC (_AT(pteval_t, 0x5) << 2) /* normal non-cacheable */
> >> +#define L_PTE_S2_MT_DEV_CACHED (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
> >> +#define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2)
> >> +
> >> +#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
> >> +#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
> >> +
> >> +#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
> >>
> >> /*
> >> * Hyp-mode PL2 PTE definitions for LPAE.
>
> The change makes sense to me. arm64 uses a slightly different approach,
> by using a PTE_S2_MEMATTR macro, but I'm not sure that would work for ARM.
>
> Russell, Catalin: could you please have a look at this?
Do we actually need more than Normal Cacheable and Device for stage 2?
--
Catalin
next prev parent reply other threads:[~2014-01-27 16:57 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-04 6:14 [PATCH] ARM: mm: Fix stage-2 device memory attributes Christoffer Dall
2014-01-04 16:27 ` [PATCH v2] " Christoffer Dall
2014-01-24 23:37 ` Christoffer Dall
2014-01-27 11:16 ` Marc Zyngier
2014-01-27 16:57 ` Catalin Marinas [this message]
2014-01-27 17:02 ` Marc Zyngier
2014-01-27 17:21 ` Catalin Marinas
2014-01-28 21:24 ` Christoffer Dall
-- strict thread matches above, loose matches on Subject: below --
2014-01-28 21:24 Christoffer Dall
2014-01-29 10:39 ` Marc Zyngier
2014-01-29 15:44 ` Christoffer Dall
2014-01-30 11:41 ` Catalin Marinas
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