From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 05/11] ARM: LPAE: provide an IPA capable pmd_addr_end
Date: Thu, 6 Feb 2014 10:43:28 +0000 [thread overview]
Message-ID: <20140206104328.GB29446@arm.com> (raw)
In-Reply-To: <1391630151-7875-6-git-send-email-marc.zyngier@arm.com>
On Wed, Feb 05, 2014 at 07:55:45PM +0000, Marc Zyngier wrote:
> The default pmd_addr_end macro uses an unsigned long to represent
> the VA. When used with KVM and stage-2 translation, the VA is
> actually an IPA, which is up to 40 bits. This also affect the
> SMMU driver, which also deals with stage-2 translation.
>
> Instead, provide an implementation that can cope with larger VAs
> by using a u64 instead. This version will overload the default
> one provided in include/asm-generic/pgtable.h.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm/include/asm/pgtable-3level.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
> index 03243f7..594867b 100644
> --- a/arch/arm/include/asm/pgtable-3level.h
> +++ b/arch/arm/include/asm/pgtable-3level.h
> @@ -262,6 +262,11 @@ static inline int has_transparent_hugepage(void)
> return 1;
> }
>
> +#define pmd_addr_end(addr, end) \
> +({ u64 __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
> + (__boundary - 1 < (end) - 1)? __boundary: (end); \
> +})
I see why you need this but it affects all the other uses of
pmd_addr_end() with 32-bit VA. It would be slight performance, I don't
think it's noticeable.
A different approach could be something like (untested):
#define pmd_addr_end(addr, end) \
({ __typeof__(addr) __boundary = ...
...
})
What about the pgd_addr_end(), do we need this or it's not used by KVM?
--
Catalin
next prev parent reply other threads:[~2014-02-06 10:43 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-05 19:55 [PATCH v3 00/11] arm/arm64: KVM: host cache maintenance when guest caches are off Marc Zyngier
2014-02-05 19:55 ` [PATCH v3 01/11] arm64: KVM: force cache clean on page fault when " Marc Zyngier
2014-02-05 19:55 ` [PATCH v3 02/11] arm64: KVM: allows discrimination of AArch32 sysreg access Marc Zyngier
2014-02-05 19:55 ` [PATCH v3 03/11] arm64: KVM: trap VM system registers until MMU and caches are ON Marc Zyngier
2014-02-05 19:55 ` [PATCH v3 04/11] arm64: KVM: flush VM pages before letting the guest enable caches Marc Zyngier
2014-02-07 4:08 ` Christoffer Dall
2014-02-05 19:55 ` [PATCH v3 05/11] ARM: LPAE: provide an IPA capable pmd_addr_end Marc Zyngier
2014-02-06 10:43 ` Catalin Marinas [this message]
2014-02-07 4:04 ` Christoffer Dall
2014-02-07 15:44 ` Catalin Marinas
2014-02-07 17:10 ` Christoffer Dall
2014-02-11 9:07 ` Marc Zyngier
2014-02-05 19:55 ` [PATCH v3 06/11] ARM: KVM: force cache clean on page fault when caches are off Marc Zyngier
2014-02-06 10:49 ` Catalin Marinas
2014-02-05 19:55 ` [PATCH v3 07/11] ARM: KVM: fix handling of trapped 64bit coprocessor accesses Marc Zyngier
2014-02-06 10:49 ` Catalin Marinas
2014-02-05 19:55 ` [PATCH v3 08/11] ARM: KVM: fix ordering of " Marc Zyngier
2014-02-06 10:50 ` Catalin Marinas
2014-02-05 19:55 ` [PATCH v3 09/11] ARM: KVM: introduce per-vcpu HYP Configuration Register Marc Zyngier
2014-02-06 11:01 ` Catalin Marinas
2014-02-05 19:55 ` [PATCH v3 10/11] ARM: KVM: add world-switch for AMAIR{0,1} Marc Zyngier
2014-02-06 11:02 ` Catalin Marinas
2014-02-05 19:55 ` [PATCH v3 11/11] ARM: KVM: trap VM system registers until MMU and caches are ON Marc Zyngier
2014-02-06 11:03 ` Catalin Marinas
2014-02-07 4:08 ` Christoffer Dall
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