[PATCH 00/11] Core support for Marvell Armada 375 and 38x

[PATCH 00/11] Core support for Marvell Armada 375 and 38x

[Thomas Petazzoni]

Jason, Andrew, Sebastian, Gregory,

Here is a set of 11 patches that add minimal support for the new
Marvell Armada 375 and 38x SoCs. The Armada 375 has already been
announced a few months ago by Marvell, and a product brief is
available at
http://www.marvell.com/embedded-processors/armada-375/. As far as I
know, the Armada 380 and 385 have not yet been announced, but we
already have working kernel support for them.

Essentially, the Armada 375 is a dual-core Cortex-A9, which re-uses
most of the IP blocks of the Armada XP, except for the network unit
and core parts of the SoC, such as the interrupt controller or cache
controller (GIC and PL310 are used). They also added an XHCI USB 3.0
controller.

The Armada 380 and 385 also use Cortex-A9 CPU cores (single core for
the 380 and dual-core for the 385), but move a little further away
than 375 in terms of peripherals: an AHCI-compatible SATA interface, a
different MMC/SDIO interface, etc.

This set of patches only add minimal support for these SOCs, as well
as support for the peripherals for which no driver changes are
needed. We therefore have support for:

 * Device Bus
 * Clocks
 * Interrupt controllers: GIC and MPIC
 * GPIO controllers
 * I2C buses
 * SPI buses
 * L2 cache
 * MBus controller
 * SDIO (for Armada 375 only)
 * Pinctrl
 * SATA (for Armada 375 only)
 * Serial
 * System controller
 * XOR engines
 * PCIe controllers
 * Network (for Armada 38x only)

Some of these features require patches to other subsystems, and the
patches are being sent to the respective maintainers currently: clock
driver patches, pinctrl driver patches, irqchip driver patches, mbus
driver patches, etc. There is however no build dependency between the
arch/arm/mach-mvebu/ code and those other patches.

We aim at getting this minimal support merged for 3.15.

We have already working code for many more features, such as SMP,
coherency support, NAND, SATA and SDIO for Armada 380, etc. We will be
sending those additional features once the basic support has been
merged.

It is worth noting that contrary to the Marvell 370 and XP support,
which has been pushed mainline fairly late in the development cycle of
the SOCs, the support for Armada 375 and 38x is now being pushed quite
early in the development cycle of the SOCs. We are having mainline
support pretty much at the same time as the SOCs are being made
available to customers, which is really great!

Best regards,

Thomas

Gregory CLEMENT (2):
  ARM: mvebu: add initial support for the Armada 375 SOCs
  ARM: mvebu: add Device Tree description of the Armada 375 SoC

Thomas Petazzoni (9):
  ARM: mvebu: add Armada 375 support to the system-controller driver
  ARM: mvebu: add workaround for data abort issue on Armada 375
  ARM: mvebu: add Device Tree for the Armada 375 DB board
  ARM: mvebu: add Armada 380/385 support to the system-controller driver
  ARM: mvebu: add initial support for the Armada 380/385 SOCs
  ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs
  ARM: mvebu: add Device Tree for the Armada 385 DB board
  ARM: mvebu: update defconfigs for Armada 375 and 38x
  Documentation: arm: update Marvell documentation about Armada 375/38x

 Documentation/arm/Marvell/README                   |  12 +-
 .../devicetree/bindings/arm/armada-375.txt         |   9 +
 .../devicetree/bindings/arm/armada-38x.txt         |  10 +
 .../bindings/arm/mvebu-system-controller.txt       |   4 +-
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/armada-375-db.dts                | 106 +++++
 arch/arm/boot/dts/armada-375.dtsi                  | 439 +++++++++++++++++++++
 arch/arm/boot/dts/armada-380.dtsi                  | 117 ++++++
 arch/arm/boot/dts/armada-385-db.dts                | 101 +++++
 arch/arm/boot/dts/armada-385.dtsi                  | 149 +++++++
 arch/arm/boot/dts/armada-38x.dtsi                  | 339 ++++++++++++++++
 arch/arm/configs/multi_v7_defconfig                |   2 +
 arch/arm/configs/mvebu_defconfig                   |   2 +
 arch/arm/mach-mvebu/Kconfig                        |  30 ++
 arch/arm/mach-mvebu/Makefile                       |   2 +
 arch/arm/mach-mvebu/armada-375.c                   |  67 ++++
 arch/arm/mach-mvebu/armada-38x.c                   |  42 ++
 arch/arm/mach-mvebu/system-controller.c            |  22 +-
 18 files changed, 1451 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-375.txt
 create mode 100644 Documentation/devicetree/bindings/arm/armada-38x.txt
 create mode 100644 arch/arm/boot/dts/armada-375-db.dts
 create mode 100644 arch/arm/boot/dts/armada-375.dtsi
 create mode 100644 arch/arm/boot/dts/armada-380.dtsi
 create mode 100644 arch/arm/boot/dts/armada-385-db.dts
 create mode 100644 arch/arm/boot/dts/armada-385.dtsi
 create mode 100644 arch/arm/boot/dts/armada-38x.dtsi
 create mode 100644 arch/arm/mach-mvebu/armada-375.c
 create mode 100644 arch/arm/mach-mvebu/armada-38x.c

-- 
1.8.3.2

[PATCH 01/11] ARM: mvebu: add Armada 375 support to the system-controller driver

[Thomas Petazzoni]

The system controller block in the Armada 375 has different register
offsets for the system reset and other related functions. Therefore,
this commit introduces the new "armada-375-system-controller"
compatible string to identify the Armada 375 variant of the system
controller.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 .../devicetree/bindings/arm/mvebu-system-controller.txt    |  3 ++-
 arch/arm/mach-mvebu/system-controller.c                    | 14 ++++++++++++--
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
index 081c6a7..d24ab2e 100644
--- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
@@ -1,12 +1,13 @@
 MVEBU System Controller
 -----------------------
-MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
+MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
 
 Required properties:
 
 - compatible: one of:
 	- "marvell,orion-system-controller"
 	- "marvell,armada-370-xp-system-controller"
+	- "marvell,armada-375-system-controller"
 - reg: Should contain system controller registers location and length.
 
 Example:
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index a7fb89a..1806187 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -1,5 +1,5 @@
 /*
- * System controller support for Armada 370 and XP platforms.
+ * System controller support for Armada 370, 375 and XP platforms.
  *
  * Copyright (C) 2012 Marvell
  *
@@ -11,7 +11,7 @@
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  *
- * The Armada 370 and Armada XP SoCs both have a range of
+ * The Armada 370, 375 and Armada XP SoCs have a range of
  * miscellaneous registers, that do not belong to a particular device,
  * but rather provide system-level features. This basic
  * system-controller driver provides a device tree binding for those
@@ -47,6 +47,13 @@ static const struct mvebu_system_controller armada_370_xp_system_controller = {
 	.system_soft_reset = 0x1,
 };
 
+static const struct mvebu_system_controller armada_375_system_controller = {
+	.rstoutn_mask_offset = 0x54,
+	.system_soft_reset_offset = 0x58,
+	.rstoutn_mask_reset_out_en = 0x1,
+	.system_soft_reset = 0x1,
+};
+
 static const struct mvebu_system_controller orion_system_controller = {
 	.rstoutn_mask_offset = 0x108,
 	.system_soft_reset_offset = 0x10c,
@@ -61,6 +68,9 @@ static struct of_device_id of_system_controller_table[] = {
 	}, {
 		.compatible = "marvell,armada-370-xp-system-controller",
 		.data = (void *) &armada_370_xp_system_controller,
+	}, {
+		.compatible = "marvell,armada-375-system-controller",
+		.data = (void *) &armada_375_system_controller,
 	},
 	{ /* end of list */ },
 };
-- 
1.8.3.2

[PATCH 02/11] ARM: mvebu: add initial support for the Armada 375 SOCs

[Thomas Petazzoni]

From: Gregory CLEMENT <gregory.clement@free-electrons.com>

This commit adds the basic support for the Armada 375 SOCs. These SoCs
share most of their IP with the Armada 370/XP SoCs. The main
difference is the use of a Cortex A9 CPU instead of the PJ4B CPU. The
interrupt controller and the L2 cache controller are also different
they are respectively the GIC and the PL310.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../devicetree/bindings/arm/armada-375.txt         |  9 +++++
 arch/arm/mach-mvebu/Kconfig                        | 15 ++++++++
 arch/arm/mach-mvebu/Makefile                       |  1 +
 arch/arm/mach-mvebu/armada-375.c                   | 44 ++++++++++++++++++++++
 4 files changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-375.txt
 create mode 100644 arch/arm/mach-mvebu/armada-375.c

diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt b/Documentation/devicetree/bindings/arm/armada-375.txt
new file mode 100644
index 0000000..867d0b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-375.txt
@@ -0,0 +1,9 @@
+Marvell Armada 375 Platforms Device Tree Bindings
+-------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 375 family shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armada375"
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 5e269d7..3aefdcd 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -37,6 +37,21 @@ config MACH_ARMADA_370
 	  Say 'Y' here if you want your kernel to support boards based
 	  on the Marvell Armada 370 SoC with device tree.
 
+config MACH_ARMADA_375
+	bool "Marvell Armada 375 boards"
+	select ARM_ERRATA_720789
+	select ARM_ERRATA_753970
+	select ARM_GIC
+	select ARMADA_370_XP_TIMER
+	select ARMADA_375_CLK
+	select CACHE_L2X0
+	select CPU_V7
+	select NEON
+	select PINCTRL_ARMADA_375
+	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada 375 SoC with device tree.
+
 config MACH_ARMADA_XP
 	bool "Marvell Armada XP boards"
 	select ARMADA_XP_CLK
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 878aebe..9862e0f 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -5,6 +5,7 @@ AFLAGS_coherency_ll.o		:= -Wa,-march=armv7-a
 
 obj-y				 += system-controller.o mvebu-soc-id.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_375)    += armada-375.o
 obj-$(CONFIG_ARCH_MVEBU)	 += coherency.o coherency_ll.o pmsu.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
diff --git a/arch/arm/mach-mvebu/armada-375.c b/arch/arm/mach-mvebu/armada-375.c
new file mode 100644
index 0000000..f13c9de
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada-375.c
@@ -0,0 +1,44 @@
+/*
+ * Device Tree support for Armada 375 platforms.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/mbus.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include "common.h"
+
+static void __init armada_375_timer_and_clk_init(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+	BUG_ON(mvebu_mbus_dt_init());
+	l2x0_of_init(0, ~0UL);
+}
+
+static const char * const armada_375_dt_compat[] = {
+	"marvell,armada375",
+	NULL,
+};
+
+DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
+	.init_time	= armada_375_timer_and_clk_init,
+	.restart	= mvebu_restart,
+	.dt_compat	= armada_375_dt_compat,
+MACHINE_END
-- 
1.8.3.2

[PATCH 03/11] ARM: mvebu: add workaround for data abort issue on Armada 375

[Thomas Petazzoni]

Early versions of Armada 375 SoC have a bug where the BootROM leaves
an external data abort pending. The kernel is hit by this data abort
as soon as it enters userspace, because it unmasks the data aborts at
this moment. We register a custom abort handler below to ignore the
first data abort to work around this problem.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/armada-375.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/mach-mvebu/armada-375.c b/arch/arm/mach-mvebu/armada-375.c
index f13c9de..d772ae2 100644
--- a/arch/arm/mach-mvebu/armada-375.c
+++ b/arch/arm/mach-mvebu/armada-375.c
@@ -22,14 +22,37 @@
 #include <linux/mbus.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
+#include <asm/signal.h>
 #include "common.h"
 
+/*
+ * Early versions of Armada 375 SoC have a bug where the BootROM
+ * leaves an external data abort pending. The kernel is hit by this
+ * data abort as soon as it enters userspace, because it unmasks the
+ * data aborts at this moment. We register a custom abort handler
+ * below to ignore the first data abort to work around this problem.
+ */
+static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
+					struct pt_regs *regs)
+{
+	static int ignore_first;
+
+	if (!ignore_first) {
+		ignore_first = 1;
+		return 0;
+	}
+
+	return 1;
+}
+
 static void __init armada_375_timer_and_clk_init(void)
 {
 	of_clk_init(NULL);
 	clocksource_of_init();
 	BUG_ON(mvebu_mbus_dt_init());
 	l2x0_of_init(0, ~0UL);
+	hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
+			"imprecise external abort");
 }
 
 static const char * const armada_375_dt_compat[] = {
-- 
1.8.3.2

[PATCH 04/11] ARM: mvebu: add Device Tree description of the Armada 375 SoC

[Thomas Petazzoni]

From: Gregory CLEMENT <gregory.clement@free-electrons.com>

The Armada 375 SoC is a new SoC from Marvell, based on a dual core
Cortex-A9 and a number of hardware blocks that are common with earlier
SoCs from the mvebu family.

The provided Device Tree describes the following parts of the SoC:

 * CPUs
 * Device Bus
 * Clocks
 * Interrupt controllers: GIC and MPIC
 * GPIO controllers
 * I2C buses
 * L2 cache
 * MBus controller
 * SDIO
 * Pinctrl
 * SATA
 * Serial
 * SPI buses
 * System controller (for reboot)
 * Timer
 * XOR engines
 * PCIe controllers

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-375.dtsi | 439 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 439 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-375.dtsi

diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
new file mode 100644
index 0000000..2697345
--- /dev/null
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -0,0 +1,439 @@
+/*
+ * Device Tree Include file for Marvell Armada 375 family SoC
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+/ {
+	model = "Marvell Armada 375 family SoC";
+	compatible = "marvell,armada375";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+	};
+
+	clocks {
+		/* 2 GHz fixed main PLL */
+		mainpll: mainpll {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <2000000000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		compatible = "marvell,armada375-mbus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		controller = <&mbusc>;
+		interrupt-parent = <&gic>;
+		pcie-mem-aperture = <0xe0000000 0x8000000>;
+		pcie-io-aperture  = <0xe8000000 0x100000>;
+
+		bootrom {
+			compatible = "marvell,bootrom";
+			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+		};
+
+		devbus-bootcs {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs0 {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs1 {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs2 {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs3 {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		internal-regs {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+			L2: cache-controller at 8000 {
+				compatible = "arm,pl310-cache";
+				reg = <0x8000 0x1000>;
+				cache-unified;
+				cache-level = <2>;
+			};
+
+			timer at c600 {
+				compatible = "arm,cortex-a9-twd-timer";
+				reg = <0xc600 0x20>;
+				interrupts = <1 13 0x301>;
+				clocks = <&coreclk 2>;
+			};
+
+			gic: interrupt-controller at d000 {
+				compatible = "arm,cortex-a9-gic";
+				#interrupt-cells = <3>;
+				#size-cells = <0>;
+				interrupt-controller;
+				reg = <0xd000 0x1000>,
+				      <0xc100 0x100>;
+			};
+
+			spi0: spi at 10600 {
+				compatible = "marvell,orion-spi";
+				reg = <0x10600 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <0>;
+				interrupts = <0 1 0x4>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			spi1: spi at 10680 {
+				compatible = "marvell,orion-spi";
+				reg = <0x10680 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <1>;
+				interrupts = <0 63 0x4>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c0: i2c at 11000 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11000 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <0 2 0x4>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 11100 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11100 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <0 3 0x4>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			serial at 12000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12000 0x100>;
+				reg-shift = <2>;
+				interrupts = <0 12 4>;
+				reg-io-width = <1>;
+				status = "disabled";
+			};
+
+			serial at 12100 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12100 0x100>;
+				reg-shift = <2>;
+				interrupts = <0 13 4>;
+				reg-io-width = <1>;
+				status = "disabled";
+			};
+
+			pinctrl {
+				compatible = "marvell,mv88f6720-pinctrl";
+				reg = <0x18000 0x24>;
+
+				i2c0_pins: i2c0-pins {
+					marvell,pins = "mpp14",  "mpp15";
+					marvell,function = "i2c0";
+				};
+
+				i2c1_pins: i2c1-pins {
+					marvell,pins = "mpp61",  "mpp62";
+					marvell,function = "i2c1";
+				};
+
+				sdio_pins: sdio-pins {
+					marvell,pins = "mpp24",  "mpp25", "mpp26",
+						     "mpp27", "mpp28", "mpp29";
+					marvell,function = "sd";
+				};
+
+				spi0_pins: spi0-pins {
+					marvell,pins = "mpp0",  "mpp1", "mpp4",
+						     "mpp5", "mpp8", "mpp9";
+					marvell,function = "spi0";
+				};
+			};
+
+			gpio0: gpio at 18100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18100 0x40>;
+				ngpios = <32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 53 0x4>, <0 54 0x4>,
+					     <0 55 0x4>, <0 56 0x4>;
+			};
+
+			gpio1: gpio at 18140 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18140 0x40>;
+				ngpios = <32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 58 0x4>, <0 59 0x4>,
+					     <0 60 0x4>, <0 61 0x4>;
+			};
+
+			gpio2: gpio at 18180 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18180 0x40>;
+				ngpios = <3>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 62 0x4>;
+			};
+
+			system-controller at 18200 {
+				compatible = "marvell,armada-375-system-controller";
+				reg = <0x18200 0x100>;
+			};
+
+			gateclk: clock-gating-control at 18220 {
+				compatible = "marvell,armada-375-gating-clock";
+				reg = <0x18220 0x4>;
+				clocks = <&coreclk 0>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller at 20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x20180 0x20>;
+			};
+
+			mpic: interrupt-controller at 20000 {
+				compatible = "marvell,mpic";
+				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+				#interrupt-cells = <1>;
+				#size-cells = <1>;
+				interrupt-controller;
+				msi-controller;
+				interrupts = <1 15 0x4>;
+			};
+
+			timer at 20300 {
+				compatible = "marvell,armada-375-timer";
+				reg = <0x20300 0x30>, <0x21040 0x30>;
+				interrupts-extended = <&gic  0  8 4>,
+						      <&gic  0  9 4>,
+						      <&gic  0 10 4>,
+						      <&gic  0 11 4>,
+						      <&mpic 5>,
+						      <&mpic 6>;
+				clocks = <&coreclk 0>;
+			};
+
+			xor at 60800 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60800 0x100
+				       0x60A00 0x100>;
+				clocks = <&gateclk 22>;
+				status = "okay";
+
+				xor00 {
+					interrupts = <0 22 0x4>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor01 {
+					interrupts = <0 23 0x4>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			xor at 60900 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60900 0x100
+				       0x60b00 0x100>;
+				clocks = <&gateclk 23>;
+				status = "okay";
+
+				xor10 {
+					interrupts = <0 65 0x4>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor11 {
+					interrupts = <0 66 0x4>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			sata at a0000 {
+				compatible = "marvell,orion-sata";
+				reg = <0xa0000 0x5000>;
+				interrupts = <0 26 0x4>;
+				clocks = <&gateclk 14>, <&gateclk 20>;
+				clock-names = "0", "1";
+				status = "disabled";
+			};
+
+			mvsdio at d4000 {
+				compatible = "marvell,orion-sdio";
+				reg = <0xd4000 0x200>;
+				interrupts = <0 25 0x4>;
+				clocks = <&gateclk 17>;
+				bus-width = <4>;
+				cap-sdio-irq;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				status = "disabled";
+			};
+
+			coreclk: mvebu-sar at e8204 {
+				compatible = "marvell,armada-375-core-clock";
+				reg = <0xe8204 0x04>;
+				#clock-cells = <1>;
+			};
+
+			coredivclk: corediv-clock at e8250 {
+				compatible = "marvell,armada-375-corediv-clock";
+				reg = <0xe8250 0xc>;
+				#clock-cells = <1>;
+				clocks = <&mainpll>;
+				clock-output-names = "nand";
+			};
+		};
+
+		pcie-controller {
+			compatible = "marvell,armada-370-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			msi-parent = <&mpic>;
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
+				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
+				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
+				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
+
+			pcie at 1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 29 0x4>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 5>;
+				status = "disabled";
+			};
+
+			pcie at 2,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 33 0x4>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <1>;
+				clocks = <&gateclk 6>;
+				status = "disabled";
+			};
+
+		};
+	};
+};
-- 
1.8.3.2

[PATCH 05/11] ARM: mvebu: add Device Tree for the Armada 375 DB board

[Thomas Petazzoni]

The Armada 375 DB board is the development board from Marvell for the
Armada 375 SoC. This commit adds a Device Tree description for this
board, which enables the following features:

 * I2C buses
 * SDIO
 * Serial port
 * SPI bus, with a SPI flash. Note that the SPI bus is disabled by
   default, because it conflicts with the NAND, and can only work if
   the board boots out of SPI. Since most boards are shipped to boot
   out of NAND, we're default to having the SPI bus disabled.
 * PCIe interfaces

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/Makefile          |   1 +
 arch/arm/boot/dts/armada-375-db.dts | 106 ++++++++++++++++++++++++++++++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-375-db.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b..f1eafbd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
 	armada-370-netgear-rn102.dtb \
 	armada-370-netgear-rn104.dtb \
 	armada-370-rd.dtb \
+	armada-375-db.dtb \
 	armada-xp-axpwifiap.dtb \
 	armada-xp-db.dtb \
 	armada-xp-gp.dtb \
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
new file mode 100644
index 0000000..7b46fe2
--- /dev/null
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -0,0 +1,106 @@
+/*
+ * Device Tree file for Marvell Armada 375 evaluation board
+ * (DB-88F6720)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "armada-375.dtsi"
+
+/ {
+	model = "Marvell Armada 375 Development Board";
+	compatible = "marvell,a375-db", "marvell,armada375";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1 GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi0: spi at 10600 {
+				pinctrl-0 = <&spi0_pins>;
+				pinctrl-names = "default";
+				/*
+				 * SPI conflicts with NAND, so we disable it
+				 * here, and select NAND as the enabled device
+				 * by default.
+				 */
+				status = "disabled";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "n25q128a13";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <108000000>;
+				};
+			};
+
+			i2c0: i2c at 11000 {
+				status = "okay";
+				clock-frequency = <100000>;
+				pinctrl-0 = <&i2c0_pins>;
+				pinctrl-names = "default";
+			};
+
+			i2c1: i2c at 11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+				pinctrl-0 = <&i2c1_pins>;
+				pinctrl-names = "default";
+			};
+
+			serial at 12000 {
+				clock-frequency = <200000000>;
+				status = "okay";
+			};
+
+			pinctrl {
+				sdio_st_pins: sdio-st-pins {
+					marvell,pins = "mpp44", "mpp45";
+					marvell,function = "gpio";
+				};
+			};
+
+			mvsdio at d4000 {
+				pinctrl-0 = <&sdio_pins &sdio_st_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+				cd-gpios = <&gpio1 12 0>;
+				wp-gpios = <&gpio1 13 0>;
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+			/*
+			 * The two PCIe units are accessible through
+			 * standard PCIe slots on the board.
+			 */
+			pcie at 1,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+			pcie at 2,0 {
+				/* Port 1, Lane 0 */
+				status = "okay";
+			};
+		};
+	};
+};
-- 
1.8.3.2

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Thomas Petazzoni]

This commit adds support for the Armada 380/385 SoCs in the
system-controller driver. Since this SoC has the same system
controller registers layout than the Armada 370/XP at least for the
few features currently supported by the driver, this commit simply
adds a new compatible string that provides the same behavior than the
one provided for Armada 370/XP.

Note that we intentionally do not use the same compatible string as
Armada 370/XP, as the current system-controller driver is far from
exploiting all the possibilities of the hardware, and we may in the
future discover differences between Armada 370/XP and Armada 380/385.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 Documentation/devicetree/bindings/arm/mvebu-system-controller.txt | 3 ++-
 arch/arm/mach-mvebu/system-controller.c                           | 8 ++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
index d24ab2e..3559972 100644
--- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
@@ -1,6 +1,6 @@
 MVEBU System Controller
 -----------------------
-MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
+MVEBU (Marvell SOCs: Armada 370/375/38x/XP, Dove, mv78xx0, Kirkwood, Orion5x)
 
 Required properties:
 
@@ -8,6 +8,7 @@ Required properties:
 	- "marvell,orion-system-controller"
 	- "marvell,armada-370-xp-system-controller"
 	- "marvell,armada-375-system-controller"
+	- "marvell,armada-380-system-controller"
 - reg: Should contain system controller registers location and length.
 
 Example:
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 1806187..b4e8bb2 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -71,6 +71,14 @@ static struct of_device_id of_system_controller_table[] = {
 	}, {
 		.compatible = "marvell,armada-375-system-controller",
 		.data = (void *) &armada_375_system_controller,
+	}, {
+		/*
+		 * As far as RSTOUTn and System soft reset registers
+		 * are concerned, Armada 38x is similar to Armada
+		 * 370/XP
+		 */
+		.compatible = "marvell,armada-380-system-controller",
+		.data = (void *) &armada_370_xp_system_controller,
 	},
 	{ /* end of list */ },
 };
-- 
1.8.3.2

[PATCH 07/11] ARM: mvebu: add initial support for the Armada 380/385 SOCs

[Thomas Petazzoni]

This commit adds the basic support for the Armada 380 and Armada 385
SOCs. These SoCs share most of their IP with the Armada 370/XP
SoCs. The main difference is the use of a Cortex A9 CPU instead of the
PJ4B CPU. The Armada 380 is a single core Cortex-A9, while the Armada
385 is a dual-core Cortex-A9.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../devicetree/bindings/arm/armada-38x.txt         | 10 ++++++
 arch/arm/mach-mvebu/Kconfig                        | 15 ++++++++
 arch/arm/mach-mvebu/Makefile                       |  1 +
 arch/arm/mach-mvebu/armada-38x.c                   | 42 ++++++++++++++++++++++
 4 files changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-38x.txt
 create mode 100644 arch/arm/mach-mvebu/armada-38x.c

diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt
new file mode 100644
index 0000000..11f2330
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-38x.txt
@@ -0,0 +1,10 @@
+Marvell Armada 38x Platforms Device Tree Bindings
+-------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 38x family shall have the
+following property:
+
+Required root node property:
+
+ - compatible: must contain either "marvell,armada380" or
+   "marvell,armada385" depending on the variant of the SoC being used.
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 3aefdcd..7d01583 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -52,6 +52,21 @@ config MACH_ARMADA_375
 	  Say 'Y' here if you want your kernel to support boards based
 	  on the Marvell Armada 375 SoC with device tree.
 
+config MACH_ARMADA_380
+	bool "Marvell Armada 380/385 boards"
+	select ARM_ERRATA_720789
+	select ARM_ERRATA_753970
+	select ARM_GIC
+	select ARMADA_370_XP_TIMER
+	select ARMADA_38X_CLK
+	select CACHE_L2X0
+	select CPU_V7
+	select NEON
+	select PINCTRL_ARMADA_38X
+	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada 380/385 SoC with device tree.
+
 config MACH_ARMADA_XP
 	bool "Marvell Armada XP boards"
 	select ARMADA_XP_CLK
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 9862e0f..7a439f9 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -6,6 +6,7 @@ AFLAGS_coherency_ll.o		:= -Wa,-march=armv7-a
 obj-y				 += system-controller.o mvebu-soc-id.o
 obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
 obj-$(CONFIG_MACH_ARMADA_375)    += armada-375.o
+obj-$(CONFIG_MACH_ARMADA_380)    += armada-38x.o
 obj-$(CONFIG_ARCH_MVEBU)	 += coherency.o coherency_ll.o pmsu.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
diff --git a/arch/arm/mach-mvebu/armada-38x.c b/arch/arm/mach-mvebu/armada-38x.c
new file mode 100644
index 0000000..936f606
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada-38x.c
@@ -0,0 +1,42 @@
+/*
+ * Device Tree support for Armada 380/385 platforms.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
+#include <linux/mbus.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include "common.h"
+
+static void __init armada_380_timer_and_clk_init(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+	BUG_ON(mvebu_mbus_dt_init());
+	l2x0_of_init(0, ~0UL);
+}
+
+static const char * const armada_380_dt_compat[] = {
+	"marvell,armada380",
+	"marvell,armada385",
+	NULL,
+};
+
+DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 380/385 (Device Tree)")
+	.init_time	= armada_380_timer_and_clk_init,
+	.restart	= mvebu_restart,
+	.dt_compat	= armada_380_dt_compat,
+MACHINE_END
-- 
1.8.3.2

[PATCH 08/11] ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs

[Thomas Petazzoni]

The Armada 380 and 385 SoCs are new SoCs from Marvell, based on a
Cortex-A9 cores (single core for 380, dual core for 385) and a number
of hardware blocks that are common with earlier SoCs from the mvebu
family.

The provided Device Tree describes the following parts of the SoC:

 * CPU
 * Device Bus
 * Clocks
 * Interrupt controllers: GIC and MPIC
 * GPIO controllers
 * I2C buses
 * L2 cache
 * MBus controller
 * Pinctrl
 * Serial
 * SPI buses
 * System controller (for reboot)
 * Timer
 * XOR engines
 * PCIe controllers
 * Network interfaces

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-380.dtsi | 117 +++++++++++++
 arch/arm/boot/dts/armada-385.dtsi | 149 +++++++++++++++++
 arch/arm/boot/dts/armada-38x.dtsi | 339 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 605 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-380.dtsi
 create mode 100644 arch/arm/boot/dts/armada-385.dtsi
 create mode 100644 arch/arm/boot/dts/armada-38x.dtsi

diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
new file mode 100644
index 0000000..5a46ec7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -0,0 +1,117 @@
+/*
+ * Device Tree Include file for Marvell Armada 380 SoC.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "armada-38x.dtsi"
+
+/ {
+	model = "Marvell Armada 380 family SoC";
+	compatible = "marvell,armada380", "marvell,armada38x";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		internal-regs {
+			pinctrl {
+				compatible = "marvell,mv88f6810-pinctrl";
+				reg = <0x18000 0x20>;
+			};
+		};
+
+		pcie-controller {
+			compatible = "marvell,armada-370-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			msi-parent = <&mpic>;
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
+				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
+				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */>;
+
+			/* x1 port */
+			pcie at 1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 29 0x4>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 8>;
+				status = "disabled";
+			};
+
+			/* x1 port */
+			pcie at 2,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 33 0x4>;
+				marvell,pcie-port = <1>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 5>;
+				status = "disabled";
+			};
+
+			/* x1 port */
+			pcie at 3,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 70 0x4>;
+				marvell,pcie-port = <2>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 6>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
new file mode 100644
index 0000000..b22f5f1
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -0,0 +1,149 @@
+/*
+ * Device Tree Include file for Marvell Armada 385 SoC.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "armada-38x.dtsi"
+
+/ {
+	model = "Marvell Armada 385 family SoC";
+	compatible = "marvell,armada385", "marvell,armada38x";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		internal-regs {
+			pinctrl {
+				compatible = "marvell,mv88f6820-pinctrl";
+				reg = <0x18000 0x20>;
+			};
+		};
+
+		pcie-controller {
+			compatible = "marvell,armada-370-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			msi-parent = <&mpic>;
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
+				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
+				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
+				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
+				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
+
+			/*
+			 * This port can be either x4 or x1. When
+			 * configured in x4 by the bootloader, then
+			 * pcie at 4,0 is not available.
+			 */
+			pcie at 1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 29 0x4>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 8>;
+				status = "disabled";
+			};
+
+			/* x1 port */
+			pcie at 2,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 33 0x4>;
+				marvell,pcie-port = <1>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 5>;
+				status = "disabled";
+			};
+
+			/* x1 port */
+			pcie at 3,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 70 0x4>;
+				marvell,pcie-port = <2>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 6>;
+				status = "disabled";
+			};
+
+			/*
+			 * x1 port only available when pcie at 1,0 is
+			 * configured as a x1 port
+			 */
+			pcie at 4,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic 0 71 0x4>;
+				marvell,pcie-port = <3>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 7>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
new file mode 100644
index 0000000..43bfbf6
--- /dev/null
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -0,0 +1,339 @@
+/*
+ * Device Tree Include file for Marvell Armada 38x family of SoCs.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+/ {
+	model = "Marvell Armada 38x family SoC";
+	compatible = "marvell,armada38x";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+	};
+
+	soc {
+		compatible = "marvell,armada380-mbus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		controller = <&mbusc>;
+		interrupt-parent = <&gic>;
+		pcie-mem-aperture = <0xe0000000 0x8000000>;
+		pcie-io-aperture  = <0xe8000000 0x100000>;
+
+		bootrom {
+			compatible = "marvell,bootrom";
+			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
+		};
+
+		devbus-bootcs {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs0 {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs1 {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs2 {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		devbus-cs3 {
+			compatible = "marvell,mvebu-devbus";
+			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&coreclk 0>;
+			status = "disabled";
+		};
+
+		internal-regs {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+			L2: cache-controller at 8000 {
+				compatible = "arm,pl310-cache";
+				reg = <0x8000 0x1000>;
+				cache-unified;
+				cache-level = <2>;
+			};
+
+			timer at c600 {
+				compatible = "arm,cortex-a9-twd-timer";
+				reg = <0xc600 0x20>;
+				interrupts = <1 13 0x301>;
+				clocks = <&coreclk 2>;
+			};
+
+			gic: interrupt-controller at d000 {
+				compatible = "arm,cortex-a9-gic";
+				#interrupt-cells = <3>;
+				#size-cells = <0>;
+				interrupt-controller;
+				reg = <0xd000 0x1000>,
+				      <0xc100 0x100>;
+			};
+
+			spi0: spi at 10600 {
+				compatible = "marvell,orion-spi";
+				reg = <0x10600 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <0>;
+				interrupts = <0 1 0x4>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			spi1: spi at 10680 {
+				compatible = "marvell,orion-spi";
+				reg = <0x10680 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <1>;
+				interrupts = <0 63 0x4>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c0: i2c at 11000 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11000 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <0 2 0x4>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 11100 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11100 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <0 3 0x4>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			serial at 12000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12000 0x100>;
+				reg-shift = <2>;
+				interrupts = <0 12 4>;
+				reg-io-width = <1>;
+				status = "disabled";
+			};
+
+			serial at 12100 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12100 0x100>;
+				reg-shift = <2>;
+				interrupts = <0 13 4>;
+				reg-io-width = <1>;
+				status = "disabled";
+			};
+
+			pinctrl {
+				compatible = "marvell,mv88f6820-pinctrl";
+				reg = <0x18000 0x20>;
+			};
+
+			gpio0: gpio at 18100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18100 0x40>;
+				ngpios = <32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 53 0x4>, <0 54 0x4>,
+					     <0 55 0x4>, <0 56 0x4>;
+			};
+
+			gpio1: gpio at 18140 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18140 0x40>;
+				ngpios = <28>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 58 0x4>, <0 59 0x4>,
+					     <0 60 0x4>, <0 61 0x4>;
+			};
+
+			system-controller at 18200 {
+				compatible = "marvell,armada-380-system-controller";
+				reg = <0x18200 0x100>;
+			};
+
+			gateclk: clock-gating-control at 18220 {
+				compatible = "marvell,armada-380-gating-clock";
+				reg = <0x18220 0x4>;
+				clocks = <&coreclk 0>;
+				#clock-cells = <1>;
+			};
+
+			coreclk: mvebu-sar at 18600 {
+				compatible = "marvell,armada-380-core-clock";
+				reg = <0x18600 0x04>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller at 20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x20180 0x20>;
+			};
+
+			mpic: interrupt-controller at 20000 {
+				compatible = "marvell,mpic";
+				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+				#interrupt-cells = <1>;
+				#size-cells = <1>;
+				interrupt-controller;
+				msi-controller;
+				interrupts = <1 15 0x4>;
+			};
+
+			timer at 20300 {
+				compatible = "marvell,armada-380-timer";
+				reg = <0x20300 0x30>, <0x21040 0x30>;
+				interrupts-extended = <&gic  0  8 4>,
+						      <&gic  0  9 4>,
+						      <&gic  0 10 4>,
+						      <&gic  0 11 4>,
+						      <&mpic 5>,
+						      <&mpic 6>;
+				clocks = <&coreclk 2>, <&refclk>;
+				clock-names = "nbclk", "fixed";
+			};
+
+			eth1: ethernet at 30000 {
+				compatible = "marvell,armada-370-neta";
+				reg = <0x30000 0x4000>;
+				interrupts-extended = <&mpic 10>;
+				clocks = <&gateclk 3>;
+				status = "disabled";
+			};
+
+			eth2: ethernet at 34000 {
+				compatible = "marvell,armada-370-neta";
+				reg = <0x34000 0x4000>;
+				interrupts-extended = <&mpic 12>;
+				clocks = <&gateclk 2>;
+				status = "disabled";
+			};
+
+			xor at 60800 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60800 0x100
+				       0x60a00 0x100>;
+				clocks = <&gateclk 22>;
+				status = "okay";
+
+				xor00 {
+					interrupts = <0 22 0x4>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor01 {
+					interrupts = <0 23 0x4>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			xor at 60900 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60900 0x100
+				       0x60b00 0x100>;
+				clocks = <&gateclk 28>;
+				status = "okay";
+
+				xor10 {
+					interrupts = <0 65 0x4>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor11 {
+					interrupts = <0 66 0x4>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			eth0: ethernet at 70000 {
+				compatible = "marvell,armada-370-neta";
+				reg = <0x70000 0x4000>;
+				interrupts-extended = <&mpic 8>;
+				clocks = <&gateclk 4>;
+				status = "disabled";
+			};
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "marvell,orion-mdio";
+				reg = <0x72004 0x4>;
+			};
+		};
+	};
+
+	clocks {
+		/* 25 MHz reference crystal */
+		refclk: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+	};
+};
-- 
1.8.3.2

[PATCH 09/11] ARM: mvebu: add Device Tree for the Armada 385 DB board

[Thomas Petazzoni]

The Armada 385 DB board is the development board from Marvell for the
Armada 385 SoC. This commit adds a Device Tree description for this
board, which enables the following features:

 * Network interfaces
 * I2C buses
 * SDIO
 * Serial port
 * SPI bus, with a SPI flash
 * PCIe interfaces

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/Makefile          |   1 +
 arch/arm/boot/dts/armada-385-db.dts | 101 ++++++++++++++++++++++++++++++++++++
 2 files changed, 102 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-385-db.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f1eafbd..bd789fc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -127,6 +127,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
 	armada-370-netgear-rn104.dtb \
 	armada-370-rd.dtb \
 	armada-375-db.dtb \
+	armada-385-db.dtb \
 	armada-xp-axpwifiap.dtb \
 	armada-xp-db.dtb \
 	armada-xp-gp.dtb \
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
new file mode 100644
index 0000000..566601c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -0,0 +1,101 @@
+/*
+ * Device Tree file for Marvell Armada 385 evaluation board
+ * (DB-88F6820)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+
+/ {
+	model = "Marvell Armada 385 Development Board";
+	compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>; /* 256 MB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi0: spi at 10600 {
+				status = "okay";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "w25q32";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <108000000>;
+				};
+			};
+
+			i2c0: i2c at 11000 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};
+
+			i2c1: i2c at 11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};
+
+			serial at 12000 {
+				clock-frequency = <200000000>;
+				status = "okay";
+			};
+
+			ethernet at 30000 {
+				status = "okay";
+				phy = <&phy1>;
+				phy-mode = "rgmii";
+			};
+
+			ethernet at 70000 {
+				status = "okay";
+				phy = <&phy0>;
+				phy-mode = "rgmii";
+			};
+
+			mdio {
+				phy0: ethernet-phy at 0 {
+					reg = <0>;
+				};
+
+				phy1: ethernet-phy at 1 {
+					reg = <1>;
+				};
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+			/*
+			 * The two PCIe units are accessible through
+			 * standard PCIe slots on the board.
+			 */
+			pcie at 1,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+			pcie at 2,0 {
+				/* Port 1, Lane 0 */
+				status = "okay";
+			};
+		};
+	};
+};
-- 
1.8.3.2

[PATCH 10/11] ARM: mvebu: update defconfigs for Armada 375 and 38x

[Thomas Petazzoni]

This commit enables the Armada 375 and Armada 38x support in
mvebu_defconfig and multi_v7_defconfig.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/configs/multi_v7_defconfig | 2 ++
 arch/arm/configs/mvebu_defconfig    | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 845bc74..d5371e6 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -9,6 +9,8 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
+CONFIG_MACH_ARMADA_375=y
+CONFIG_MACH_ARMADA_380=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM_MOBILE=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 0f4511d..d63dfe4 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -10,6 +10,8 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
+CONFIG_MACH_ARMADA_375=y
+CONFIG_MACH_ARMADA_380=y
 CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
-- 
1.8.3.2

[PATCH 11/11] Documentation: arm: update Marvell documentation about Armada 375/38x

[Thomas Petazzoni]

This commit updates the documentation that describes the various
families of SOCs produced by Marvell, together with the corresponding
available technical documents. It adds Armada 375 and Armada 38x, and
adds a link to the product brief for the already supported Armada 370.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 Documentation/arm/Marvell/README | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index 5a930c1..963ec44 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -83,14 +83,24 @@ EBU Armada family
         88F6710
         88F6707
         88F6W11
+    Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf
+
+  Armada 375 Flavors:
+	88F6720
+    Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA_375_SoC-01_product_brief.pdf
+
+  Armada 380/385 Flavors:
+	88F6810
+	88F6820
+	88F6828
 
   Armada XP Flavors:
         MV78230
         MV78260
         MV78460
     NOTE: not to be confused with the non-SMP 78xx0 SoCs
+    Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
 
-  Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
   No public datasheet available.
 
   Core: Sheeva ARMv7 compatible
-- 
1.8.3.2

[PATCH 04/11] ARM: mvebu: add Device Tree description of the Armada 375 SoC

[Jason Cooper]

On Mon, Feb 10, 2014 at 06:23:15PM +0100, Thomas Petazzoni wrote:
> From: Gregory CLEMENT <gregory.clement@free-electrons.com>
> 
> The Armada 375 SoC is a new SoC from Marvell, based on a dual core
> Cortex-A9 and a number of hardware blocks that are common with earlier
> SoCs from the mvebu family.
> 
> The provided Device Tree describes the following parts of the SoC:
> 
>  * CPUs
>  * Device Bus
>  * Clocks
>  * Interrupt controllers: GIC and MPIC
>  * GPIO controllers
>  * I2C buses
>  * L2 cache
>  * MBus controller
>  * SDIO
>  * Pinctrl
>  * SATA
>  * Serial
>  * SPI buses
>  * System controller (for reboot)
>  * Timer
>  * XOR engines
>  * PCIe controllers
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-375.dtsi | 439 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 439 insertions(+)
>  create mode 100644 arch/arm/boot/dts/armada-375.dtsi
> 
> diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
> new file mode 100644
> index 0000000..2697345
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-375.dtsi
> @@ -0,0 +1,439 @@
> +/*
> + * Device Tree Include file for Marvell Armada 375 family SoC
> + *
> + * Copyright (C) 2014 Marvell
> + *
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
> +
> +/ {
> +	model = "Marvell Armada 375 family SoC";
> +	compatible = "marvell,armada375";
> +
> +	aliases {
> +		gpio0 = &gpio0;
> +		gpio1 = &gpio1;
> +		gpio2 = &gpio2;
> +	};
> +
> +	clocks {
> +		/* 2 GHz fixed main PLL */
> +		mainpll: mainpll {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <2000000000>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0>;
> +		};
> +		cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <1>;
> +		};
> +	};
> +
> +	soc {
...
> +		internal-regs {
...
> +			gateclk: clock-gating-control at 18220 {
> +				compatible = "marvell,armada-375-gating-clock";
> +				reg = <0x18220 0x4>;
> +				clocks = <&coreclk 0>;
> +				#clock-cells = <1>;
> +			};
> +
...
> +			coreclk: mvebu-sar at e8204 {
> +				compatible = "marvell,armada-375-core-clock";
> +				reg = <0xe8204 0x04>;
> +				#clock-cells = <1>;
> +			};
> +
> +			coredivclk: corediv-clock at e8250 {
> +				compatible = "marvell,armada-375-corediv-clock";
> +				reg = <0xe8250 0xc>;
> +				#clock-cells = <1>;
> +				clocks = <&mainpll>;
> +				clock-output-names = "nand";
> +			};

Thanks for putting the internal-regs nodes in order so I didn't have to
ask.  :) Have you noticed the same problem as the other SoCs with clock
ordering on bootup?

thx,

Jason.

[PATCH 04/11] ARM: mvebu: add Device Tree description of the Armada 375 SoC

[Gregory CLEMENT]

On 10/02/2014 18:35, Jason Cooper wrote:
> On Mon, Feb 10, 2014 at 06:23:15PM +0100, Thomas Petazzoni wrote:
>> From: Gregory CLEMENT <gregory.clement@free-electrons.com>
>>
>> The Armada 375 SoC is a new SoC from Marvell, based on a dual core
>> Cortex-A9 and a number of hardware blocks that are common with earlier
>> SoCs from the mvebu family.
>>
>> The provided Device Tree describes the following parts of the SoC:
>>
>>  * CPUs
>>  * Device Bus
>>  * Clocks
>>  * Interrupt controllers: GIC and MPIC
>>  * GPIO controllers
>>  * I2C buses
>>  * L2 cache
>>  * MBus controller
>>  * SDIO
>>  * Pinctrl
>>  * SATA
>>  * Serial
>>  * SPI buses
>>  * System controller (for reboot)
>>  * Timer
>>  * XOR engines
>>  * PCIe controllers
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> ---
>>  arch/arm/boot/dts/armada-375.dtsi | 439 ++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 439 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/armada-375.dtsi
>>
>> diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
>> new file mode 100644
>> index 0000000..2697345
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-375.dtsi
>> @@ -0,0 +1,439 @@
>> +/*
>> + * Device Tree Include file for Marvell Armada 375 family SoC
>> + *
>> + * Copyright (C) 2014 Marvell
>> + *
>> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
>> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
>> +
>> +/ {
>> +	model = "Marvell Armada 375 family SoC";
>> +	compatible = "marvell,armada375";
>> +
>> +	aliases {
>> +		gpio0 = &gpio0;
>> +		gpio1 = &gpio1;
>> +		gpio2 = &gpio2;
>> +	};
>> +
>> +	clocks {
>> +		/* 2 GHz fixed main PLL */
>> +		mainpll: mainpll {
>> +			compatible = "fixed-clock";
>> +			#clock-cells = <0>;
>> +			clock-frequency = <2000000000>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		cpu at 0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a9";
>> +			reg = <0>;
>> +		};
>> +		cpu at 1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a9";
>> +			reg = <1>;
>> +		};
>> +	};
>> +
>> +	soc {
> ...
>> +		internal-regs {
> ...
>> +			gateclk: clock-gating-control at 18220 {
>> +				compatible = "marvell,armada-375-gating-clock";
>> +				reg = <0x18220 0x4>;
>> +				clocks = <&coreclk 0>;
>> +				#clock-cells = <1>;
>> +			};
>> +
> ...
>> +			coreclk: mvebu-sar at e8204 {
>> +				compatible = "marvell,armada-375-core-clock";
>> +				reg = <0xe8204 0x04>;
>> +				#clock-cells = <1>;
>> +			};
>> +
>> +			coredivclk: corediv-clock at e8250 {
>> +				compatible = "marvell,armada-375-corediv-clock";
>> +				reg = <0xe8250 0xc>;
>> +				#clock-cells = <1>;
>> +				clocks = <&mainpll>;
>> +				clock-output-names = "nand";
>> +			};
> 
> Thanks for putting the internal-regs nodes in order so I didn't have to
> ask.  :) Have you noticed the same problem as the other SoCs with clock
> ordering on bootup?

Yes :(

> 
> thx,
> 
> Jason.
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH 05/11] ARM: mvebu: add Device Tree for the Armada 375 DB board

[Andrew Lunn]

Hi Thomas

> +			mvsdio at d4000 {
> +				pinctrl-0 = <&sdio_pins &sdio_st_pins>;
> +				pinctrl-names = "default";
> +				status = "okay";
> +				cd-gpios = <&gpio1 12 0>;
> +				wp-gpios = <&gpio1 13 0>;

Kirkwood recently started using include/dt-bindings/gpio/gpio.h. Maybe
you can do the same here?

    Andrew

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Jason Cooper]

On Mon, Feb 10, 2014 at 06:23:17PM +0100, Thomas Petazzoni wrote:
> This commit adds support for the Armada 380/385 SoCs in the
> system-controller driver. Since this SoC has the same system
> controller registers layout than the Armada 370/XP at least for the
> few features currently supported by the driver, this commit simply
> adds a new compatible string that provides the same behavior than the
> one provided for Armada 370/XP.
> 
> Note that we intentionally do not use the same compatible string as
> Armada 370/XP, as the current system-controller driver is far from
> exploiting all the possibilities of the hardware, and we may in the
> future discover differences between Armada 370/XP and Armada 380/385.

I'd much prefer to add a new compatible string iff it accompanies
incompatible changes.

For now, I think it's best to use 'marvell,armada-370-xp-system-controller'
in the dtsi file and change it when you introduce the incompatible
features.

thx,

Jason.

> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/arm/mvebu-system-controller.txt | 3 ++-
>  arch/arm/mach-mvebu/system-controller.c                           | 8 ++++++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
> index d24ab2e..3559972 100644
> --- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
> +++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
> @@ -1,6 +1,6 @@
>  MVEBU System Controller
>  -----------------------
> -MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
> +MVEBU (Marvell SOCs: Armada 370/375/38x/XP, Dove, mv78xx0, Kirkwood, Orion5x)
>  
>  Required properties:
>  
> @@ -8,6 +8,7 @@ Required properties:
>  	- "marvell,orion-system-controller"
>  	- "marvell,armada-370-xp-system-controller"
>  	- "marvell,armada-375-system-controller"
> +	- "marvell,armada-380-system-controller"
>  - reg: Should contain system controller registers location and length.
>  
>  Example:
> diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
> index 1806187..b4e8bb2 100644
> --- a/arch/arm/mach-mvebu/system-controller.c
> +++ b/arch/arm/mach-mvebu/system-controller.c
> @@ -71,6 +71,14 @@ static struct of_device_id of_system_controller_table[] = {
>  	}, {
>  		.compatible = "marvell,armada-375-system-controller",
>  		.data = (void *) &armada_375_system_controller,
> +	}, {
> +		/*
> +		 * As far as RSTOUTn and System soft reset registers
> +		 * are concerned, Armada 38x is similar to Armada
> +		 * 370/XP
> +		 */
> +		.compatible = "marvell,armada-380-system-controller",
> +		.data = (void *) &armada_370_xp_system_controller,
>  	},
>  	{ /* end of list */ },
>  };
> -- 
> 1.8.3.2
> 

[PATCH 07/11] ARM: mvebu: add initial support for the Armada 380/385 SOCs

[Andrew Lunn]

Hi Thomas

> +config MACH_ARMADA_380

Should this maybe be MACH_ARMADA_38X. You have PINCTRL_ARMADA_38X, so
it seems a bit inconsistent.

> +
> +static void __init armada_380_timer_and_clk_init(void)
> +{
> +	of_clk_init(NULL);
> +	clocksource_of_init();
> +	BUG_ON(mvebu_mbus_dt_init());
> +	l2x0_of_init(0, ~0UL);
> +}
> +
> +static const char * const armada_380_dt_compat[] = {
> +	"marvell,armada380",
> +	"marvell,armada385",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 380/385 (Device Tree)")
> +	.init_time	= armada_380_timer_and_clk_init,
> +	.restart	= mvebu_restart,
> +	.dt_compat	= armada_380_dt_compat,
> +MACHINE_END

This looks very similar to the 375 code. Could they be combined?

     Andrew

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Thomas Petazzoni]

Dear Jason Cooper,

On Mon, 10 Feb 2014 12:39:57 -0500, Jason Cooper wrote:

> > Note that we intentionally do not use the same compatible string as
> > Armada 370/XP, as the current system-controller driver is far from
> > exploiting all the possibilities of the hardware, and we may in the
> > future discover differences between Armada 370/XP and Armada 380/385.
> 
> I'd much prefer to add a new compatible string iff it accompanies
> incompatible changes.
> 
> For now, I think it's best to use 'marvell,armada-370-xp-system-controller'
> in the dtsi file and change it when you introduce the incompatible
> features.

This doesn't work really well: if an user keeps an old DTB around,
which uses the old compatible string, then you're screwed because
there's no way a new kernel version can make the distinction between
Armada 370/XP and Armada 380/385. If we discover than Armada 380/385
need a special quirk to really work reliably for example, but that this
quirk doesn't apply to Armada 370/XP, then you have a serious problem.

Therefore, I would like to really insist to have separate compatible
strings for different SOCs. As an example, we used to have the same
compatible string for the timer between Armada 370 and Armada XP, and
later discovered that it was not possible due to a bug affecting only
one of the two SOCs. Our experience clearly shows that sharing
compatible strings is a bad idea, and having separate compatible
strings from the beginning doesn't cost anything, and offers higher
flexibility for the future.

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 05/11] ARM: mvebu: add Device Tree for the Armada 375 DB board

[Thomas Petazzoni]

Dear Andrew Lunn,

On Mon, 10 Feb 2014 18:37:59 +0100, Andrew Lunn wrote:
> Hi Thomas
> 
> > +			mvsdio at d4000 {
> > +				pinctrl-0 = <&sdio_pins &sdio_st_pins>;
> > +				pinctrl-names = "default";
> > +				status = "okay";
> > +				cd-gpios = <&gpio1 12 0>;
> > +				wp-gpios = <&gpio1 13 0>;
> 
> Kirkwood recently started using include/dt-bindings/gpio/gpio.h. Maybe
> you can do the same here?

Sure, will do for the v2!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 00/11] Core support for Marvell Armada 375 and 38x

[Jason Gunthorpe]

On Mon, Feb 10, 2014 at 06:23:11PM +0100, Thomas Petazzoni wrote:

> It is worth noting that contrary to the Marvell 370 and XP support,
> which has been pushed mainline fairly late in the development cycle of
> the SOCs, the support for Armada 375 and 38x is now being pushed quite
> early in the development cycle of the SOCs. We are having mainline
> support pretty much at the same time as the SOCs are being made
> available to customers, which is really great!

Congratulations to Marvell, this is a major achievement!

Jason

[PATCH 07/11] ARM: mvebu: add initial support for the Armada 380/385 SOCs

[Thomas Petazzoni]

Dear Andrew Lunn,

On Mon, 10 Feb 2014 18:44:04 +0100, Andrew Lunn wrote:

> > +config MACH_ARMADA_380
> 
> Should this maybe be MACH_ARMADA_38X. You have PINCTRL_ARMADA_38X, so
> it seems a bit inconsistent.

True, will fix this in v2.

> > +static void __init armada_380_timer_and_clk_init(void)
> > +{
> > +	of_clk_init(NULL);
> > +	clocksource_of_init();
> > +	BUG_ON(mvebu_mbus_dt_init());
> > +	l2x0_of_init(0, ~0UL);
> > +}
> > +
> > +static const char * const armada_380_dt_compat[] = {
> > +	"marvell,armada380",
> > +	"marvell,armada385",
> > +	NULL,
> > +};
> > +
> > +DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 380/385 (Device Tree)")
> > +	.init_time	= armada_380_timer_and_clk_init,
> > +	.restart	= mvebu_restart,
> > +	.dt_compat	= armada_380_dt_compat,
> > +MACHINE_END
> 
> This looks very similar to the 375 code. Could they be combined?

It is not entirely clear at this point how different they will be. For
now, the external abort workaround applies only to Armada 375, but that
can easily be checked by looking at the DT compatible string. Maybe we
can decide to have a common file for now, and split it later on if we
realize that the differences are too complex?

Only problem with that (but a problem that is often difficult to
solve) : what should be the same of this file? armada-375-38x.c ?

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Jason Cooper]

On Mon, Feb 10, 2014 at 06:47:26PM +0100, Thomas Petazzoni wrote:
> Dear Jason Cooper,
> 
> On Mon, 10 Feb 2014 12:39:57 -0500, Jason Cooper wrote:
> 
> > > Note that we intentionally do not use the same compatible string as
> > > Armada 370/XP, as the current system-controller driver is far from
> > > exploiting all the possibilities of the hardware, and we may in the
> > > future discover differences between Armada 370/XP and Armada 380/385.
> > 
> > I'd much prefer to add a new compatible string iff it accompanies
> > incompatible changes.
> > 
> > For now, I think it's best to use 'marvell,armada-370-xp-system-controller'
> > in the dtsi file and change it when you introduce the incompatible
> > features.
> 
> This doesn't work really well: if an user keeps an old DTB around,
> which uses the old compatible string, then you're screwed because
> there's no way a new kernel version can make the distinction between
> Armada 370/XP and Armada 380/385. 

devicetree is designed to handle this.  The dtb is _supposed_ to be
separate from the kernel.

> If we discover than Armada 380/385 need a special quirk to really work
> reliably for example, but that this quirk doesn't apply to Armada
> 370/XP, then you have a serious problem.

No, you don't.  It's the responsibility of the driver author to _not_
make incompatible changes and to sanely fall back to default behavior.

Right now there are no differences, and both SoCs work with the same
compatible string.  If later there is support added for a feature for
one of them, we add a compatible string to differentiate the two.  When
the driver encounters a potentially old dtb, it defaults to behaving as
it does today.  iow, no new feature.

In this situation, the driver or SoC code could see the root compatible
node is marvell,armada385 with a sys-con node using
marvell,armada-370-xp-sys-con.  It could then print a warning about
potentially old dtb.  Depending on the severity of the bug (which
couldn't be too severe, otherwise you'd have code here today ;) ), you
could even override the compatible string in the SoC code.

> Therefore, I would like to really insist to have separate compatible
> strings for different SOCs. As an example, we used to have the same
> compatible string for the timer between Armada 370 and Armada XP, and
> later discovered that it was not possible due to a bug affecting only
> one of the two SOCs. Our experience clearly shows that sharing
> compatible strings is a bad idea, and having separate compatible
> strings from the beginning doesn't cost anything, and offers higher
> flexibility for the future.

Your argument is tempting, but I see a lot of over-quantization with
little to no measurable gain other than "just in case."

If I follow your logic and refer to the i2c transaction generator
problem, should we go back and add compatible strings for all on-die IP
blocks for every SoC and SoC revision?  Even though we only wish we had
something once?  Can we anticipate every possible way an IP block will
be broken?

Ultimately, what I'm saying is that the devicetree process should be
able to handle this kind of situation.  And if it can't, the process is
broken.  No amount of bubblewrap and safety helmets will save us then.

Now, wrt marvell,armada-38x-system-controller, if you can point out
specific features you know about *today* that are different from the
370/xp sys-con, please spell them out at least in the commit log.  I'm
fine with just mentioning the features at this point, since we're
dealing with initial SoC support.  But "...we may in the future discover
differences between..." doesn't inspire confidence.

thx,

Jason.

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Thomas Petazzoni]

Dear Jason Cooper,

On Mon, 10 Feb 2014 13:48:57 -0500, Jason Cooper wrote:

> > This doesn't work really well: if an user keeps an old DTB around,
> > which uses the old compatible string, then you're screwed because
> > there's no way a new kernel version can make the distinction between
> > Armada 370/XP and Armada 380/385. 
> 
> devicetree is designed to handle this.  The dtb is _supposed_ to be
> separate from the kernel.

Exactly. Which is the whole point why your strategy doesn't work. Since
the DTB is supposed to be separate from the kernel, we have no
guarantee that the user will update the DTB when updating the kernel.
Therefore, we have to keep compatibility for old DTBs, which forces us
to be extra cautious when choosing compatible strings.

> > If we discover than Armada 380/385 need a special quirk to really work
> > reliably for example, but that this quirk doesn't apply to Armada
> > 370/XP, then you have a serious problem.
> 
> No, you don't.  It's the responsibility of the driver author to _not_
> make incompatible changes and to sanely fall back to default behavior.

This is not always possible. If we discover that the 38x system
controller has a bug that needs to be worked around in a way that isn't
suitable for Armada 370/XP, then there is *no* way for the driver
author to keep backward compatibility.

> Right now there are no differences, and both SoCs work with the same
> compatible string.  If later there is support added for a feature for
> one of them, we add a compatible string to differentiate the two.  When
> the driver encounters a potentially old dtb, it defaults to behaving as
> it does today.  iow, no new feature.

This only works if you *add* new features. Not if you have to get back
to existing features and make changes that have to be different between
the SOCs to fix bugs for existing features.

> In this situation, the driver or SoC code could see the root compatible
> node is marvell,armada385 with a sys-con node using
> marvell,armada-370-xp-sys-con.  It could then print a warning about
> potentially old dtb.  Depending on the severity of the bug (which
> couldn't be too severe, otherwise you'd have code here today ;) ), you
> could even override the compatible string in the SoC code.

This seems overly complicated compared to the simple usage of different
compatible strings per-SoC.

At least, I'd like your policy to be baked by statements from the DT
maintainers because I am not sure this policy is universally accepted.

> > Therefore, I would like to really insist to have separate compatible
> > strings for different SOCs. As an example, we used to have the same
> > compatible string for the timer between Armada 370 and Armada XP, and
> > later discovered that it was not possible due to a bug affecting only
> > one of the two SOCs. Our experience clearly shows that sharing
> > compatible strings is a bad idea, and having separate compatible
> > strings from the beginning doesn't cost anything, and offers higher
> > flexibility for the future.
> 
> Your argument is tempting, but I see a lot of over-quantization with
> little to no measurable gain other than "just in case."

Did you see the very real example of "just in case" I described in the
paragraph just above, with the Armada 370/XP timer? This "just in case"
lead us to break compatibility with old DTs, and have a broken kernel
until -rc4 or -rc5, due to issues in merging the necessary DT changes
and driver changes.

To me, your policy is simply ignoring the experience.

> If I follow your logic and refer to the i2c transaction generator
> problem, should we go back and add compatible strings for all on-die IP
> blocks for every SoC and SoC revision?  Even though we only wish we had
> something once?  Can we anticipate every possible way an IP block will
> be broken?

Hard to anticipate all the cases, but when we can, we should do it.
Armada 370/XP and Armada 38x are *very* different SOCs. They don't use
the same CPU core, the same cache controller, the same interrupt
controller, a large number of peripherals have changed. The likely-hood
of discovering differences is fairly high.

> Ultimately, what I'm saying is that the devicetree process should be
> able to handle this kind of situation.  And if it can't, the process is
> broken.  No amount of bubblewrap and safety helmets will save us then.
> 
> Now, wrt marvell,armada-38x-system-controller, if you can point out
> specific features you know about *today* that are different from the
> 370/xp sys-con, please spell them out at least in the commit log.  I'm
> fine with just mentioning the features at this point, since we're
> dealing with initial SoC support.  But "...we may in the future discover
> differences between..." doesn't inspire confidence.

Have you ever had a look at a very early datasheet? It seems like not.
The datasheet details at this stage of the SoC development are very
limited as the datasheet is still being written. Remember that we are
talking about a SoC that has not even been announced publicly on the
SoC vendor web site.

We had to get back to Marvell many, many times to have enough details
to understand various aspects of the SoC. So yes, we may very well
discover differences in the future, simply because we have no way,
today, to have a clear view of all aspects of the SoC.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Grant Likely]

On Mon, Feb 10, 2014 at 5:39 PM, Jason Cooper <jason@lakedaemon.net> wrote:
> On Mon, Feb 10, 2014 at 06:23:17PM +0100, Thomas Petazzoni wrote:
>> This commit adds support for the Armada 380/385 SoCs in the
>> system-controller driver. Since this SoC has the same system
>> controller registers layout than the Armada 370/XP at least for the
>> few features currently supported by the driver, this commit simply
>> adds a new compatible string that provides the same behavior than the
>> one provided for Armada 370/XP.
>>
>> Note that we intentionally do not use the same compatible string as
>> Armada 370/XP, as the current system-controller driver is far from
>> exploiting all the possibilities of the hardware, and we may in the
>> future discover differences between Armada 370/XP and Armada 380/385.
>
> I'd much prefer to add a new compatible string iff it accompanies
> incompatible changes.
>
> For now, I think it's best to use 'marvell,armada-370-xp-system-controller'
> in the dtsi file and change it when you introduce the incompatible
> features.

Actually, they are doing the right thing here. It is completely
appropriate to encode the SoC version into the compatible string, but
then to retain compatibility with the older device driver by including
the earlier compatible string in the compatible list so that no code
changes are required.

g.

>
> thx,
>
> Jason.
>
>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> ---
>>  Documentation/devicetree/bindings/arm/mvebu-system-controller.txt | 3 ++-
>>  arch/arm/mach-mvebu/system-controller.c                           | 8 ++++++++
>>  2 files changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
>> index d24ab2e..3559972 100644
>> --- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
>> +++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
>> @@ -1,6 +1,6 @@
>>  MVEBU System Controller
>>  -----------------------
>> -MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
>> +MVEBU (Marvell SOCs: Armada 370/375/38x/XP, Dove, mv78xx0, Kirkwood, Orion5x)
>>
>>  Required properties:
>>
>> @@ -8,6 +8,7 @@ Required properties:
>>       - "marvell,orion-system-controller"
>>       - "marvell,armada-370-xp-system-controller"
>>       - "marvell,armada-375-system-controller"
>> +     - "marvell,armada-380-system-controller"
>>  - reg: Should contain system controller registers location and length.
>>
>>  Example:
>> diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
>> index 1806187..b4e8bb2 100644
>> --- a/arch/arm/mach-mvebu/system-controller.c
>> +++ b/arch/arm/mach-mvebu/system-controller.c
>> @@ -71,6 +71,14 @@ static struct of_device_id of_system_controller_table[] = {
>>       }, {
>>               .compatible = "marvell,armada-375-system-controller",
>>               .data = (void *) &armada_375_system_controller,
>> +     }, {
>> +             /*
>> +              * As far as RSTOUTn and System soft reset registers
>> +              * are concerned, Armada 38x is similar to Armada
>> +              * 370/XP
>> +              */
>> +             .compatible = "marvell,armada-380-system-controller",
>> +             .data = (void *) &armada_370_xp_system_controller,

However, this would not be the right thing to do. The better solution
is to put the following into the .dts file:

compatible = "marvell,armada-380-system-controller","marvell,armada-370-system-controller"

So that the kernel has the option to override the 370 version if an
errata or extra feature support ever needs to be added.

g.

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Thomas Petazzoni]

Grant,

On Tue, 11 Feb 2014 14:22:04 +0000, Grant Likely wrote:

> >> +     }, {
> >> +             /*
> >> +              * As far as RSTOUTn and System soft reset registers
> >> +              * are concerned, Armada 38x is similar to Armada
> >> +              * 370/XP
> >> +              */
> >> +             .compatible = "marvell,armada-380-system-controller",
> >> +             .data = (void *) &armada_370_xp_system_controller,
> 
> However, this would not be the right thing to do. The better solution
> is to put the following into the .dts file:
> 
> compatible = "marvell,armada-380-system-controller","marvell,armada-370-system-controller"
> 
> So that the kernel has the option to override the 370 version if an
> errata or extra feature support ever needs to be added.

Ah, right true. Makes sense. We are going to update our patch set to
take this suggestion into account, and resubmit a v2 with this. This
way, we don't need new to introduce in drivers new compatible strings
for the clocksource driver, the mbus driver and the system-controller
driver.

Thanks Grant for your suggestion.

Jason, are you ok with this?

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Jason Cooper]

On Tue, Feb 11, 2014 at 04:24:36PM +0100, Thomas Petazzoni wrote:
> Grant,
> 
> On Tue, 11 Feb 2014 14:22:04 +0000, Grant Likely wrote:
> 
> > >> +     }, {
> > >> +             /*
> > >> +              * As far as RSTOUTn and System soft reset registers
> > >> +              * are concerned, Armada 38x is similar to Armada
> > >> +              * 370/XP
> > >> +              */
> > >> +             .compatible = "marvell,armada-380-system-controller",
> > >> +             .data = (void *) &armada_370_xp_system_controller,
> > 
> > However, this would not be the right thing to do. The better solution
> > is to put the following into the .dts file:
> > 
> > compatible = "marvell,armada-380-system-controller","marvell,armada-370-system-controller"
> > 
> > So that the kernel has the option to override the 370 version if an
> > errata or extra feature support ever needs to be added.
> 
> Ah, right true. Makes sense. We are going to update our patch set to
> take this suggestion into account, and resubmit a v2 with this. This
> way, we don't need new to introduce in drivers new compatible strings
> for the clocksource driver, the mbus driver and the system-controller
> driver.
> 
> Thanks Grant for your suggestion.
> 
> Jason, are you ok with this?

Yes.  Thanks Grant for clearing this up.  And thanks guys for tolerating
my "This doesn't look right, but I'm having trouble explaining how"
moment :)

thx,

Jason.

[PATCH 06/11] ARM: mvebu: add Armada 380/385 support to the system-controller driver

[Gregory CLEMENT]

On 11/02/2014 16:30, Jason Cooper wrote:
> On Tue, Feb 11, 2014 at 04:24:36PM +0100, Thomas Petazzoni wrote:
>> Grant,
>>
>> On Tue, 11 Feb 2014 14:22:04 +0000, Grant Likely wrote:
>>
>>>>> +     }, {
>>>>> +             /*
>>>>> +              * As far as RSTOUTn and System soft reset registers
>>>>> +              * are concerned, Armada 38x is similar to Armada
>>>>> +              * 370/XP
>>>>> +              */
>>>>> +             .compatible = "marvell,armada-380-system-controller",
>>>>> +             .data = (void *) &armada_370_xp_system_controller,
>>>
>>> However, this would not be the right thing to do. The better solution
>>> is to put the following into the .dts file:
>>>
>>> compatible = "marvell,armada-380-system-controller","marvell,armada-370-system-controller"
>>>
>>> So that the kernel has the option to override the 370 version if an
>>> errata or extra feature support ever needs to be added.
>>
>> Ah, right true. Makes sense. We are going to update our patch set to
>> take this suggestion into account, and resubmit a v2 with this. This
>> way, we don't need new to introduce in drivers new compatible strings
>> for the clocksource driver, the mbus driver and the system-controller
>> driver.
>>
>> Thanks Grant for your suggestion.
>>
>> Jason, are you ok with this?
> 
> Yes.  Thanks Grant for clearing this up.  And thanks guys for tolerating
> my "This doesn't look right, but I'm having trouble explaining how"
> moment :)

Great, with this solution we have the better of the two options:
the ability to deal with different behaviors of the IP without
having to update the dts and no code added in the drivers files.


> 
> thx,
> 
> Jason.
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com