From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 03/13] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU
Date: Wed, 19 Feb 2014 17:09:07 +0100 [thread overview]
Message-ID: <20140219170907.002941da@skate> (raw)
In-Reply-To: <1392312816-17657-4-git-send-email-gregory.clement@free-electrons.com>
Dear Gregory CLEMENT,
On Thu, 13 Feb 2014 18:33:26 +0100, Gregory CLEMENT wrote:
> ll_set_cpu_coherent is always used on the current CPU, so instead of
> passing the CPU id as argument, ll_set_cpu_coherent() can find it by
> itself.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> arch/arm/mach-mvebu/coherency.c | 10 +++++-----
> arch/arm/mach-mvebu/coherency.h | 2 +-
> arch/arm/mach-mvebu/coherency_ll.S | 12 ++++++------
> arch/arm/mach-mvebu/headsmp.S | 4 ----
> arch/arm/mach-mvebu/platsmp.c | 2 +-
> 5 files changed, 13 insertions(+), 17 deletions(-)
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
with just one thing I am not entirely sure about:
> /* Create bit by cpu index */
> - mov r3, #(1 << 24)
> - lsl r1, r3, r1
> -ARM_BE8(rev r1, r1)
> + mrc 15, 0, r1, cr0, cr0, 5
> + and r1, r1, #15
> + mov r2, #(1 << 24)
> + lsl r1, r2, r1
> + ARM_BE8(rev r1, r1)
Have you tested this in a big endian configuration? I'd like to make
sure we have gotten the ARM_BE8(rev ...) thing correct.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
next prev parent reply other threads:[~2014-02-19 16:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-13 17:33 [PATCH v4 00/13] CPU idle for Armada XP Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 01/13] ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B Gregory CLEMENT
2014-02-14 16:06 ` Lorenzo Pieralisi
2014-03-25 22:57 ` Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 02/13] ARM: mvebu: remove the address parameter for ll_set_cpu_coherent Gregory CLEMENT
2014-02-19 16:06 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 03/13] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU Gregory CLEMENT
2014-02-19 16:09 ` Thomas Petazzoni [this message]
2014-02-19 16:17 ` Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 04/13] ARM: mvebu: Remove the unused argument of set_cpu_coherent() Gregory CLEMENT
2014-02-19 16:27 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 05/13] ARM: mvebu: Low level function to disable HW coherency support Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 06/13] ARM: mvebu: Add a new set of registers for pmsu Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 07/13] ARM: dts: mvebu: Add a new set of registers to the PMSU node Gregory CLEMENT
2014-02-17 2:57 ` Jason Cooper
2014-02-19 16:00 ` Thomas Petazzoni
2014-02-19 17:49 ` Gregory CLEMENT
2014-02-19 18:21 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 08/13] ARM: mvebu: Allow to power down L2 cache controller in idle mode Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 09/13] ARM: mvebu: Add the PMSU related part of the cpu idle functions Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 10/13] ARM: mvebu: Set the start address of a CPU in a separate function Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 11/13] ARM: mvebu: Register notifier callback for the cpuidle transition Gregory CLEMENT
2014-02-13 17:33 ` [PATCH v4 12/13] cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC Gregory CLEMENT
2014-02-14 17:00 ` Lorenzo Pieralisi
2014-03-25 22:57 ` Gregory CLEMENT
2014-02-17 8:49 ` Daniel Lezcano
2014-03-25 22:57 ` Gregory CLEMENT
2014-02-19 16:51 ` Thomas Petazzoni
2014-02-19 17:19 ` Gregory CLEMENT
2014-02-19 18:32 ` Thomas Petazzoni
2014-02-13 17:33 ` [PATCH v4 13/13] ARM: mvebu: register the cpuidle driver for the Armada XP SoCs Gregory CLEMENT
2014-02-19 16:46 ` Thomas Petazzoni
2014-02-19 16:52 ` Gregory CLEMENT
2014-02-19 17:01 ` Thomas Petazzoni
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