From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: Possible mistake in defining TTBR cache-able attributes for v7-2 level ?
Date: Fri, 14 Mar 2014 15:53:59 +0000 [thread overview]
Message-ID: <20140314155359.GH18126@arm.com> (raw)
In-Reply-To: <CAPub149amJ0Aa7Y8DLkHbkQzcKFfr--d8oiuFsw7MMokAia4xw@mail.gmail.com>
On Fri, Mar 14, 2014 at 01:46:27PM +0000, Shiraz Hashim wrote:
> TTB_IRGN_WBWA macro defined in arch/arm/mm/proc-v7-2level.S, seems incorrect
>
> #define TTB_IRGN_WBWA ? ((0 << 0) | (1 << 6))
>
> Its intention seems to program as write back and write allocate whereas it
> actually
> programs it? write-through,
>
> From ARM TRM
>
> The possible values of IRGN[1:0] are:
> ? 0b00 Normal memory, Inner Non-cacheable.
> ? 0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
> ? 0b10 Normal memory, Inner Write-Through Cacheable.
> ? 0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
>
> --IRGN[0] is b'0 and IRGN[1] is b'6
In the ARMv7 ARM, IRGN[0] is bit 6 and IRGN[1] is bit 0. Which TRM is
this?
--
Catalin
next parent reply other threads:[~2014-03-14 15:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CAPub149amJ0Aa7Y8DLkHbkQzcKFfr--d8oiuFsw7MMokAia4xw@mail.gmail.com>
2014-03-14 15:53 ` Catalin Marinas [this message]
2014-03-15 13:07 ` Possible mistake in defining TTBR cache-able attributes for v7-2 level ? Shiraz Hashim
2014-03-15 15:00 ` bhupesh.sharma at freescale.com
2014-03-15 23:14 ` Catalin Marinas
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