From: carlo@caione.org (Carlo Caione)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 0/3] ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller
Date: Tue, 25 Mar 2014 22:27:35 +0100 [thread overview]
Message-ID: <20140325212735.GA4853@localhost.fastwebnet.it> (raw)
In-Reply-To: <1395256879-8475-1-git-send-email-carlo@caione.org>
On Wed, Mar 19, 2014 at 08:21:16PM +0100, Carlo Caione wrote:
> Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI.
> Three register are present to (un)mask, control and acknowledge NMI.
> These two patches add a new irqchip driver in cascade with GIC.
Hi Thomas,
Is this ok with the Maxime ACKs?
--
Carlo Caione
prev parent reply other threads:[~2014-03-25 21:27 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-19 19:21 [PATCH v7 0/3] ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller Carlo Caione
2014-03-19 19:21 ` [PATCH v7 1/3] ARM: sun7i/sun6i: irqchip: Add irqchip " Carlo Caione
2014-03-19 19:21 ` [PATCH v7 2/3] ARM: sun7i/sun6i: dts: Add NMI irqchip support Carlo Caione
2014-03-20 15:17 ` Maxime Ripard
2014-03-26 8:39 ` Hans de Goede
2014-03-26 9:39 ` Maxime Ripard
2014-03-26 10:04 ` Hans de Goede
2014-03-26 14:38 ` Hans de Goede
2014-03-26 20:24 ` Carlo Caione
2014-03-19 19:21 ` [PATCH v7 3/3] ARM: sun7i/sun6i: irqchip: Update the documentation Carlo Caione
2014-03-20 15:17 ` Maxime Ripard
2014-03-25 21:27 ` Carlo Caione [this message]
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