From mboxrd@z Thu Jan  1 00:00:00 1970
From: linux@arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 28 Mar 2014 13:02:36 +0000
Subject: *READ THIS IF YOUR SOC HAS A L2 CACHE* PL310 auxctrl settings
In-Reply-To: <5335704F.4090502@st.com>
References: <20140314144835.GP21483@n2100.arm.linux.org.uk>
 <20140316152953.GX21483@n2100.arm.linux.org.uk>
 <CAL_JsqLDun2VkCFK9Fec6n38bNz2w9mscPdXcGYeLiZtiXkVDg@mail.gmail.com>
 <20140318112221.GV21483@n2100.arm.linux.org.uk> <5335704F.4090502@st.com>
Message-ID: <20140328130236.GG7528@n2100.arm.linux.org.uk>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On Fri, Mar 28, 2014 at 01:51:27PM +0100, Maxime Coquelin wrote:
> On 03/18/2014 12:22 PM, Russell King - ARM Linux wrote:
>> arch/arm/mach-sti/board-dt.c:                           Y  30480000 c0000fff
>
> For STiH416 SoC, the reset value of the AUX_CTRL register is 0x02000000.
> So bits 19:17 = 0, whereas the expected value is bits 19:17 = 4.

Which L2 cache is it?  210/220/310 ?

Thanks.

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