* [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0
@ 2014-04-03 2:40 dinguyen at altera.com
2014-04-03 2:40 ` [PATCH 2/2] ARM: dts: socfpga: Remove hard coded clock-frequency property dinguyen at altera.com
2014-04-03 5:19 ` [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0 Steffen Trumtrar
0 siblings, 2 replies; 5+ messages in thread
From: dinguyen at altera.com @ 2014-04-03 2:40 UTC (permalink / raw)
To: linux-arm-kernel
From: Dinh Nguyen <dinguyen@altera.com>
The Altera Cyclone5 and Arria5 devkit has an EEPROM, LCD and a RTC on the
board. This patch adds support for them.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
arch/arm/boot/dts/socfpga_arria5_socdk.dts | 22 ++++++++++++++++++++++
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 22 ++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 88e4a8e..674dcf8 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -59,3 +59,25 @@
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
};
+
+&i2c0 {
+ status = "okay";
+ lcd: lcd at 28 {
+ compatible = "newhaven,nhd-0216k3z-nsw-bbw";
+ reg = <0x28>;
+ height = <2>;
+ width = <16>;
+ brightness = <8>;
+ };
+
+ eeprom at 51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc at 68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 5e9445a..0d85021 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -52,3 +52,25 @@
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
};
+
+&i2c0 {
+ status = "okay";
+ lcd: lcd at 28 {
+ compatible = "newhaven,nhd-0216k3z-nsw-bbw";
+ reg = <0x28>;
+ height = <2>;
+ width = <16>;
+ brightness = <8>;
+ };
+
+ eeprom at 51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+
+ rtc at 68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] ARM: dts: socfpga: Remove hard coded clock-frequency property
2014-04-03 2:40 [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0 dinguyen at altera.com
@ 2014-04-03 2:40 ` dinguyen at altera.com
2014-04-03 5:32 ` Steffen Trumtrar
2014-04-03 5:19 ` [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0 Steffen Trumtrar
1 sibling, 1 reply; 5+ messages in thread
From: dinguyen at altera.com @ 2014-04-03 2:40 UTC (permalink / raw)
To: linux-arm-kernel
From: Dinh Nguyen <dinguyen@altera.com>
The timers and uart can get their clock frequencies using the common clock
driver.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
arch/arm/boot/dts/socfpga.dtsi | 10 ++++++++++
arch/arm/boot/dts/socfpga_arria5.dtsi | 24 ------------------------
arch/arm/boot/dts/socfpga_cyclone5.dtsi | 24 ------------------------
3 files changed, 10 insertions(+), 48 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 039cebb..df43702 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -630,24 +630,32 @@
compatible = "snps,dw-apb-timer";
interrupts = <0 167 4>;
reg = <0xffc08000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer";
};
timer1: timer1 at ffc09000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 168 4>;
reg = <0xffc09000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer";
};
timer2: timer2 at ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 169 4>;
reg = <0xffd00000 0x1000>;
+ clocks = <&osc1>;
+ clock-names = "timer";
};
timer3: timer3 at ffd01000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 170 4>;
reg = <0xffd01000 0x1000>;
+ clocks = <&osc1>;
+ clock-names = "timer";
};
uart0: serial0 at ffc02000 {
@@ -656,6 +664,7 @@
interrupts = <0 162 4>;
reg-shift = <2>;
reg-io-width = <4>;
+ clocks = <&l4_sp_clk>;
};
uart1: serial1 at ffc03000 {
@@ -664,6 +673,7 @@
interrupts = <0 163 4>;
reg-shift = <2>;
reg-io-width = <4>;
+ clocks = <&l4_sp_clk>;
};
rstmgr at ffd05000 {
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 373b340..12d1c2c 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -38,32 +38,8 @@
};
};
- serial0 at ffc02000 {
- clock-frequency = <100000000>;
- };
-
- serial1 at ffc03000 {
- clock-frequency = <100000000>;
- };
-
sysmgr at ffd08000 {
cpu1-start-addr = <0xffd080c4>;
};
-
- timer0 at ffc08000 {
- clock-frequency = <100000000>;
- };
-
- timer1 at ffc09000 {
- clock-frequency = <100000000>;
- };
-
- timer2 at ffd00000 {
- clock-frequency = <25000000>;
- };
-
- timer3 at ffd01000 {
- clock-frequency = <25000000>;
- };
};
};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 63a9513..bf51182 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -45,30 +45,6 @@
status = "okay";
};
- timer0 at ffc08000 {
- clock-frequency = <100000000>;
- };
-
- timer1 at ffc09000 {
- clock-frequency = <100000000>;
- };
-
- timer2 at ffd00000 {
- clock-frequency = <25000000>;
- };
-
- timer3 at ffd01000 {
- clock-frequency = <25000000>;
- };
-
- serial0 at ffc02000 {
- clock-frequency = <100000000>;
- };
-
- serial1 at ffc03000 {
- clock-frequency = <100000000>;
- };
-
sysmgr at ffd08000 {
cpu1-start-addr = <0xffd080c4>;
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] ARM: dts: socfpga: Remove hard coded clock-frequency property
2014-04-03 2:40 ` [PATCH 2/2] ARM: dts: socfpga: Remove hard coded clock-frequency property dinguyen at altera.com
@ 2014-04-03 5:32 ` Steffen Trumtrar
0 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2014-04-03 5:32 UTC (permalink / raw)
To: linux-arm-kernel
Hi!
On Wed, Apr 02, 2014 at 09:40:34PM -0500, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
>
> The timers and uart can get their clock frequencies using the common clock
> driver.
>
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> arch/arm/boot/dts/socfpga.dtsi | 10 ++++++++++
> arch/arm/boot/dts/socfpga_arria5.dtsi | 24 ------------------------
> arch/arm/boot/dts/socfpga_cyclone5.dtsi | 24 ------------------------
> 3 files changed, 10 insertions(+), 48 deletions(-)
>
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 039cebb..df43702 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -630,24 +630,32 @@
> compatible = "snps,dw-apb-timer";
> interrupts = <0 167 4>;
> reg = <0xffc08000 0x1000>;
> + clocks = <&l4_sp_clk>;
> + clock-names = "timer";
> };
>
> timer1: timer1 at ffc09000 {
> compatible = "snps,dw-apb-timer";
> interrupts = <0 168 4>;
> reg = <0xffc09000 0x1000>;
> + clocks = <&l4_sp_clk>;
> + clock-names = "timer";
> };
>
> timer2: timer2 at ffd00000 {
> compatible = "snps,dw-apb-timer";
> interrupts = <0 169 4>;
> reg = <0xffd00000 0x1000>;
> + clocks = <&osc1>;
> + clock-names = "timer";
> };
>
> timer3: timer3 at ffd01000 {
> compatible = "snps,dw-apb-timer";
> interrupts = <0 170 4>;
> reg = <0xffd01000 0x1000>;
> + clocks = <&osc1>;
> + clock-names = "timer";
> };
>
> uart0: serial0 at ffc02000 {
> @@ -656,6 +664,7 @@
> interrupts = <0 162 4>;
> reg-shift = <2>;
> reg-io-width = <4>;
> + clocks = <&l4_sp_clk>;
> };
>
> uart1: serial1 at ffc03000 {
> @@ -664,6 +673,7 @@
> interrupts = <0 163 4>;
> reg-shift = <2>;
> reg-io-width = <4>;
> + clocks = <&l4_sp_clk>;
> };
>
> rstmgr at ffd05000 {
> diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
> index 373b340..12d1c2c 100644
> --- a/arch/arm/boot/dts/socfpga_arria5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
> @@ -38,32 +38,8 @@
> };
> };
>
> - serial0 at ffc02000 {
> - clock-frequency = <100000000>;
> - };
> -
> - serial1 at ffc03000 {
> - clock-frequency = <100000000>;
> - };
> -
> sysmgr at ffd08000 {
> cpu1-start-addr = <0xffd080c4>;
> };
> -
> - timer0 at ffc08000 {
> - clock-frequency = <100000000>;
> - };
> -
> - timer1 at ffc09000 {
> - clock-frequency = <100000000>;
> - };
> -
> - timer2 at ffd00000 {
> - clock-frequency = <25000000>;
> - };
> -
> - timer3 at ffd01000 {
> - clock-frequency = <25000000>;
> - };
> };
> };
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> index 63a9513..bf51182 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> @@ -45,30 +45,6 @@
> status = "okay";
> };
>
> - timer0 at ffc08000 {
> - clock-frequency = <100000000>;
> - };
> -
> - timer1 at ffc09000 {
> - clock-frequency = <100000000>;
> - };
> -
> - timer2 at ffd00000 {
> - clock-frequency = <25000000>;
> - };
> -
> - timer3 at ffd01000 {
> - clock-frequency = <25000000>;
> - };
> -
> - serial0 at ffc02000 {
> - clock-frequency = <100000000>;
> - };
> -
> - serial1 at ffc03000 {
> - clock-frequency = <100000000>;
> - };
> -
> sysmgr at ffd08000 {
> cpu1-start-addr = <0xffd080c4>;
> };
Ah, good. I like getting rid of stuff like this. Looks okay to me:
Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Thanks,
Steffen
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0
2014-04-03 2:40 [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0 dinguyen at altera.com
2014-04-03 2:40 ` [PATCH 2/2] ARM: dts: socfpga: Remove hard coded clock-frequency property dinguyen at altera.com
@ 2014-04-03 5:19 ` Steffen Trumtrar
2014-04-03 22:33 ` Dinh Nguyen
1 sibling, 1 reply; 5+ messages in thread
From: Steffen Trumtrar @ 2014-04-03 5:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi!
On Wed, Apr 02, 2014 at 09:40:33PM -0500, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
>
> The Altera Cyclone5 and Arria5 devkit has an EEPROM, LCD and a RTC on the
> board. This patch adds support for them.
>
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> arch/arm/boot/dts/socfpga_arria5_socdk.dts | 22 ++++++++++++++++++++++
> arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 22 ++++++++++++++++++++++
> 2 files changed, 44 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
> index 88e4a8e..674dcf8 100644
> --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
> +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
> @@ -59,3 +59,25 @@
> rxdv-skew-ps = <0>;
> rxc-skew-ps = <2000>;
> };
> +
> +&i2c0 {
> + status = "okay";
> + lcd: lcd at 28 {
> + compatible = "newhaven,nhd-0216k3z-nsw-bbw";
> + reg = <0x28>;
> + height = <2>;
> + width = <16>;
> + brightness = <8>;
> + };
I would prefer if we have the display in an extra patch.
This seems simple and okay, but everybody should get a chance to at least
discuss this new binding+driver instead of just "hiding" it in this patch.
> +
> + eeprom at 51 {
> + compatible = "atmel,24c32";
> + reg = <0x51>;
> + pagesize = <32>;
> + };
> +
> + rtc at 68 {
> + compatible = "dallas,ds1339";
> + reg = <0x68>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> index 5e9445a..0d85021 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> @@ -52,3 +52,25 @@
> rxdv-skew-ps = <0>;
> rxc-skew-ps = <2000>;
> };
> +
> +&i2c0 {
> + status = "okay";
> + lcd: lcd at 28 {
> + compatible = "newhaven,nhd-0216k3z-nsw-bbw";
> + reg = <0x28>;
> + height = <2>;
> + width = <16>;
> + brightness = <8>;
> + };
> +
> + eeprom at 51 {
> + compatible = "atmel,24c32";
> + reg = <0x51>;
> + pagesize = <32>;
> + };
> +
> + rtc at 68 {
> + compatible = "dallas,ds1339";
> + reg = <0x68>;
> + };
> +};
> --
> 1.7.9.5
>
>
The rest looks okay.
Regards,
Steffen
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0
2014-04-03 5:19 ` [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0 Steffen Trumtrar
@ 2014-04-03 22:33 ` Dinh Nguyen
0 siblings, 0 replies; 5+ messages in thread
From: Dinh Nguyen @ 2014-04-03 22:33 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, 2014-04-03 at 07:19 +0200, Steffen Trumtrar wrote:
> Hi!
>
> On Wed, Apr 02, 2014 at 09:40:33PM -0500, dinguyen at altera.com wrote:
> > From: Dinh Nguyen <dinguyen@altera.com>
> >
> > The Altera Cyclone5 and Arria5 devkit has an EEPROM, LCD and a RTC on the
> > board. This patch adds support for them.
> >
> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> > ---
> > arch/arm/boot/dts/socfpga_arria5_socdk.dts | 22 ++++++++++++++++++++++
> > arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 22 ++++++++++++++++++++++
> > 2 files changed, 44 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
> > index 88e4a8e..674dcf8 100644
> > --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
> > +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
> > @@ -59,3 +59,25 @@
> > rxdv-skew-ps = <0>;
> > rxc-skew-ps = <2000>;
> > };
> > +
> > +&i2c0 {
> > + status = "okay";
> > + lcd: lcd at 28 {
> > + compatible = "newhaven,nhd-0216k3z-nsw-bbw";
> > + reg = <0x28>;
> > + height = <2>;
> > + width = <16>;
> > + brightness = <8>;
> > + };
>
> I would prefer if we have the display in an extra patch.
> This seems simple and okay, but everybody should get a chance to at least
> discuss this new binding+driver instead of just "hiding" it in this patch.
>
You're right. I forgot that the driver for this LCD display is not even
upstreamed yet.
Thanks,
Dinh
> > +
> > + eeprom at 51 {
> > + compatible = "atmel,24c32";
> > + reg = <0x51>;
> > + pagesize = <32>;
> > + };
> > +
> > + rtc at 68 {
> > + compatible = "dallas,ds1339";
> > + reg = <0x68>;
> > + };
> > +};
> > diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> > index 5e9445a..0d85021 100644
> > --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> > +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
> > @@ -52,3 +52,25 @@
> > rxdv-skew-ps = <0>;
> > rxc-skew-ps = <2000>;
> > };
> > +
> > +&i2c0 {
> > + status = "okay";
> > + lcd: lcd at 28 {
> > + compatible = "newhaven,nhd-0216k3z-nsw-bbw";
> > + reg = <0x28>;
> > + height = <2>;
> > + width = <16>;
> > + brightness = <8>;
> > + };
> > +
> > + eeprom at 51 {
> > + compatible = "atmel,24c32";
> > + reg = <0x51>;
> > + pagesize = <32>;
> > + };
> > +
> > + rtc at 68 {
> > + compatible = "dallas,ds1339";
> > + reg = <0x68>;
> > + };
> > +};
> > --
> > 1.7.9.5
> >
> >
>
> The rest looks okay.
>
> Regards,
> Steffen
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-04-03 22:33 UTC | newest]
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2014-04-03 2:40 [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0 dinguyen at altera.com
2014-04-03 2:40 ` [PATCH 2/2] ARM: dts: socfpga: Remove hard coded clock-frequency property dinguyen at altera.com
2014-04-03 5:32 ` Steffen Trumtrar
2014-04-03 5:19 ` [PATCH 1/2] ARM: socfpga: dts: add eeprom, lcd, and rtc on i2c0 Steffen Trumtrar
2014-04-03 22:33 ` Dinh Nguyen
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