From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: Help for doubt about why update SCTLR by cr_alignment every syscall,IRQ,exception ?
Date: Sat, 5 Apr 2014 10:43:13 +0100 [thread overview]
Message-ID: <20140405094313.GI7528@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <CAEjEV8DLk5fhQHMomrrO3h+_9=yo3pMiEvjXG7nOydJOWdf7zg@mail.gmail.com>
On Sat, Apr 05, 2014 at 01:41:17PM +0800, qixuan wu wrote:
> Dear King, all,
>
> If we enable CONFIG_ALIGNMENT_TRAP:
This code in arch/arm/kernel/head-common.S:
bicne r4, r0, #CR_A @ Clear 'A' bit
stmneia r7, {r0, r4} @ Save control register values
saves different values to cr_alignment and cr_no_alignment. One always
has the A bit cleared, the other may have the A bit set.
For ARMv5 and older, we must have the A bit set while in the kernel so
misaligned loads are aborted, so that they can be fixed up. This
behaviour is relied upon by the networking code amongst other places.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
next prev parent reply other threads:[~2014-04-05 9:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-05 5:41 Help for doubt about why update SCTLR by cr_alignment every syscall,IRQ,exception ? qixuan wu
2014-04-05 9:43 ` Russell King - ARM Linux [this message]
-- strict thread matches above, loose matches on Subject: below --
2014-04-09 1:22 Wuqixuan
[not found] <BB7C62C2B0732E4DA93834A501E846456C8F15D9@szxema505-mbx.china.huawei.com>
2014-04-13 19:29 ` Russell King - ARM Linux
2014-04-15 12:54 ` Wuqixuan
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