From: shawn.guo@linaro.org (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: L2 cache suspend/resume
Date: Sun, 6 Apr 2014 19:40:35 +0800 [thread overview]
Message-ID: <20140406114033.GC24260@dragon> (raw)
In-Reply-To: <20140405112700.GJ7528@n2100.arm.linux.org.uk>
On Sat, Apr 05, 2014 at 12:27:00PM +0100, Russell King - ARM Linux wrote:
> While looking through the L2 resume code paths, I notice that:
>
> * exynos
> * imx
> * tegra
>
> all resume their L2 caches from assembly code, rather than using
> outer_disable() before cpu_suspend(), and outer_resume() afterwards.
> From what I can see, these are all running in the secure world, so that
> isn't the reason.
>
> What is the reason for this difference? Can these three be converted to
> the outer_disable()...outer_resume() method?
For imx, the L2 power and therefore the memory array is retained in
suspend. We do not want to call outer_disable() to have these data
flushed, and need to restore L2 controller before MMU is enabled.
Shawn
next prev parent reply other threads:[~2014-04-06 11:40 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-05 11:27 L2 cache suspend/resume Russell King - ARM Linux
2014-04-06 11:40 ` Shawn Guo [this message]
2014-04-06 11:46 ` Russell King - ARM Linux
2014-04-06 12:19 ` Shawn Guo
2014-04-07 15:35 ` Stephen Warren
2014-04-08 2:46 ` Joseph Lo
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