From: shawn.guo@freescale.com (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] ARM i.MX6: Fix ethernet PLL clocks
Date: Wed, 9 Apr 2014 14:59:54 +0800 [thread overview]
Message-ID: <20140409065952.GD2611@dragon> (raw)
In-Reply-To: <5343E106.7070902@de.bosch.com>
On Tue, Apr 08, 2014 at 01:44:06PM +0200, Dirk Behme wrote:
> I'm no expert on this, but it seems to be able to use 100MHz or
> 125Mhz enet clock, you additionally have to set the ENABLE_100M
> (CCM_ANALOG_PLL_ENET[20]) or ENABLE_125M (CCM_ANALOG_PLL_ENET[19])
> bits. Which isn't done by above change,
The following two lines added by the patch should just do.
clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
> and even worse, it's not
> possible with switching from dedicated clk_pllv3_enet_set_rate() to
> the generic ones using the clk_enet_ref_table.
Hmm, I'm not sure I understand it. But why not possible?
Shawn
next prev parent reply other threads:[~2014-04-09 6:59 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-22 9:59 [PATCH] i.MX6 clock Sascha Hauer
2012-11-22 9:59 ` [PATCH 1/3] ARM i.MX6: rename PLLs according to datasheet Sascha Hauer
2012-11-22 9:59 ` [PATCH 2/3] ARM i.MX6: Fix ethernet PLL clocks Sascha Hauer
2012-11-22 11:32 ` Shawn Guo
2012-11-22 12:35 ` Sascha Hauer
2014-04-08 11:44 ` Dirk Behme
2014-04-09 6:59 ` Shawn Guo [this message]
2014-04-09 7:11 ` Dirk Behme
2012-11-22 9:59 ` [PATCH 3/3] ARM i.MX6: remove gate_mask from pllv3 Sascha Hauer
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