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From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] ARM: OMAP2+: AM43x: L2 cache support
Date: Thu, 10 Apr 2014 14:40:28 +0100	[thread overview]
Message-ID: <20140410134028.GL27282@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <53469C29.8050906@ti.com>

On Thu, Apr 10, 2014 at 06:57:05PM +0530, Sekhar Nori wrote:
> On Thursday 10 April 2014 05:46 PM, Sekhar Nori wrote:
> > This will work. NS_LOCKDOWN is required for L2C-220 as well and so I was
> > thinking about adding a new l2c220_enable() which will set the
> > NS_LOCKDOWN and then call l2c_enable()
> 
> Here is a patch for what I was saying above.
> 
> diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
> index c47ac8f..dc9e03b 100644
> --- a/arch/arm/include/asm/hardware/cache-l2x0.h
> +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
> @@ -105,6 +105,8 @@
>  #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK	(7 << 9)
>  #define L2X0_AUX_CTRL_ASSOC_SHIFT		13
>  #define L2X0_AUX_CTRL_ASSOC_MASK		(15 << 13)
> +/* L2C-220/310 common bits */
> +#define L2C_AUX_CTRL_NS_LOCKDOWN		BIT(26)
>  /* L2C-210 specific bits */
>  #define L210_AUX_CTRL_WRAP_DISABLE		BIT(12)
>  #define L210_AUX_CTRL_WA_OVERRIDE		BIT(23)
> @@ -113,7 +115,6 @@
>  #define L220_AUX_CTRL_EXCLUSIVE_CACHE		BIT(12)
>  #define L220_AUX_CTRL_FWA_SHIFT			23
>  #define L220_AUX_CTRL_FWA_MASK			(3 << 23)
> -#define L220_AUX_CTRL_NS_LOCKDOWN		BIT(26)
>  #define L220_AUX_CTRL_NS_INT_CTRL		BIT(27)
>  /* L2C-310 specific bits */
>  #define L310_AUX_CTRL_FULL_LINE_ZERO		BIT(0)	/* R2P0+ */
> @@ -122,7 +123,6 @@
>  #define L310_AUX_CTRL_EXCLUSIVE_CACHE		BIT(12)
>  #define L310_AUX_CTRL_ASSOCIATIVITY_16		BIT(16)
>  #define L310_AUX_CTRL_CACHE_REPLACE_RR		BIT(25)	/* R2P0+ */
> -#define L310_AUX_CTRL_NS_LOCKDOWN		BIT(26)

NAK.  The reason for this split is because the NS lockdown bit is *not*
on L2C-210, and so it does not deserve to be a "common" bit - because it
isn't common to all variants.

> @@ -764,7 +776,7 @@ static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
>  			power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis");
>  	}
>  
> -	l2c_enable(base, aux, num_lock);
> +	l2c220_enable(base, aux, num_lock);

My first reaction to this is to say NAK again - I don't want to create
a multi-layered maze of X calls Y calls Z.  Who's to say that The 220
won't need to do something different from 310 in the future?

-- 
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

  reply	other threads:[~2014-04-10 13:40 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-04 10:10 [PATCH v2 0/3] ARM: OMAP2+: AM437x: L2 cache support Sekhar Nori
2014-04-04 10:10 ` [PATCH v2 1/3] ARM: OMAP2+: L2 cache: allow different aux ctrl settings Sekhar Nori
2014-04-04 10:10 ` [PATCH v2 2/3] ARM: OMAP2+: L2 cache: get rid of init call Sekhar Nori
2014-04-04 10:10 ` [PATCH v2 3/3] ARM: OMAP2+: AM43x: L2 cache support Sekhar Nori
2014-04-04 10:18   ` Russell King - ARM Linux
2014-04-08 14:53     ` Sekhar Nori
2014-04-08 15:17       ` Santosh Shilimkar
2014-04-09  9:44         ` Sekhar Nori
2014-04-09 16:33         ` Russell King - ARM Linux
2014-04-09 16:52           ` Santosh Shilimkar
2014-04-10 12:08             ` Sekhar Nori
2014-04-09 16:23       ` Russell King - ARM Linux
2014-04-10 11:56         ` Sekhar Nori
2014-04-10 12:03           ` Russell King - ARM Linux
2014-04-10 12:16             ` Sekhar Nori
2014-04-10 13:27               ` Sekhar Nori
2014-04-10 13:40                 ` Russell King - ARM Linux [this message]
2014-04-11  5:33                   ` Sekhar Nori
2014-04-11 11:25                     ` Russell King - ARM Linux
2014-04-11 12:01                       ` Sekhar Nori
2014-04-22  5:48                       ` Sekhar Nori

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