[PATCH] ARM: fix v7-M signal return

[u.kleine-koenig@pengutronix.de (Uwe Kleine-König)]

On Mon, Apr 21, 2014 at 08:07:44PM +0200, Rabin Vincent wrote:
> According to the ARM ARM, the behaviour is UNDPREDICTABLE if the PC read
> from the exception return stack is not half word aligned.  See the
> pseudo code for ExceptionReturn() and PopStack().
> 
> The signal handler's address has the bit 0 set, and setup_return()
> directly writes this to regs->ARM_pc.  Mask out bit 0 before the
> exception return to get predictable behaviour.
> 
> Signed-off-by: Rabin Vincent <rabin@rab.in>
> ---
>  arch/arm/kernel/entry-header.S | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
> index 1420725..ef72f4b 100644
> --- a/arch/arm/kernel/entry-header.S
> +++ b/arch/arm/kernel/entry-header.S
> @@ -133,6 +133,7 @@
>  	biceq	r5, V7M_xPSR_FRAMEPTRALIGN
>  
>  	@ write basic exception frame
> +	bic	r4, r4, #1
>  	stmdb	r2!, {r1, r3-r5}
>  	ldmia	sp, {r1, r3-r5}
>  	.if	\ret_r0
This is a valid fix, but it seems on my efm32 the unpredictable
behaviour is to just discard the LSB. How did you find that? Is it an
issue on your machine? Which cpu are you using?

I'd like to have the instruction clearing the thumb bit above the
comment about the basic exception frame and please add a comment for
your instruction, too.

Best regards
Uwe

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Pengutronix e.K.                           | Uwe Kleine-K?nig            |
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