From mboxrd@z Thu Jan 1 00:00:00 1970 From: catalin.marinas@arm.com (Catalin Marinas) Date: Fri, 9 May 2014 17:01:45 +0100 Subject: [PATH V3] arm64: mm: Optimise tlb flush logic where we have >4K granule In-Reply-To: <1399038540-6547-1-git-send-email-steve.capper@linaro.org> References: <1399038540-6547-1-git-send-email-steve.capper@linaro.org> Message-ID: <20140509160145.GL7950@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, May 02, 2014 at 02:49:00PM +0100, Steve Capper wrote: > The tlb maintainence functions: __cpu_flush_user_tlb_range and > __cpu_flush_kern_tlb_range do not take into consideration the page > granule when looping through the address range, and repeatedly flush > tlb entries for the same page when operating with 64K pages. > > This patch re-works the logic s.t. we instead advance the loop by > 1 << (PAGE_SHIFT - 12), so avoid repeating ourselves. > > Also the routines have been converted from assembler to static inline > functions to aid with legibility and potential compiler optimisations. > > The isb() has been removed from flush_tlb_kernel_range(.) as it is > only needed when changing the execute permission of a mapping. If one > needs to set an area of the kernel as execute/non-execute an isb() > must be inserted after the call to flush_tlb_kernel_range. > > Cc: Laura Abbott > Signed-off-by: Steve Capper > Acked-by: Will Deacon Applied. Thanks. -- Catalin