[PATCH] ARM: pci: add call to pcie_bus_configure_settings()

[PATCH] ARM: pci: add call to pcie_bus_configure_settings()

[Murali Karicheri]

PCI core supports PCIE_BUS_SAFE and PCIE_BUS_PERFORMANCE modes.
PCI controllers may not be able to handle pay load size higher
than MPS and also read data size higher than MRSS. So limit the
max to the least common supported payload size by calling
pcie_bus_configure_settings(). Using pci=pcie_bus_safe do a walk
and set the MPS to least common value used by devices on the bus.
pci=pcie_bus_perf does do a walk and set MRSS to MPS.

This is suggested as a better solution than pci quirk to do similar
thing.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>

CC: Russell King <linux@arm.linux.org.uk>
CC: Bjorn Helgaas <bhelgaas@google.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
 arch/arm/kernel/bios32.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 16d43cd..537f99e 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -545,6 +545,18 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
 		 */
 		pci_bus_add_devices(bus);
 	}
+
+	list_for_each_entry(sys, &head, node) {
+		struct pci_bus *bus = sys->bus;
+
+		/* Configure PCI Express settings */
+		if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
+			struct pci_bus *child;
+
+			list_for_each_entry(child, &bus->children, node)
+			pcie_bus_configure_settings(child);
+		}
+	}
 }
 
 #ifndef CONFIG_PCI_HOST_ITE8152
-- 
1.7.9.5

[PATCH] ARM: pci: add call to pcie_bus_configure_settings()

[Jason Gunthorpe]

On Wed, May 28, 2014 at 10:26:16AM -0400, Murali Karicheri wrote:
> PCI core supports PCIE_BUS_SAFE and PCIE_BUS_PERFORMANCE modes.
> PCI controllers may not be able to handle pay load size higher
> than MPS and also read data size higher than MRSS. So limit the
> max to the least common supported payload size by calling
> pcie_bus_configure_settings(). Using pci=pcie_bus_safe do a walk
> and set the MPS to least common value used by devices on the bus.
> pci=pcie_bus_perf does do a walk and set MRSS to MPS.

This text doesn't make much sense.. Calling
pcie_bus_configure_settings is just a good thing to do, the fact it
helps avoid a HW defect in a specific PCI-E implementation is not the
main reason to add this to the core ARM code.

 Call pcie_bus_configure_settings on ARM, like for other
 platforms. pcie_bus_configure_settings makes sure the MPS across the
 bus is uniform and provides the ability to tune the MRSS and MPS to
 higher performance values.

 This is particularly important for embedded where there is no
 firmware to program these PCI-E settings for the OS.

> +
> +			list_for_each_entry(child, &bus->children, node)
> +			pcie_bus_configure_settings(child);
                  ^^^^^^^^^^^^^^^

Missing indent.

Regards,
Jason

[PATCH] ARM: pci: add call to pcie_bus_configure_settings()

[Murali Karicheri]

On 5/28/2014 12:58 PM, Jason Gunthorpe wrote:
> On Wed, May 28, 2014 at 10:26:16AM -0400, Murali Karicheri wrote:
>> PCI core supports PCIE_BUS_SAFE and PCIE_BUS_PERFORMANCE modes.
>> PCI controllers may not be able to handle pay load size higher
>> than MPS and also read data size higher than MRSS. So limit the
>> max to the least common supported payload size by calling
>> pcie_bus_configure_settings(). Using pci=pcie_bus_safe do a walk
>> and set the MPS to least common value used by devices on the bus.
>> pci=pcie_bus_perf does do a walk and set MRSS to MPS.
> This text doesn't make much sense.. Calling
> pcie_bus_configure_settings is just a good thing to do, the fact it
> helps avoid a HW defect in a specific PCI-E implementation is not the
> main reason to add this to the core ARM code.
>
>   Call pcie_bus_configure_settings on ARM, like for other
>   platforms. pcie_bus_configure_settings makes sure the MPS across the
>   bus is uniform and provides the ability to tune the MRSS and MPS to
>   higher performance values.
>
>   This is particularly important for embedded where there is no
>   firmware to program these PCI-E settings for the OS.

Thanks. I will add this text for v1.
>
>> +
>> +			list_for_each_entry(child, &bus->children, node)
>> +			pcie_bus_configure_settings(child);
>                    ^^^^^^^^^^^^^^^
>
> Missing indent.
>
> Regards,
> Jason
Will fix in v1.

Thanks