From: jszhang@marvell.com (Jisheng Zhang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
Date: Thu, 12 Jun 2014 18:19:19 +0800 [thread overview]
Message-ID: <20140612181919.038012f5@xhacker> (raw)
In-Reply-To: <20140612181503.06562a38@xhacker>
Hi Russell,
On Thu, 12 Jun 2014 03:15:03 -0700
Jisheng Zhang <jszhang@marvell.com> wrote:
> Hi Russell,
>
> On Thu, 12 Jun 2014 02:44:23 -0700
> Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
>
> > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > > For all BG2Q SoCs, 2 cycles is the best/correct value
> >
> > It would be a good idea to set all these parameters if you need to set
> > them at all - in other words, setting arm,dirty-latency as well, as
> > that's all part of the timing specification.
> >
>
> Thanks for reviewing this patch. I will check with SoC people to find the
> correct dirty-latency value.
The BG2Q L2 cache controller is PL310, so no "dirty-latency"
Thanks,
Jisheng
next prev parent reply other threads:[~2014-06-12 10:19 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-12 9:38 [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles Jisheng Zhang
2014-06-12 9:44 ` Russell King - ARM Linux
2014-06-12 10:15 ` Jisheng Zhang
2014-06-12 10:19 ` Jisheng Zhang [this message]
2014-06-16 11:24 ` Sebastian Hesselbarth
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