iMX6Q FEC: transmit queue 0 timed out

[shawn.guo@freescale.com (Shawn Guo)]

On Wed, Jul 16, 2014 at 10:41:10AM +0200, Holger Schurig wrote:
> Andy,
> 
> to revive an old thread: I now got ethernet working. Basically, I
> needed to set the system so that the PHY is generating the ref-clock.
> I found even code in arch/arm/mach-imx/mach-imx6q.c that controls
> setting of GPR1[21] from the device tree. However, I wasn't really
> able to come up with a device-tree that triggers the code
> IMX6Q_GPR1_ENET_CLK_SEL_PAD. For example, Neither
> Documentation/devicetree/bindings/net/fsl-fec.txt nor any other file
> there mention anything on how to do this.
> 
> Currently I disable the 3rd clock. I changed the default
>          clocks = <&clks 117>, <&clks 117>, <&clks 190>;
>          clock-names = "ipg", "ahb", "ptp";
> (from imx6qdl.dtsi) to my dts:
>          clocks = <&clks 117>, <&clks 117>;
>          clock-names = "ipg", "ahb";
> 
> Would I have needed to create some dummy clock, e.g. "ext-phy-clk" and
> specified that as a third clock in my dts?

Since in your setup PHY is generating the reference clock, you need to
define this clock in your board dts, and overwrite the 'ptp' clock with
it, something like the following.

clocks {
	#address-cells = <1>;
	#size-cells = <0>;

	rmii_clk: clock at 0 {
		compatible = "fixed-clock";
		reg = <0>;
		#clock-cells = <0>;
		clock-frequency = <25000000>;  /* 25MHz for example */
		clock-output-names = "rmii_ref_clk";
	};
};

&fec {
        clocks = <&clks 117>, <&clks 117>, <&rmii_clk>;
};