[PATCHv2 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code

[mark.rutland@arm.com (Mark Rutland)]

Hi Dinh,

On Thu, Aug 14, 2014 at 10:13:34PM +0100, dinguyen at opensource.altera.com wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to
> bring secondary cores online. This patch adds a /memreserve/ section to
> reserve the first 4K for the SMP trampoline code.

I'm slightly confused. 

Sorry to split hairs here, but I think the comment is subtly wrong.

The trampoline code seems to be placed in this location by Linux, so
it's not that we're protecting the trampoline code, but rather we're
preserving the location for future use.

I take it that the reset address isn't configurable?

Thanks,
Mark.

> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> Acked-by: Pavel Machek <pavel@denx.de>
> ---
> v2: Add a comment in the dts files
> ---
>  arch/arm/boot/dts/socfpga_arria5.dtsi   | 2 ++
>  arch/arm/boot/dts/socfpga_cyclone5.dtsi | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
> index 468fc4c..03e8268 100644
> --- a/arch/arm/boot/dts/socfpga_arria5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
> @@ -15,6 +15,8 @@
>   */
>  
>  /dts-v1/;
> +/* First 4KB has trampoline code for secondary cores. */
> +/memreserve/ 0x00000000 0x0001000;
>  #include "socfpga.dtsi"
>  
>  / {
> diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> index 33cad8b..28c05e7 100644
> --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
> @@ -16,6 +16,8 @@
>   */
>  
>  /dts-v1/;
> +/* First 4KB has trampoline code for secondary cores. */
> +/memreserve/ 0x00000000 0x0001000;
>  #include "socfpga.dtsi"
>  
>  / {
> -- 
> 2.0.3
> 
>