* [PATCH V1 1/2] ARM: clk-imx6q: refine clock tree for ASRC @ 2014-09-04 9:48 Shengjiu Wang 2014-09-04 9:48 ` [PATCH V1 2/2] ARM: clk-imx6q: refine clock tree for SSI Shengjiu Wang 2014-09-05 0:43 ` [PATCH V1 1/2] ARM: clk-imx6q: refine clock tree for ASRC Shawn Guo 0 siblings, 2 replies; 3+ messages in thread From: Shengjiu Wang @ 2014-09-04 9:48 UTC (permalink / raw) To: linux-arm-kernel ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> --- arch/arm/mach-imx/clk-imx6q.c | 5 ++++- include/dt-bindings/clock/imx6qdl-clock.h | 4 +++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 2edcebf..d5bf1e2 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -107,6 +107,7 @@ static struct clk_div_table video_div_table[] = { }; static unsigned int share_count_esai; +static unsigned int share_count_asrc; static void __init imx6q_clocks_init(struct device_node *ccm_node) { @@ -317,7 +318,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* name parent_name reg shift */ clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); - clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); + clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); + clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); + clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 323e865..1e99613 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -220,6 +220,8 @@ #define IMX6QDL_CLK_LVDS2_GATE 207 #define IMX6QDL_CLK_ESAI_IPG 208 #define IMX6QDL_CLK_ESAI_MEM 209 -#define IMX6QDL_CLK_END 210 +#define IMX6QDL_CLK_ASRC_IPG 210 +#define IMX6QDL_CLK_ASRC_MEM 211 +#define IMX6QDL_CLK_END 212 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH V1 2/2] ARM: clk-imx6q: refine clock tree for SSI 2014-09-04 9:48 [PATCH V1 1/2] ARM: clk-imx6q: refine clock tree for ASRC Shengjiu Wang @ 2014-09-04 9:48 ` Shengjiu Wang 2014-09-05 0:43 ` [PATCH V1 1/2] ARM: clk-imx6q: refine clock tree for ASRC Shawn Guo 1 sibling, 0 replies; 3+ messages in thread From: Shengjiu Wang @ 2014-09-04 9:48 UTC (permalink / raw) To: linux-arm-kernel Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> --- arch/arm/mach-imx/clk-imx6q.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index d5bf1e2..013d3cd 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -108,6 +108,9 @@ static struct clk_div_table video_div_table[] = { static unsigned int share_count_esai; static unsigned int share_count_asrc; +static unsigned int share_count_ssi1; +static unsigned int share_count_ssi2; +static unsigned int share_count_ssi3; static void __init imx6q_clocks_init(struct device_node *ccm_node) { @@ -392,9 +395,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); - clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); - clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); - clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); + clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); + clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); + clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); + clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); + clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); + clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH V1 1/2] ARM: clk-imx6q: refine clock tree for ASRC 2014-09-04 9:48 [PATCH V1 1/2] ARM: clk-imx6q: refine clock tree for ASRC Shengjiu Wang 2014-09-04 9:48 ` [PATCH V1 2/2] ARM: clk-imx6q: refine clock tree for SSI Shengjiu Wang @ 2014-09-05 0:43 ` Shawn Guo 1 sibling, 0 replies; 3+ messages in thread From: Shawn Guo @ 2014-09-05 0:43 UTC (permalink / raw) To: linux-arm-kernel On Thu, Sep 04, 2014 at 05:48:58PM +0800, Shengjiu Wang wrote: > ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share > the same gate bits. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Applied both, thanks. ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2014-09-05 0:43 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-09-04 9:48 [PATCH V1 1/2] ARM: clk-imx6q: refine clock tree for ASRC Shengjiu Wang 2014-09-04 9:48 ` [PATCH V1 2/2] ARM: clk-imx6q: refine clock tree for SSI Shengjiu Wang 2014-09-05 0:43 ` [PATCH V1 1/2] ARM: clk-imx6q: refine clock tree for ASRC Shawn Guo
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