* [PATCH] ARM: dts: imx6qdl-sabresd: Configure the pins locally
@ 2014-09-05 12:46 Fabio Estevam
2014-09-10 1:30 ` Shawn Guo
2014-09-10 1:52 ` Shawn Guo
0 siblings, 2 replies; 4+ messages in thread
From: Fabio Estevam @ 2014-09-05 12:46 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@freescale.com>
Passing '0x80000000' to the pin configuration means that kernel will skip the
IOMUXC_SW_PAD_CTL configuration and will use whathever values come from the
bootloader.
Instead of relying on the bootloader setup, let's configure it in the kernel to
have predictable settings.
'0x1b0b0' is the default POR value for all these pins and has also been verified
that the pins are using this value by manually inspecting the IOMUXC_SW_PAD_CTL
registers, so no functional change has been made.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 07fb302..baf2f00 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -327,15 +327,15 @@
imx6qdl-sabresd {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
>;
};
@@ -380,9 +380,9 @@
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
>;
};
@@ -409,7 +409,7 @@
pinctrl_pcie: pciegrp {
fsl,pins = <
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
@@ -487,7 +487,7 @@
gpio_leds {
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH] ARM: dts: imx6qdl-sabresd: Configure the pins locally
2014-09-05 12:46 [PATCH] ARM: dts: imx6qdl-sabresd: Configure the pins locally Fabio Estevam
@ 2014-09-10 1:30 ` Shawn Guo
2014-09-10 1:33 ` Fabio Estevam
2014-09-10 1:52 ` Shawn Guo
1 sibling, 1 reply; 4+ messages in thread
From: Shawn Guo @ 2014-09-10 1:30 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Sep 05, 2014 at 09:46:10AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> Passing '0x80000000' to the pin configuration means that kernel will skip the
> IOMUXC_SW_PAD_CTL configuration and will use whathever values come from the
> bootloader.
>
> Instead of relying on the bootloader setup, let's configure it in the kernel to
> have predictable settings.
>
> '0x1b0b0' is the default POR value for all these pins and has also been verified
> that the pins are using this value by manually inspecting the IOMUXC_SW_PAD_CTL
> registers, so no functional change has been made.
Just to ensure I get it right, you verified the setting for all those
pins by inspecting a running kernel, right?
Shawn
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 26 +++++++++++++-------------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
> index 07fb302..baf2f00 100644
> --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
> @@ -327,15 +327,15 @@
> imx6qdl-sabresd {
> pinctrl_hog: hoggrp {
> fsl,pins = <
> - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
> - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
> - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
> - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
> MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
> - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
> - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
> - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
> - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
> + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
> + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
> >;
> };
>
> @@ -380,9 +380,9 @@
>
> pinctrl_gpio_keys: gpio_keysgrp {
> fsl,pins = <
> - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
> - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
> - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
> + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
> >;
> };
>
> @@ -409,7 +409,7 @@
>
> pinctrl_pcie: pciegrp {
> fsl,pins = <
> - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
> >;
> };
>
> @@ -487,7 +487,7 @@
> gpio_leds {
> pinctrl_gpio_leds: gpioledsgrp {
> fsl,pins = <
> - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
> >;
> };
> };
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH] ARM: dts: imx6qdl-sabresd: Configure the pins locally
2014-09-05 12:46 [PATCH] ARM: dts: imx6qdl-sabresd: Configure the pins locally Fabio Estevam
2014-09-10 1:30 ` Shawn Guo
@ 2014-09-10 1:52 ` Shawn Guo
1 sibling, 0 replies; 4+ messages in thread
From: Shawn Guo @ 2014-09-10 1:52 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Sep 05, 2014 at 09:46:10AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> Passing '0x80000000' to the pin configuration means that kernel will skip the
> IOMUXC_SW_PAD_CTL configuration and will use whathever values come from the
> bootloader.
>
> Instead of relying on the bootloader setup, let's configure it in the kernel to
> have predictable settings.
>
> '0x1b0b0' is the default POR value for all these pins and has also been verified
> that the pins are using this value by manually inspecting the IOMUXC_SW_PAD_CTL
> registers, so no functional change has been made.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2014-09-05 12:46 [PATCH] ARM: dts: imx6qdl-sabresd: Configure the pins locally Fabio Estevam
2014-09-10 1:30 ` Shawn Guo
2014-09-10 1:33 ` Fabio Estevam
2014-09-10 1:52 ` Shawn Guo
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