* [PATCHv2 1/8] irqchip: atmel-aic5: Add sama5d4 support
2014-09-12 15:42 [PATCHv2 0/8] Initial support for the Atmel SMART sama5d4 Alexandre Belloni
@ 2014-09-12 15:43 ` Alexandre Belloni
2014-09-14 6:37 ` Jason Cooper
2014-09-12 15:43 ` [PATCHv2 2/8] clk: at91: add a driver for the h32mx clock Alexandre Belloni
` (6 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 15:43 UTC (permalink / raw)
To: linux-arm-kernel
Add sama5d4 support to irq-atmel-aic5.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Cc: Jason Cooper <jason@lakedaemon.net>
.../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +-
drivers/irqchip/irq-atmel-aic5.c | 10 ++++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
index 2742e9cfd6b1..f292917fa00d 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
@@ -2,7 +2,7 @@
Required properties:
- compatible: Should be "atmel,<chip>-aic"
- <chip> can be "at91rm9200" or "sama5d3"
+ <chip> can be "at91rm9200", "sama5d3" or "sama5d4"
- interrupt-controller: Identifies the node as an interrupt controller.
- interrupt-parent: For single AIC system, it is an empty property.
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index dc7d98607a89..a11aae8fb006 100644
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -295,6 +295,7 @@ static void __init sama5d3_aic_irq_fixup(struct device_node *root)
static const struct of_device_id __initdata aic5_irq_fixups[] = {
{ .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
+ { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup },
{ /* sentinel */ },
};
@@ -349,3 +350,12 @@ static int __init sama5d3_aic5_of_init(struct device_node *node,
return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
}
IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);
+
+#define NR_SAMA5D4_IRQS 68
+
+static int __init sama5d4_aic5_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return aic5_of_init(node, parent, NR_SAMA5D4_IRQS);
+}
+IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCHv2 2/8] clk: at91: add a driver for the h32mx clock
2014-09-12 15:42 [PATCHv2 0/8] Initial support for the Atmel SMART sama5d4 Alexandre Belloni
2014-09-12 15:43 ` [PATCHv2 1/8] irqchip: atmel-aic5: Add sama5d4 support Alexandre Belloni
@ 2014-09-12 15:43 ` Alexandre Belloni
2014-09-15 9:14 ` Nicolas Ferre
2014-09-12 15:43 ` [PATCHv2 3/8] ARM: at91: introduce basic SAMA5D4 support Alexandre Belloni
` (5 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 15:43 UTC (permalink / raw)
To: linux-arm-kernel
Newer SoCs have two different peripheral master clocks, h32mx is able to divide
mck for slower peripherals.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Cc: Mike Turquette <mturquette@linaro.org>
.../devicetree/bindings/clock/at91-clock.txt | 15 +++
arch/arm/mach-at91/Kconfig | 3 +
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-h32mx.c | 121 +++++++++++++++++++++
drivers/clk/at91/pmc.c | 6 +
drivers/clk/at91/pmc.h | 5 +
include/linux/clk/at91_pmc.h | 1 +
7 files changed, 152 insertions(+)
create mode 100644 drivers/clk/at91/clk-h32mx.c
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index b3d544ca522a..c8dcbbd242e5 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -74,6 +74,9 @@ Required properties:
"atmel,at91sam9x5-clk-utmi":
at91 utmi clock
+ "atmel,sama5d4-clk-h32mx":
+ at91 h32mx clock
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
@@ -447,3 +450,15 @@ For example:
#clock-cells = <0>;
clocks = <&main>;
};
+
+Required properties for h32mx clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the master clock source phandle.
+
+For example:
+ h32ck: h32mxck {
+ #clock-cells = <0>;
+ compatible = "atmel,sama5d4-clk-h32mx";
+ clocks = <&mck>;
+ };
+
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6eb3c658761d..a2c8ecb10730 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -39,6 +39,9 @@ config AT91_SAM9_TIME
config HAVE_AT91_SMD
bool
+config HAVE_AT91_H64MX
+ bool
+
config SOC_AT91SAM9
bool
select AT91_SAM9_TIME
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 4998aee59267..b2d43ff8112b 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -9,3 +9,4 @@ obj-y += clk-system.o clk-peripheral.o clk-programmable.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
+obj-$(CONFIG_HAVE_AT91_H64MX) += clk-h32mx.o
diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
new file mode 100644
index 000000000000..21a2f3630a43
--- /dev/null
+++ b/drivers/clk/at91/clk-h32mx.c
@@ -0,0 +1,121 @@
+/*
+ * drivers/clk/at91/clk-h32mx.c
+ *
+ * Copyright (C) 2014 Atmel
+ *
+ * Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91_pmc.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+
+#include "pmc.h"
+
+struct clk_sama5d4_h32mx {
+ struct clk_hw hw;
+ struct at91_pmc *pmc;
+};
+
+#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
+
+static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
+
+ if (pmc_read(h32mxclk->pmc, AT91_PMC_MCKR) & AT91_PMC_H32MXDIV)
+ return parent_rate / 2;
+
+ if (parent_rate > 90000000)
+ pr_warn("H32 clock is too fast\n");
+ return parent_rate;
+}
+
+static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+
+ if (rate > *parent_rate)
+ return *parent_rate;
+ div = *parent_rate / 2;
+ if (rate < div)
+ return div;
+
+ if (rate - div < *parent_rate - rate)
+ return div;
+
+ return *parent_rate;
+}
+
+static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
+ struct at91_pmc *pmc = h32mxclk->pmc;
+ u32 tmp;
+
+ if (parent_rate != rate && (parent_rate / 2) != rate)
+ return -EINVAL;
+
+ pmc_lock(pmc);
+ tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_H32MXDIV;
+ if ((parent_rate / 2) == rate)
+ tmp |= AT91_PMC_H32MXDIV;
+ pmc_write(pmc, AT91_PMC_MCKR, tmp);
+ pmc_unlock(pmc);
+
+ return 0;
+}
+
+static const struct clk_ops h32mx_ops = {
+ .recalc_rate = clk_sama5d4_h32mx_recalc_rate,
+ .round_rate = clk_sama5d4_h32mx_round_rate,
+ .set_rate = clk_sama5d4_h32mx_set_rate,
+};
+
+void __init of_sama5d4_clk_h32mx_setup(struct device_node *np,
+ struct at91_pmc *pmc)
+{
+ struct clk_sama5d4_h32mx *h32mxclk;
+ struct clk_init_data init;
+ const char *parent_name;
+ struct clk *clk;
+
+ h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
+ if (!h32mxclk)
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ init.name = np->name;
+ init.ops = &h32mx_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ h32mxclk->hw.init = &init;
+ h32mxclk->pmc = pmc;
+
+ clk = clk_register(NULL, &h32mxclk->hw);
+ if (!clk)
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 524196bb35a5..0d98b3f2b780 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -337,6 +337,12 @@ static const struct of_device_id pmc_clk_ids[] __initconst = {
.data = of_at91sam9x5_clk_smd_setup,
},
#endif
+#if defined(CONFIG_HAVE_AT91_H64MX)
+ {
+ .compatible = "atmel,sama5d4-clk-h32mx",
+ .data = of_sama5d4_clk_h32mx_setup,
+ },
+#endif
{ /*sentinel*/ }
};
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 6c7625976113..52d2041fa3f6 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -120,4 +120,9 @@ extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
struct at91_pmc *pmc);
#endif
+#if defined(CONFIG_HAVE_AT91_SMD)
+extern void __init of_sama5d4_clk_h32mx_setup(struct device_node *np,
+ struct at91_pmc *pmc);
+#endif
+
#endif /* __PMC_H_ */
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index de4268d4987a..c8e3b3d1eded 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -125,6 +125,7 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
#define AT91_PMC_PLLADIV2_ON (1 << 12)
+#define AT91_PMC_H32MXDIV BIT(24)
#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCHv2 2/8] clk: at91: add a driver for the h32mx clock
2014-09-12 15:43 ` [PATCHv2 2/8] clk: at91: add a driver for the h32mx clock Alexandre Belloni
@ 2014-09-15 9:14 ` Nicolas Ferre
0 siblings, 0 replies; 15+ messages in thread
From: Nicolas Ferre @ 2014-09-15 9:14 UTC (permalink / raw)
To: linux-arm-kernel
On 12/09/2014 17:43, Alexandre Belloni :
> Newer SoCs have two different peripheral master clocks, h32mx is able to divide
Well, it is not the h32mx that allows it, it is the clock associated
with it.
> mck for slower peripherals.
Maybe say at the beginning that h32mx stands for "AHB 32 bits Matrix
interconnect" and that we are talking about the particular clock that is
associated with it. This particular clock can be setup at the half of
the H64mx clock which is the mck.
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Cc: Mike Turquette <mturquette@linaro.org>
> .../devicetree/bindings/clock/at91-clock.txt | 15 +++
> arch/arm/mach-at91/Kconfig | 3 +
> drivers/clk/at91/Makefile | 1 +
> drivers/clk/at91/clk-h32mx.c | 121 +++++++++++++++++++++
> drivers/clk/at91/pmc.c | 6 +
> drivers/clk/at91/pmc.h | 5 +
> include/linux/clk/at91_pmc.h | 1 +
> 7 files changed, 152 insertions(+)
> create mode 100644 drivers/clk/at91/clk-h32mx.c
>
> diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
> index b3d544ca522a..c8dcbbd242e5 100644
> --- a/Documentation/devicetree/bindings/clock/at91-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
> @@ -74,6 +74,9 @@ Required properties:
> "atmel,at91sam9x5-clk-utmi":
> at91 utmi clock
>
> + "atmel,sama5d4-clk-h32mx":
> + at91 h32mx clock
> +
> Required properties for SCKC node:
> - reg : defines the IO memory reserved for the SCKC.
> - #size-cells : shall be 0 (reg is used to encode clk id).
> @@ -447,3 +450,15 @@ For example:
> #clock-cells = <0>;
> clocks = <&main>;
> };
> +
> +Required properties for h32mx clock:
for the 32 bits bus Matrix clock (h32mx clock):
> +- #clock-cells : from common clock binding; shall be set to 0.
> +- clocks : shall be the master clock source phandle.
> +
> +For example:
> + h32ck: h32mxck {
> + #clock-cells = <0>;
> + compatible = "atmel,sama5d4-clk-h32mx";
> + clocks = <&mck>;
> + };
> +
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 6eb3c658761d..a2c8ecb10730 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -39,6 +39,9 @@ config AT91_SAM9_TIME
> config HAVE_AT91_SMD
> bool
>
> +config HAVE_AT91_H64MX
HAVE_AT91_H32MX
> + bool
> +
> config SOC_AT91SAM9
> bool
> select AT91_SAM9_TIME
> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
> index 4998aee59267..b2d43ff8112b 100644
> --- a/drivers/clk/at91/Makefile
> +++ b/drivers/clk/at91/Makefile
> @@ -9,3 +9,4 @@ obj-y += clk-system.o clk-peripheral.o clk-programmable.o
> obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
> obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
> obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
> +obj-$(CONFIG_HAVE_AT91_H64MX) += clk-h32mx.o
Ditto.
> diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
> new file mode 100644
> index 000000000000..21a2f3630a43
> --- /dev/null
> +++ b/drivers/clk/at91/clk-h32mx.c
> @@ -0,0 +1,121 @@
> +/*
> + * drivers/clk/at91/clk-h32mx.c
Not the whole path, please.
> + *
> + * Copyright (C) 2014 Atmel
> + *
> + * Alexandre Belloni <alexandre.belloni@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/at91_pmc.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/sched.h>
> +#include <linux/wait.h>
> +
> +#include "pmc.h"
> +
> +struct clk_sama5d4_h32mx {
> + struct clk_hw hw;
> + struct at91_pmc *pmc;
> +};
> +
> +#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
> +
> +static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
> +
> + if (pmc_read(h32mxclk->pmc, AT91_PMC_MCKR) & AT91_PMC_H32MXDIV)
> + return parent_rate / 2;
> +
> + if (parent_rate > 90000000)
A #define here?
> + pr_warn("H32 clock is too fast\n");
H32MX
> + return parent_rate;
> +}
> +
> +static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *parent_rate)
> +{
> + unsigned long div;
> +
> + if (rate > *parent_rate)
> + return *parent_rate;
> + div = *parent_rate / 2;
> + if (rate < div)
> + return div;
> +
> + if (rate - div < *parent_rate - rate)
> + return div;
> +
> + return *parent_rate;
> +}
> +
> +static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
> + struct at91_pmc *pmc = h32mxclk->pmc;
> + u32 tmp;
> +
> + if (parent_rate != rate && (parent_rate / 2) != rate)
> + return -EINVAL;
> +
> + pmc_lock(pmc);
> + tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_H32MXDIV;
> + if ((parent_rate / 2) == rate)
> + tmp |= AT91_PMC_H32MXDIV;
> + pmc_write(pmc, AT91_PMC_MCKR, tmp);
> + pmc_unlock(pmc);
> +
> + return 0;
> +}
> +
> +static const struct clk_ops h32mx_ops = {
> + .recalc_rate = clk_sama5d4_h32mx_recalc_rate,
> + .round_rate = clk_sama5d4_h32mx_round_rate,
> + .set_rate = clk_sama5d4_h32mx_set_rate,
> +};
> +
> +void __init of_sama5d4_clk_h32mx_setup(struct device_node *np,
> + struct at91_pmc *pmc)
> +{
> + struct clk_sama5d4_h32mx *h32mxclk;
> + struct clk_init_data init;
> + const char *parent_name;
> + struct clk *clk;
> +
> + h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
> + if (!h32mxclk)
> + return;
> +
> + parent_name = of_clk_get_parent_name(np, 0);
> +
> + init.name = np->name;
> + init.ops = &h32mx_ops;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.num_parents = parent_name ? 1 : 0;
> + init.flags = CLK_SET_RATE_GATE;
> +
> + h32mxclk->hw.init = &init;
> + h32mxclk->pmc = pmc;
> +
> + clk = clk_register(NULL, &h32mxclk->hw);
> + if (!clk)
> + return;
> +
> + of_clk_add_provider(np, of_clk_src_simple_get, clk);
> +}
> diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
> index 524196bb35a5..0d98b3f2b780 100644
> --- a/drivers/clk/at91/pmc.c
> +++ b/drivers/clk/at91/pmc.c
> @@ -337,6 +337,12 @@ static const struct of_device_id pmc_clk_ids[] __initconst = {
> .data = of_at91sam9x5_clk_smd_setup,
> },
> #endif
> +#if defined(CONFIG_HAVE_AT91_H64MX)
> + {
> + .compatible = "atmel,sama5d4-clk-h32mx",
> + .data = of_sama5d4_clk_h32mx_setup,
> + },
> +#endif
> { /*sentinel*/ }
> };
>
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 6c7625976113..52d2041fa3f6 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -120,4 +120,9 @@ extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
> struct at91_pmc *pmc);
> #endif
>
> +#if defined(CONFIG_HAVE_AT91_SMD)
> +extern void __init of_sama5d4_clk_h32mx_setup(struct device_node *np,
> + struct at91_pmc *pmc);
> +#endif
> +
> #endif /* __PMC_H_ */
> diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
> index de4268d4987a..c8e3b3d1eded 100644
> --- a/include/linux/clk/at91_pmc.h
> +++ b/include/linux/clk/at91_pmc.h
> @@ -125,6 +125,7 @@ extern void __iomem *at91_pmc_base;
> #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
> #define AT91_PMC_PLLADIV2_OFF (0 << 12)
> #define AT91_PMC_PLLADIV2_ON (1 << 12)
> +#define AT91_PMC_H32MXDIV BIT(24)
>
> #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
> #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
>
Best regards,
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCHv2 3/8] ARM: at91: introduce basic SAMA5D4 support
2014-09-12 15:42 [PATCHv2 0/8] Initial support for the Atmel SMART sama5d4 Alexandre Belloni
2014-09-12 15:43 ` [PATCHv2 1/8] irqchip: atmel-aic5: Add sama5d4 support Alexandre Belloni
2014-09-12 15:43 ` [PATCHv2 2/8] clk: at91: add a driver for the h32mx clock Alexandre Belloni
@ 2014-09-12 15:43 ` Alexandre Belloni
2014-09-12 15:43 ` [PATCHv2 4/8] ARM: at91: SAMA5D4 SoC detection code and low level routines Alexandre Belloni
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 15:43 UTC (permalink / raw)
To: linux-arm-kernel
From: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/Kconfig.debug | 4 ++++
arch/arm/mach-at91/Kconfig | 18 ++++++++++++++++
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/include/mach/cpu.h | 9 ++++++++
arch/arm/mach-at91/include/mach/sama5d4.h | 33 ++++++++++++++++++++++++++++
arch/arm/mach-at91/sama5d4.c | 36 +++++++++++++++++++++++++++++++
arch/arm/mach-at91/soc.h | 5 +++++
7 files changed, 106 insertions(+)
create mode 100644 arch/arm/mach-at91/include/mach/sama5d4.h
create mode 100644 arch/arm/mach-at91/sama5d4.c
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b11ad54f8d17..7b44db208f10 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -101,6 +101,10 @@ choice
bool "Kernel low-level debugging on 9263 and 9g45"
depends on HAVE_AT91_DBGU1
+ config AT91_DEBUG_LL_DBGU2
+ bool "Kernel low-level debugging on sama5d4"
+ depends on HAVE_AT91_DBGU2
+
config DEBUG_BCM2835
bool "Kernel low-level debugging on BCM2835 PL011 UART"
depends on ARCH_BCM2835
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a2c8ecb10730..0e11013fea76 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -12,6 +12,9 @@ config HAVE_AT91_DBGU0
config HAVE_AT91_DBGU1
bool
+config HAVE_AT91_DBGU2
+ bool
+
config AT91_USE_OLD_CLK
bool
@@ -104,6 +107,21 @@ config SOC_SAMA5D3
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
+
+config SOC_SAMA5D4
+ bool "SAMA5D4 family"
+ select SOC_SAMA5
+ select HAVE_AT91_DBGU2
+ select CLKSRC_MMIO
+ select CACHE_L2X0
+ select CACHE_PL310
+ select HAVE_FB_ATMEL
+ select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
+ select HAVE_AT91_USB_CLK
+ select HAVE_AT91_H64MX
+ help
+ Select this if you are using one of Atmel's SAMA5D4 family SoC.
endif
if SOC_SAM_V4_V5
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 306c82b3d45c..82edd532c139 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
+obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 86c71debab5b..d77572e8cb15 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -86,6 +86,9 @@ enum at91_soc_type {
/* SAMA5D3 */
AT91_SOC_SAMA5D3,
+ /* SAMA5D4 */
+ AT91_SOC_SAMA5D4,
+
/* Unknown type */
AT91_SOC_UNKNOWN,
};
@@ -211,6 +214,12 @@ static inline int at91_soc_is_detected(void)
#define cpu_is_sama5d3() (0)
#endif
+#ifdef CONFIG_SOC_SAMA5D4
+#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
+#else
+#define cpu_is_sama5d4() (0)
+#endif
+
/*
* Since this is ARM, we will never run on any AVR32 CPU. But these
* definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
new file mode 100644
index 000000000000..f256a45d9854
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -0,0 +1,33 @@
+/*
+ * Chip-specific header file for the SAMA5D4 family
+ *
+ * Copyright (C) 2013 Atmel Corporation,
+ * Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Common definitions.
+ * Based on SAMA5D4 datasheet.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef SAMA5D4_H
+#define SAMA5D4_H
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */
+#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */
+#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */
+#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
+
+/* Some other peripherals */
+#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD
+
+/*
+ * Internal Memory.
+ */
+#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */
+#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */
+
+#endif
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
new file mode 100644
index 000000000000..f81f11ed8deb
--- /dev/null
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -0,0 +1,36 @@
+/*
+ * Chip-specific setup code for the SAMA5D4 family
+ *
+ * Copyright (C) 2013 Atmel Corporation,
+ * Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk/at91_pmc.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/sama5d4.h>
+#include <mach/cpu.h>
+#include <mach/hardware.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ * Processor initialization
+ * -------------------------------------------------------------------- */
+
+static void __init sama5d4_map_io(void)
+{
+ at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
+}
+
+AT91_SOC_START(sama5d4)
+ .map_io = sama5d4_map_io,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index ab983f2cc7dd..85ecd8ad9c53 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -25,6 +25,7 @@ extern struct at91_init_soc at91sam9rl_soc;
extern struct at91_init_soc at91sam9x5_soc;
extern struct at91_init_soc at91sam9n12_soc;
extern struct at91_init_soc sama5d3_soc;
+extern struct at91_init_soc sama5d4_soc;
#define AT91_SOC_START(_name) \
struct at91_init_soc __initdata _name##_soc \
@@ -75,3 +76,7 @@ static inline int at91_soc_is_enabled(void)
#if !defined(CONFIG_SOC_SAMA5D3)
#define sama5d3_soc at91_boot_soc
#endif
+
+#if !defined(CONFIG_SOC_SAMA5D4)
+#define sama5d4_soc at91_boot_soc
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCHv2 4/8] ARM: at91: SAMA5D4 SoC detection code and low level routines
2014-09-12 15:42 [PATCHv2 0/8] Initial support for the Atmel SMART sama5d4 Alexandre Belloni
` (2 preceding siblings ...)
2014-09-12 15:43 ` [PATCHv2 3/8] ARM: at91: introduce basic SAMA5D4 support Alexandre Belloni
@ 2014-09-12 15:43 ` Alexandre Belloni
2014-09-12 15:43 ` [PATCHv2 5/8] ARM: at91: dt: add device tree file for SAMA5D4 SoC Alexandre Belloni
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 15:43 UTC (permalink / raw)
To: linux-arm-kernel
From: Nicolas Ferre <nicolas.ferre@atmel.com>
SoC identification code, kernel uncompress and low level
debugging routines update.
On SAMA5D4, DBGU is at another address AT91_BASE_DBGU2 so another
round of detection is needed. We also had to differentiate with
SAMA5D3 SoC family and rename some variables.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/board-dt-sama5.c | 17 ++++-
arch/arm/mach-at91/generic.h | 1 +
arch/arm/mach-at91/include/mach/cpu.h | 13 +++-
arch/arm/mach-at91/include/mach/debug-macro.S | 5 +-
arch/arm/mach-at91/include/mach/hardware.h | 19 +++++-
arch/arm/mach-at91/include/mach/uncompress.h | 21 ++++--
arch/arm/mach-at91/sama5d4.c | 28 ++++++++
arch/arm/mach-at91/setup.c | 97 +++++++++++++++++++++++++--
8 files changed, 189 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 8c5814fa5325..548de4ad6937 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -40,7 +40,7 @@ static void __init sama5_dt_device_init(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
-static const char *sama5_dt_board_compat[] __initdata = {
+static const char *sama5_dt_board_compat[] __initconst = {
"atmel,sama5",
NULL
};
@@ -53,3 +53,18 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
.init_machine = sama5_dt_device_init,
.dt_compat = sama5_dt_board_compat,
MACHINE_END
+
+static const char *sama5_alt_dt_board_compat[] __initconst = {
+ "atmel,sama5d4",
+ NULL
+};
+
+DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5 (Device Tree)")
+ /* Maintainer: Atmel */
+ .init_time = sama5_dt_timer_init,
+ .map_io = at91_alt_map_io,
+ .init_early = at91_dt_initialize,
+ .init_machine = sama5_dt_device_init,
+ .dt_compat = sama5_alt_dt_board_compat,
+ .l2c_aux_mask = ~0UL,
+MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index f42b0490ad98..4e0a965cf7c0 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -14,6 +14,7 @@
/* Map io */
extern void __init at91_map_io(void);
+extern void __init at91_alt_map_io(void);
extern void __init at91_init_sram(int bank, unsigned long base,
unsigned int length);
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index d77572e8cb15..b27e9ca65653 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -36,7 +36,7 @@
#define ARCH_ID_AT91M40807 0x14080745
#define ARCH_ID_AT91R40008 0x44000840
-#define ARCH_ID_SAMA5D3 0x8A5C07C0
+#define ARCH_ID_SAMA5 0x8A5C07C0
#define ARCH_EXID_AT91SAM9M11 0x00000001
#define ARCH_EXID_AT91SAM9M10 0x00000002
@@ -49,12 +49,19 @@
#define ARCH_EXID_AT91SAM9G25 0x00000003
#define ARCH_EXID_AT91SAM9X25 0x00000004
+#define ARCH_EXID_SAMA5D3 0x00004300
#define ARCH_EXID_SAMA5D31 0x00444300
#define ARCH_EXID_SAMA5D33 0x00414300
#define ARCH_EXID_SAMA5D34 0x00414301
#define ARCH_EXID_SAMA5D35 0x00584300
#define ARCH_EXID_SAMA5D36 0x00004301
+#define ARCH_EXID_SAMA5D4 0x00000007
+#define ARCH_EXID_SAMA5D41 0x00000001
+#define ARCH_EXID_SAMA5D42 0x00000002
+#define ARCH_EXID_SAMA5D43 0x00000003
+#define ARCH_EXID_SAMA5D44 0x00000004
+
#define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
@@ -111,6 +118,10 @@ enum at91_soc_subtype {
AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
+ /* SAMA5D4 */
+ AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
+ AT91_SOC_SAMA5D44,
+
/* No subtype for this SoC */
AT91_SOC_SUBTYPE_NONE,
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index c6bb9e2d9baa..2103a90f2261 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -16,8 +16,11 @@
#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
#define AT91_DBGU AT91_BASE_DBGU0
-#else
+#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
#define AT91_DBGU AT91_BASE_DBGU1
+#else
+/* On sama5d4, use USART3 as low level serial console */
+#define AT91_DBGU SAMA5D4_BASE_USART3
#endif
.macro addruart, rp, rv, tmp
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 56338245653a..d84776f6b8ac 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -19,8 +19,10 @@
/* DBGU base */
/* rm9200, 9260/9g20, 9261/9g10, 9rl */
#define AT91_BASE_DBGU0 0xfffff200
-/* 9263, 9g45 */
+/* 9263, 9g45, sama5d3 */
#define AT91_BASE_DBGU1 0xffffee00
+/* sama5d4 */
+#define AT91_BASE_DBGU2 0xfc069000
#if defined(CONFIG_ARCH_AT91X40)
#include <mach/at91x40.h>
@@ -34,6 +36,7 @@
#include <mach/at91sam9x5.h>
#include <mach/at91sam9n12.h>
#include <mach/sama5d3.h>
+#include <mach/sama5d4.h>
/*
* On all at91 except rm9200 and x40 have the System Controller starts
@@ -47,6 +50,11 @@
* and map the same memory space
*/
#define AT91_BASE_SYS 0xffffc000
+
+/*
+ * On sama5d4 there is no system controller, we map some needed peripherals
+ */
+#define AT91_ALT_BASE_SYS 0xfc069000
#endif
/*
@@ -69,6 +77,13 @@
*/
#define AT91_IO_PHYS_BASE 0xFFF78000
#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE)
+
+/*
+ * On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000
+ * to 0xFB069000 .. 0xFB06F000. (24Kb)
+ */
+#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
+#define AT91_ALT_IO_VIRT_BASE IOMEM(0xFB069000)
#else
/*
* Identity mapping for the non MMU case.
@@ -81,11 +96,13 @@
/* Convert a physical IO address to virtual IO address */
#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
+#define AT91_ALT_IO_P2V(x) ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE)
/*
* Virtual to Physical Address mapping for IO devices.
*/
#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
+#define AT91_ALT_VA_BASE_SYS AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS)
/* Internal SRAM is mapped below the IO devices */
#define AT91_SRAM_MAX SZ_1M
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 4bb644f8e87c..acb2d890ad7e 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
0,
};
-static const u32 uarts_sama5[] = {
+static const u32 uarts_sama5d3[] = {
AT91_BASE_DBGU1,
SAMA5D3_BASE_USART0,
SAMA5D3_BASE_USART1,
@@ -103,6 +103,12 @@ static const u32 uarts_sama5[] = {
0,
};
+static const u32 uarts_sama5d4[] = {
+ AT91_BASE_DBGU2,
+ SAMA5D4_BASE_USART3,
+ 0,
+};
+
static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
{
u32 cidr, socid;
@@ -134,8 +140,14 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
case ARCH_ID_AT91SAM9X5:
return uarts_sam9x5;
- case ARCH_ID_SAMA5D3:
- return uarts_sama5;
+ case ARCH_ID_SAMA5:
+ cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
+ if (cidr & ARCH_EXID_SAMA5D3)
+ return uarts_sama5d3;
+ else if (cidr & ARCH_EXID_SAMA5D4)
+ return uarts_sama5d4;
+
+ break;
}
/* at91sam9g10 */
@@ -156,9 +168,10 @@ static inline void arch_decomp_setup(void)
const u32* usarts;
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
-
if (!usarts)
usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
+ if (!usarts)
+ usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
if (!usarts) {
at91_uart = NULL;
return;
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
index f81f11ed8deb..7638509639f4 100644
--- a/arch/arm/mach-at91/sama5d4.c
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -25,9 +25,37 @@
/* --------------------------------------------------------------------
* Processor initialization
* -------------------------------------------------------------------- */
+static struct map_desc at91_io_desc[] __initdata = {
+ {
+ .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
+ .pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
+ .length = SZ_512,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
+ .pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
+ .length = SZ_512,
+ .type = MT_DEVICE,
+ },
+ { /* On sama5d4, we use USART3 as serial console */
+ .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
+ .pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
+ .length = SZ_256,
+ .type = MT_DEVICE,
+ },
+ { /* A bunch of peripheral with fine grained IO space */
+ .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
+ .pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
+ .length = SZ_2K,
+ .type = MT_DEVICE,
+ },
+};
+
static void __init sama5d4_map_io(void)
{
+ iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
}
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index d2cade21ebd7..25e583b513bf 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -98,6 +98,13 @@ static struct map_desc at91_io_desc __initdata __maybe_unused = {
.type = MT_DEVICE,
};
+static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
+ .virtual = (unsigned long)AT91_ALT_VA_BASE_SYS,
+ .pfn = __phys_to_pfn(AT91_ALT_BASE_SYS),
+ .length = 24 * SZ_1K,
+ .type = MT_DEVICE,
+};
+
static void __init soc_detect(u32 dbgu_base)
{
u32 cidr, socid;
@@ -160,9 +167,12 @@ static void __init soc_detect(u32 dbgu_base)
at91_boot_soc = at91sam9n12_soc;
break;
- case ARCH_ID_SAMA5D3:
- at91_soc_initdata.type = AT91_SOC_SAMA5D3;
- at91_boot_soc = sama5d3_soc;
+ case ARCH_ID_SAMA5:
+ at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+ if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
+ at91_soc_initdata.type = AT91_SOC_SAMA5D3;
+ at91_boot_soc = sama5d3_soc;
+ }
break;
}
@@ -185,7 +195,8 @@ static void __init soc_detect(u32 dbgu_base)
at91_soc_initdata.cidr = cidr;
/* sub version of soc */
- at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+ if (!at91_soc_initdata.exid)
+ at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
switch (at91_soc_initdata.exid) {
@@ -242,6 +253,54 @@ static void __init soc_detect(u32 dbgu_base)
}
}
+static void __init alt_soc_detect(u32 dbgu_base)
+{
+ u32 cidr, socid;
+
+ /* SoC ID */
+ cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
+ socid = cidr & ~AT91_CIDR_VERSION;
+
+ switch (socid) {
+ case ARCH_ID_SAMA5:
+ at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+ if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
+ at91_soc_initdata.type = AT91_SOC_SAMA5D3;
+ at91_boot_soc = sama5d3_soc;
+ } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
+ at91_soc_initdata.type = AT91_SOC_SAMA5D4;
+ at91_boot_soc = sama5d4_soc;
+ }
+ break;
+ }
+
+ if (!at91_soc_is_detected())
+ return;
+
+ at91_soc_initdata.cidr = cidr;
+
+ /* sub version of soc */
+ if (!at91_soc_initdata.exid)
+ at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
+
+ if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
+ switch (at91_soc_initdata.exid) {
+ case ARCH_EXID_SAMA5D41:
+ at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
+ break;
+ case ARCH_EXID_SAMA5D42:
+ at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
+ break;
+ case ARCH_EXID_SAMA5D43:
+ at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
+ break;
+ case ARCH_EXID_SAMA5D44:
+ at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
+ break;
+ }
+ }
+}
+
static const char *soc_name[] = {
[AT91_SOC_RM9200] = "at91rm9200",
[AT91_SOC_SAM9260] = "at91sam9260",
@@ -254,6 +313,7 @@ static const char *soc_name[] = {
[AT91_SOC_SAM9X5] = "at91sam9x5",
[AT91_SOC_SAM9N12] = "at91sam9n12",
[AT91_SOC_SAMA5D3] = "sama5d3",
+ [AT91_SOC_SAMA5D4] = "sama5d4",
[AT91_SOC_UNKNOWN] = "Unknown",
};
@@ -281,6 +341,10 @@ static const char *soc_subtype_name[] = {
[AT91_SOC_SAMA5D34] = "sama5d34",
[AT91_SOC_SAMA5D35] = "sama5d35",
[AT91_SOC_SAMA5D36] = "sama5d36",
+ [AT91_SOC_SAMA5D41] = "sama5d41",
+ [AT91_SOC_SAMA5D42] = "sama5d42",
+ [AT91_SOC_SAMA5D43] = "sama5d43",
+ [AT91_SOC_SAMA5D44] = "sama5d44",
[AT91_SOC_SUBTYPE_NONE] = "None",
[AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
};
@@ -319,6 +383,31 @@ void __init at91_map_io(void)
at91_boot_soc.map_io();
}
+void __init at91_alt_map_io(void)
+{
+ /* Map peripherals */
+ iotable_init(&at91_alt_io_desc, 1);
+
+ at91_soc_initdata.type = AT91_SOC_UNKNOWN;
+ at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
+
+ alt_soc_detect(AT91_BASE_DBGU2);
+ if (!at91_soc_is_detected())
+ panic("AT91: Impossible to detect the SOC type");
+
+ pr_info("AT91: Detected soc type: %s\n",
+ at91_get_soc_type(&at91_soc_initdata));
+ if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
+ pr_info("AT91: Detected soc subtype: %s\n",
+ at91_get_soc_subtype(&at91_soc_initdata));
+
+ if (!at91_soc_is_enabled())
+ panic("AT91: Soc not enabled");
+
+ if (at91_boot_soc.map_io)
+ at91_boot_soc.map_io();
+}
+
void __iomem *at91_matrix_base;
EXPORT_SYMBOL_GPL(at91_matrix_base);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCHv2 5/8] ARM: at91: dt: add device tree file for SAMA5D4 SoC
2014-09-12 15:42 [PATCHv2 0/8] Initial support for the Atmel SMART sama5d4 Alexandre Belloni
` (3 preceding siblings ...)
2014-09-12 15:43 ` [PATCHv2 4/8] ARM: at91: SAMA5D4 SoC detection code and low level routines Alexandre Belloni
@ 2014-09-12 15:43 ` Alexandre Belloni
2014-09-12 15:43 ` [PATCHv2 6/8] ARM: at91: dt: add device tree file for SAMA5D4ek board Alexandre Belloni
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 15:43 UTC (permalink / raw)
To: linux-arm-kernel
From: Nicolas Ferre <nicolas.ferre@atmel.com>
Add SAMA5D4 SoC DT file.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/sama5d4.dtsi | 1233 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 1233 insertions(+)
create mode 100644 arch/arm/boot/dts/sama5d4.dtsi
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
new file mode 100644
index 000000000000..af4177258411
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -0,0 +1,1233 @@
+/*
+ * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
+ *
+ * Copyright (C) 2014 Atmel,
+ * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Atmel SAMA5D4 family SoC";
+ compatible = "atmel,sama5d4";
+ interrupt-parent = <&aic>;
+
+ aliases {
+ serial0 = &usart3;
+ serial1 = &usart4;
+ serial2 = &usart2;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ gpio4 = &pioE;
+ tcb0 = &tcb0;
+ tcb1 = &tcb1;
+ i2c2 = &i2c2;
+ };
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ reg = <0x20000000 0x20000000>;
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ L2: cache-controller at 00a00000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a00000 0x1000>;
+ interrupts = <0 67 4>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ pmc: pmc at f0018000 {
+ compatible = "atmel,sama5d3-pmc";
+ reg = <0xf0018000 0x120>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ main_rc_osc: main_rc_osc {
+ compatible = "atmel,at91sam9x5-clk-main-rc-osc";
+ #clock-cells = <0>;
+ interrupt-parent = <&pmc>;
+ interrupts = <AT91_PMC_MOSCRCS>;
+ clock-frequency = <12000000>;
+ clock-accuracy = <100000000>;
+ };
+
+ main_osc: main_osc {
+ compatible = "atmel,at91rm9200-clk-main-osc";
+ #clock-cells = <0>;
+ interrupt-parent = <&pmc>;
+ interrupts = <AT91_PMC_MOSCS>;
+ clocks = <&main_xtal>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91sam9x5-clk-main";
+ #clock-cells = <0>;
+ interrupt-parent = <&pmc>;
+ interrupts = <AT91_PMC_MOSCSELS>;
+ clocks = <&main_rc_osc &main_osc>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,sama5d3-clk-pll";
+ #clock-cells = <0>;
+ interrupt-parent = <&pmc>;
+ interrupts = <AT91_PMC_LOCKA>;
+ clocks = <&main>;
+ reg = <0>;
+ atmel,clk-input-range = <12000000 12000000>;
+ #atmel,pll-clk-output-range-cells = <4>;
+ atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ interrupt-parent = <&pmc>;
+ interrupts = <AT91_PMC_LOCKU>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ interrupt-parent = <&pmc>;
+ interrupts = <AT91_PMC_MCKRDY>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ atmel,clk-output-range = <125000000 177000000>;
+ atmel,clk-divisors = <1 2 4 3>;
+ };
+
+ h32ck: h32mxck {
+ #clock-cells = <0>;
+ compatible = "atmel,sama5d4-clk-h32mx";
+ clocks = <&mck>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9x5-clk-programmable";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&pmc>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+
+ prog0: prog0 {
+ #clock-cells = <0>;
+ reg = <0>;
+ interrupts = <AT91_PMC_PCKRDY(0)>;
+ };
+
+ prog1: prog1 {
+ #clock-cells = <0>;
+ reg = <1>;
+ interrupts = <AT91_PMC_PCKRDY(1)>;
+ };
+
+ prog2: prog2 {
+ #clock-cells = <0>;
+ reg = <2>;
+ interrupts = <AT91_PMC_PCKRDY(2)>;
+ };
+ };
+
+ smd: smdclk {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ddrck: ddrck {
+ #clock-cells = <0>;
+ reg = <2>;
+ clocks = <&mck>;
+ };
+
+ lcdck: lcdck {
+ #clock-cells = <0>;
+ reg = <4>;
+ clocks = <&smd>;
+ };
+
+ smdck: smdck {
+ #clock-cells = <0>;
+ reg = <4>;
+ clocks = <&smd>;
+ };
+
+ uhpck: uhpck {
+ #clock-cells = <0>;
+ reg = <6>;
+ clocks = <&usb>;
+ };
+
+ udpck: udpck {
+ #clock-cells = <0>;
+ reg = <7>;
+ clocks = <&usb>;
+ };
+
+ pck0: pck0 {
+ #clock-cells = <0>;
+ reg = <8>;
+ clocks = <&prog0>;
+ };
+
+ pck1: pck1 {
+ #clock-cells = <0>;
+ reg = <9>;
+ clocks = <&prog1>;
+ };
+
+ pck2: pck2 {
+ #clock-cells = <0>;
+ reg = <10>;
+ clocks = <&prog2>;
+ };
+ };
+
+ periph32ck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&h32ck>;
+
+ pioD_clk: pioD_clk {
+ #clock-cells = <0>;
+ reg = <5>;
+ };
+
+ usart0_clk: usart0_clk {
+ #clock-cells = <0>;
+ reg = <6>;
+ };
+
+ usart1_clk: usart1_clk {
+ #clock-cells = <0>;
+ reg = <7>;
+ };
+
+ icm_clk: icm_clk {
+ #clock-cells = <0>;
+ reg = <9>;
+ };
+
+ aes_clk: aes_clk {
+ #clock-cells = <0>;
+ reg = <12>;
+ };
+
+ tdes_clk: tdes_clk {
+ #clock-cells = <0>;
+ reg = <14>;
+ };
+
+ sha_clk: sha_clk {
+ #clock-cells = <0>;
+ reg = <15>;
+ };
+
+ matrix1_clk: matrix1_clk {
+ #clock-cells = <0>;
+ reg = <17>;
+ };
+
+ hsmc_clk: hsmc_clk {
+ #clock-cells = <0>;
+ reg = <22>;
+ };
+
+ pioA_clk: pioA_clk {
+ #clock-cells = <0>;
+ reg = <23>;
+ };
+
+ pioB_clk: pioB_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
+
+ pioC_clk: pioC_clk {
+ #clock-cells = <0>;
+ reg = <25>;
+ };
+
+ pioE_clk: pioE_clk {
+ #clock-cells = <0>;
+ reg = <26>;
+ };
+
+ uart0_clk: uart0_clk {
+ #clock-cells = <0>;
+ reg = <27>;
+ };
+
+ uart1_clk: uart1_clk {
+ #clock-cells = <0>;
+ reg = <28>;
+ };
+
+ usart2_clk: usart2_clk {
+ #clock-cells = <0>;
+ reg = <29>;
+ };
+
+ usart3_clk: usart3_clk {
+ #clock-cells = <0>;
+ reg = <30>;
+ };
+
+ usart4_clk: usart4_clk {
+ #clock-cells = <0>;
+ reg = <31>;
+ };
+
+ twi0_clk: twi0_clk {
+ reg = <32>;
+ #clock-cells = <0>;
+ };
+
+ twi1_clk: twi1_clk {
+ #clock-cells = <0>;
+ reg = <33>;
+ };
+
+ twi2_clk: twi2_clk {
+ #clock-cells = <0>;
+ reg = <34>;
+ };
+
+ mci0_clk: mci0_clk {
+ #clock-cells = <0>;
+ reg = <35>;
+ };
+
+ mci1_clk: mci1_clk {
+ #clock-cells = <0>;
+ reg = <36>;
+ };
+
+ spi0_clk: spi0_clk {
+ #clock-cells = <0>;
+ reg = <37>;
+ };
+
+ spi1_clk: spi1_clk {
+ #clock-cells = <0>;
+ reg = <38>;
+ };
+
+ spi2_clk: spi2_clk {
+ #clock-cells = <0>;
+ reg = <39>;
+ };
+
+ tcb0_clk: tcb0_clk {
+ #clock-cells = <0>;
+ reg = <40>;
+ };
+
+ tcb1_clk: tcb1_clk {
+ #clock-cells = <0>;
+ reg = <41>;
+ };
+
+ tcb2_clk: tcb2_clk {
+ #clock-cells = <0>;
+ reg = <42>;
+ };
+
+ pwm_clk: pwm_clk {
+ #clock-cells = <0>;
+ reg = <43>;
+ };
+
+ adc_clk: adc_clk {
+ #clock-cells = <0>;
+ reg = <44>;
+ };
+
+ dbgu_clk: dbgu_clk {
+ #clock-cells = <0>;
+ reg = <45>;
+ };
+
+ uhphs_clk: uhphs_clk {
+ #clock-cells = <0>;
+ reg = <46>;
+ };
+
+ udphs_clk: udphs_clk {
+ #clock-cells = <0>;
+ reg = <47>;
+ };
+
+ ssc0_clk: ssc0_clk {
+ #clock-cells = <0>;
+ reg = <48>;
+ };
+
+ ssc1_clk: ssc1_clk {
+ #clock-cells = <0>;
+ reg = <49>;
+ };
+
+ trng_clk: trng_clk {
+ #clock-cells = <0>;
+ reg = <53>;
+ };
+
+ macb0_clk: macb0_clk {
+ #clock-cells = <0>;
+ reg = <54>;
+ };
+
+ macb1_clk: macb1_clk {
+ #clock-cells = <0>;
+ reg = <55>;
+ };
+
+ fuse_clk: fuse_clk {
+ #clock-cells = <0>;
+ reg = <57>;
+ };
+
+ securam_clk: securam_clk {
+ #clock-cells = <0>;
+ reg = <59>;
+ };
+
+ smd_clk: smd_clk {
+ #clock-cells = <0>;
+ reg = <61>;
+ };
+
+ twi3_clk: twi3_clk {
+ #clock-cells = <0>;
+ reg = <62>;
+ };
+
+ catb_clk: catb_clk {
+ #clock-cells = <0>;
+ reg = <63>;
+ };
+ };
+
+ periph64ck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mck>;
+
+ dma0_clk: dma0_clk {
+ #clock-cells = <0>;
+ reg = <8>;
+ };
+
+ cpkcc_clk: cpkcc_clk {
+ #clock-cells = <0>;
+ reg = <10>;
+ };
+
+ aesb_clk: aesb_clk {
+ #clock-cells = <0>;
+ reg = <13>;
+ };
+
+ mpddr_clk: mpddr_clk {
+ #clock-cells = <0>;
+ reg = <16>;
+ };
+
+ matrix0_clk: matrix0_clk {
+ #clock-cells = <0>;
+ reg = <18>;
+ };
+
+ vdec_clk: vdec_clk {
+ #clock-cells = <0>;
+ reg = <19>;
+ };
+
+ dma1_clk: dma1_clk {
+ #clock-cells = <0>;
+ reg = <50>;
+ };
+
+ lcd_clk: lcd_clk {
+ #clock-cells = <0>;
+ reg = <51>;
+ };
+
+ isi_clk: isi_clk {
+ #clock-cells = <0>;
+ reg = <52>;
+ };
+ };
+ };
+
+ ramc0: ramc at f0010000 {
+ compatible = "atmel,sama5d3-ddramc";
+ reg = <0xf0010000 0x200>;
+ clocks = <&ddrck>, <&mpddr_clk>;
+ clock-names = "ddrck", "mpddr";
+ };
+
+ mmc0: mmc at f8000000 {
+ compatible = "atmel,hsmci";
+ reg = <0xf8000000 0x600>;
+ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci0_clk>;
+ clock-names = "mci_clk";
+ };
+
+ spi0: spi at f8010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xf8010000 0x100>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&spi0_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ i2c0: i2c at f8014000 {
+ compatible = "atmel,at91sam9x5-i2c";
+ reg = <0xf8014000 0x4000>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ status = "disabled";
+ };
+
+ tcb0: timer at f801c000 {
+ compatible = "atmel,at91sam9x5-tcb";
+ reg = <0xf801c000 0x100>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tcb0_clk>;
+ clock-names = "t0_clk";
+ };
+
+ macb0: ethernet at f8020000 {
+ compatible = "atmel,sama5d4-gem";
+ reg = <0xf8020000 0x100>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ clocks = <&macb0_clk>, <&macb0_clk>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+
+ i2c2: i2c at f8024000 {
+ compatible = "atmel,at91sam9x5-i2c";
+ reg = <0xf8024000 0x4000>;
+ interrupts = <34 4 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi2_clk>;
+ status = "disabled";
+ };
+
+ adc0: adc at fc034000 {
+ compatible = "atmel,at91sam9x5-adc";
+ reg = <0xfc034000 0x100>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* external trigger is conflict with USBA_VBUS */
+ &pinctrl_adc0_ad0
+ &pinctrl_adc0_ad1
+ &pinctrl_adc0_ad2
+ &pinctrl_adc0_ad3
+ &pinctrl_adc0_ad4
+ >;
+ clocks = <&adc_clk>,
+ <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
+ atmel,adc-channels-used = <0x01f>;
+ atmel,adc-startup-time = <40>;
+ atmel,adc-use-external;
+ atmel,adc-vref = <3000>;
+ atmel,adc-res = <8 10>;
+ atmel,adc-sample-hold-time = <11>;
+ atmel,adc-res-names = "lowres", "highres";
+ atmel,adc-ts-pressure-threshold = <10000>;
+ status = "disabled";
+
+ trigger at 0 {
+ trigger-name = "external-rising";
+ trigger-value = <0x1>;
+ trigger-external;
+ };
+ trigger at 1 {
+ trigger-name = "external-falling";
+ trigger-value = <0x2>;
+ trigger-external;
+ };
+ trigger at 2 {
+ trigger-name = "external-any";
+ trigger-value = <0x3>;
+ trigger-external;
+ };
+ trigger at 3 {
+ trigger-name = "continuous";
+ trigger-value = <0x6>;
+ };
+ };
+
+ mmc1: mmc at fc000000 {
+ compatible = "atmel,hsmci";
+ reg = <0xfc000000 0x600>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci1_clk>;
+ clock-names = "mci_clk";
+ };
+
+ usart2: serial at fc008000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfc008000 0x100>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
+ clocks = <&usart2_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart3: serial at fc00c000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfc00c000 0x100>;
+ interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&usart3_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart4: serial at fc010000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfc010000 0x100>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart4>;
+ clocks = <&usart4_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ tcb1: timer at fc020000 {
+ compatible = "atmel,at91sam9x5-tcb";
+ reg = <0xfc020000 0x100>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tcb1_clk>;
+ clock-names = "t0_clk";
+ };
+
+ rstc at fc068600 {
+ compatible = "atmel,at91sam9g45-rstc";
+ reg = <0xfc068600 0x10>;
+ };
+
+ shdwc at fc068610 {
+ compatible = "atmel,at91sam9x5-shdwc";
+ reg = <0xfc068610 0x10>;
+ };
+
+ pit: timer at fc068630 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xfc068630 0xf>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&h32ck>;
+ };
+
+ watchdog at fc068640 {
+ compatible = "atmel,at91sam9260-wdt";
+ reg = <0xfc068640 0x10>;
+ status = "disabled";
+ };
+
+ dbgu: serial at fc069000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfc069000 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&dbgu_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+
+ pinctrl at fc06a000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+ ranges = <0xfc06a000 0xfc06a000 0x4000>;
+ /* WARNING: revisit as pin spec has changed */
+ atmel,mux-mask = <
+ /* A B C */
+ 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
+ 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
+ 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
+ 0x00000000 0x00000000 0x00000000 /* pioD */
+ 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
+ >;
+
+ pioA: gpio at fc06a000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc06a000 0x100>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
+
+ pioB: gpio at fc06b000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc06b000 0x100>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
+
+ pioC: gpio at fc06c000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc06c000 0x100>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ };
+
+ pioE: gpio at fc06d000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc06d000 0x100>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioE_clk>;
+ };
+
+ /* pinctrl pin settings */
+ adc0 {
+ pinctrl_adc0_adtrg: adc0_adtrg {
+ atmel,pins =
+ <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
+ };
+ pinctrl_adc0_ad0: adc0_ad0 {
+ atmel,pins =
+ <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad1: adc0_ad1 {
+ atmel,pins =
+ <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad2: adc0_ad2 {
+ atmel,pins =
+ <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad3: adc0_ad3 {
+ atmel,pins =
+ <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad4: adc0_ad4 {
+ atmel,pins =
+ <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
+ <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
+ };
+ };
+
+ i2c0 {
+ pinctrl_i2c0: i2c0-0 {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2: i2c2-0 {
+ atmel,pins =
+ <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
+ AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
+ };
+ };
+
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
+ AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
+ AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
+ >;
+ };
+ };
+
+ mmc0 {
+ pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
+ atmel,pins =
+ <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK */
+ AT91_PIOE 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB */
+ AT91_PIOE 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0 */
+ >;
+ };
+ pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
+ atmel,pins =
+ <AT91_PIOE 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1 */
+ AT91_PIOE 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2 */
+ AT91_PIOE 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3 */
+ >;
+ };
+ };
+
+ mmc1 {
+ pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
+ atmel,pins =
+ <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI0_CK */
+ AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI0_CDA */
+ AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI0_DA0 */
+ >;
+ };
+ pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
+ atmel,pins =
+ <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI0_DA1 */
+ AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI0_DA2 */
+ AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI0_DA3 */
+ >;
+ };
+ };
+
+ nand0 {
+ pinctrl_nand: nand-0 {
+ atmel,pins =
+ <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
+
+ AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
+ AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
+
+ AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
+ AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
+ AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
+ >;
+ };
+ };
+
+ usart2 {
+ pinctrl_usart2: usart2-0 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
+ AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
+ >;
+ };
+ pinctrl_usart2_rts: usart2_rts-0 {
+ atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
+ };
+ pinctrl_usart2_cts: usart2_cts-0 {
+ atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
+ };
+ };
+
+ usart3 {
+ pinctrl_usart3: usart3-0 {
+ atmel,pins =
+ <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
+ AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
+ >;
+ };
+ };
+
+ usart4 {
+ pinctrl_usart4: usart4-0 {
+ atmel,pins =
+ <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
+ AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
+ >;
+ };
+ pinctrl_usart4_rts: usart4_rts-0 {
+ atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
+ };
+ pinctrl_usart4_cts: usart4_cts-0 {
+ atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
+ };
+ };
+ };
+
+ sckc at fc068650 {
+ compatible = "atmel,at91sam9x5-sckc";
+ reg = <0xfc068650 0x4>;
+
+ slow_rc_osc: slow_rc_osc {
+ compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-accuracy = <250000000>;
+ atmel,startup-time-usec = <75>;
+ };
+
+ slow_osc: slow_osc {
+ compatible = "atmel,at91sam9x5-clk-slow-osc";
+ #clock-cells = <0>;
+ clocks = <&slow_xtal>;
+ atmel,startup-time-usec = <1200000>;
+ };
+
+ clk32k: slowck {
+ compatible = "atmel,at91sam9x5-clk-slow";
+ #clock-cells = <0>;
+ clocks = <&slow_rc_osc &slow_osc>;
+ };
+ };
+
+ aic: interrupt-controller at fc06e000 {
+ #interrupt-cells = <3>;
+ compatible = "atmel,sama5d4-aic";
+ interrupt-controller;
+ reg = <0xfc06e000 0x200>;
+ atmel,external-irqs = <56>;
+ };
+ };
+
+ usb0: gadget at 00400000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91sam9rl-udc";
+ reg = <0x00400000 0x100000
+ 0xfc02c000 0x4000>;
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&udphs_clk>, <&utmi>;
+ clock-names = "pclk", "hclk";
+ status = "disabled";
+
+ ep0 {
+ reg = <0>;
+ atmel,fifo-size = <64>;
+ atmel,nb-banks = <1>;
+ };
+
+ ep1 {
+ reg = <1>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <3>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep2 {
+ reg = <2>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <3>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep3 {
+ reg = <3>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep4 {
+ reg = <4>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep5 {
+ reg = <5>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep6 {
+ reg = <6>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-dma;
+ atmel,can-isoc;
+ };
+
+ ep7 {
+ reg = <7>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+
+ ep8 {
+ reg = <8>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+
+ ep9 {
+ reg = <9>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+
+ ep10 {
+ reg = <10>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+
+ ep11 {
+ reg = <11>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+
+ ep12 {
+ reg = <12>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+
+ ep13 {
+ reg = <13>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+
+ ep14 {
+ reg = <14>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+
+ ep15 {
+ reg = <15>;
+ atmel,fifo-size = <1024>;
+ atmel,nb-banks = <2>;
+ atmel,can-isoc;
+ };
+ };
+
+ usb1: ohci at 00500000 {
+ compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+ reg = <0x00500000 0x100000>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
+ <&uhpck>;
+ clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+
+ usb2: ehci at 00600000 {
+ compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+ reg = <0x00600000 0x100000>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
+ clock-names = "usb_clk", "ehci_clk", "uhpck";
+ status = "disabled";
+ };
+
+ nand0: nand at 80000000 {
+ compatible = "atmel,at91rm9200-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = < 0x80000000 0x08000000 /* EBI CS3 */
+ 0xfc05c070 0x00000490 /* SMC PMECC regs */
+ 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
+ >;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
+ atmel,nand-addr-offset = <21>;
+ atmel,nand-cmd-offset = <22>;
+ atmel,nand-has-dma;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ status = "disabled";
+
+ nfc at 90000000 {
+ compatible = "atmel,sama5d3-nfc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <
+ 0x90000000 0x10000000 /* NFC Command Registers */
+ 0xfc05c000 0x00000070 /* NFC HSMC regs */
+ 0x00100000 0x00100000 /* NFC SRAM banks */
+ >;
+ clocks = <&hsmc_clk>;
+ atmel,write-by-sram;
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCHv2 6/8] ARM: at91: dt: add device tree file for SAMA5D4ek board
2014-09-12 15:42 [PATCHv2 0/8] Initial support for the Atmel SMART sama5d4 Alexandre Belloni
` (4 preceding siblings ...)
2014-09-12 15:43 ` [PATCHv2 5/8] ARM: at91: dt: add device tree file for SAMA5D4 SoC Alexandre Belloni
@ 2014-09-12 15:43 ` Alexandre Belloni
2014-09-12 15:43 ` [PATCHv2 7/8] ARM: at91: add sama5d4 support to sama5_defconfig Alexandre Belloni
2014-09-12 15:43 ` [PATCHv2 8/8] ARM: at91: document Atmel SMART compatibles Alexandre Belloni
7 siblings, 0 replies; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 15:43 UTC (permalink / raw)
To: linux-arm-kernel
From: Nicolas Ferre <nicolas.ferre@atmel.com>
Add reference SAMA5D4-EK platform DT file.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/at91-sama5d4ek.dts | 308 +++++++++++++++++++++++++++++++++++
2 files changed, 310 insertions(+)
create mode 100644 arch/arm/boot/dts/at91-sama5d4ek.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 75c7b7425c79..a7df6aeb5a1a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -48,6 +48,8 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
+# sama5d4
+dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
new file mode 100644
index 000000000000..aa01c2610c6d
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,308 @@
+/*
+ * sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ * Copyright (C) 2014 Atmel,
+ * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+ model = "Atmel SAMA5D4-EK";
+ compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
+
+ chosen {
+ bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
+ };
+
+ memory {
+ reg = <0x20000000 0x20000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ main_clock: clock at 0 {
+ compatible = "atmel,osc", "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ ahb {
+ apb {
+ lcd_bus at f0000000 {
+ status = "okay";
+
+ lcd at f0000000 {
+ status = "okay";
+ };
+
+ lcdovl1 at f0000140 {
+ status = "okay";
+ };
+
+ lcdovl2 at f0000240 {
+ status = "okay";
+ };
+
+ lcdheo1 at f0000340 {
+ status = "okay";
+ };
+ };
+
+ adc0: adc at fc034000 {
+ /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
+ atmel,adc-vref = <3300>;
+ /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
+ status = "okay"; /* Enable ADC IIO support */
+ };
+
+ mmc0: mmc at f8000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
+ slot at 1 {
+ reg = <1>;
+ bus-width = <4>;
+ cd-gpios = <&pioE 5 0>;
+ };
+ };
+
+ spi0: spi at f8010000 {
+ cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
+ status = "okay";
+ m25p80 at 0 {
+ compatible = "atmel,at25df321a";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+ };
+
+ i2c0: i2c at f8014000 {
+ status = "okay";
+ pmic: act8865 at 5b {
+ compatible = "active-semi,act8865";
+ reg = <0x5b>;
+ status = "okay";
+
+ regulators {
+ vcc_1v8_reg: DCDC_REG1 {
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc_1v2_reg: DCDC_REG2 {
+ regulator-name = "1V2_HDMI";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vcc_3v3_reg: DCDC_REG3 {
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_2v5_reg: LDO_REG1 {
+ regulator-name = "FUSE_2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ vdd_3v3_reg: LDO_REG2 {
+ regulator-name = "VDDANA";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_1v8_reg: LDO_REG3 {
+ regulator-name = "1V8_AUDIO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
+ macb0: ethernet at f8020000 {
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
+ mmc1: mmc at fc000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+ status = "okay";
+ slot at 0 {
+ reg = <0>;
+ bus-width = <4>;
+ cd-gpios = <&pioE 6 0>;
+ };
+ };
+
+ usart2: serial at fc008000 {
+ status = "okay";
+ };
+
+ usart3: serial at fc00c000 {
+ status = "okay";
+ };
+
+ usart4: serial at fc010000 {
+ status = "okay";
+ };
+
+ watchdog at fc068640 {
+ status = "okay";
+ };
+
+ pinctrl at fc06a000 {
+ board {
+ pinctrl_mmc0_cd: mmc0_cd {
+ atmel,pins =
+ <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+ pinctrl_mmc1_cd: mmc1_cd {
+ atmel,pins =
+ <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+ pinctrl_usba_vbus: usba_vbus {
+ atmel,pins =
+ <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
+ };
+ pinctrl_key_gpio: key_gpio_0 {
+ atmel,pins =
+ <AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
+ };
+ };
+ };
+ };
+
+ usb0: gadget at 00400000 {
+ atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+ };
+
+ usb1: ohci at 00500000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
+ &pioE 11 GPIO_ACTIVE_LOW
+ &pioE 12 GPIO_ACTIVE_LOW
+ >;
+ status = "okay";
+ };
+
+ usb2: ehci at 00600000 {
+ status = "okay";
+ };
+
+ nand0: nand at 80000000 {
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ atmel,has-pmecc;
+ status = "okay";
+
+ at91bootstrap at 0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader at 40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv at c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb at 180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel at 200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs at 800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio>;
+
+ pb_user1 {
+ label = "pb_user1";
+ gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
+ linux,code = <0x100>;
+ gpio-key,wakeup;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCHv2 7/8] ARM: at91: add sama5d4 support to sama5_defconfig
2014-09-12 15:42 [PATCHv2 0/8] Initial support for the Atmel SMART sama5d4 Alexandre Belloni
` (5 preceding siblings ...)
2014-09-12 15:43 ` [PATCHv2 6/8] ARM: at91: dt: add device tree file for SAMA5D4ek board Alexandre Belloni
@ 2014-09-12 15:43 ` Alexandre Belloni
2014-09-15 9:18 ` Nicolas Ferre
2014-09-12 15:43 ` [PATCHv2 8/8] ARM: at91: document Atmel SMART compatibles Alexandre Belloni
7 siblings, 1 reply; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 15:43 UTC (permalink / raw)
To: linux-arm-kernel
Add sama5d4 to sama5_defconfig to build kernel booting on both sama5d3 and
samad4.
Note that earlyprintk can only be working for one or the other.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/configs/sama5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 96c15b775d57..c9089c927daf 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -19,6 +19,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_AT91=y
CONFIG_SOC_SAM_V7=y
CONFIG_SOC_SAMA5D3=y
+CONFIG_SOC_SAMA5D4=y
CONFIG_MACH_SAMA5_DT=y
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCHv2 7/8] ARM: at91: add sama5d4 support to sama5_defconfig
2014-09-12 15:43 ` [PATCHv2 7/8] ARM: at91: add sama5d4 support to sama5_defconfig Alexandre Belloni
@ 2014-09-15 9:18 ` Nicolas Ferre
0 siblings, 0 replies; 15+ messages in thread
From: Nicolas Ferre @ 2014-09-15 9:18 UTC (permalink / raw)
To: linux-arm-kernel
On 12/09/2014 17:43, Alexandre Belloni :
> Add sama5d4 to sama5_defconfig to build kernel booting on both sama5d3 and
> samad4.
>
> Note that earlyprintk can only be working for one or the other.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> arch/arm/configs/sama5_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
> index 96c15b775d57..c9089c927daf 100644
> --- a/arch/arm/configs/sama5_defconfig
> +++ b/arch/arm/configs/sama5_defconfig
> @@ -19,6 +19,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
> CONFIG_ARCH_AT91=y
> CONFIG_SOC_SAM_V7=y
> CONFIG_SOC_SAMA5D3=y
> +CONFIG_SOC_SAMA5D4=y
> CONFIG_MACH_SAMA5_DT=y
> CONFIG_AEABI=y
> CONFIG_UACCESS_WITH_MEMCPY=y
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCHv2 8/8] ARM: at91: document Atmel SMART compatibles
2014-09-12 15:42 [PATCHv2 0/8] Initial support for the Atmel SMART sama5d4 Alexandre Belloni
` (6 preceding siblings ...)
2014-09-12 15:43 ` [PATCHv2 7/8] ARM: at91: add sama5d4 support to sama5_defconfig Alexandre Belloni
@ 2014-09-12 15:43 ` Alexandre Belloni
2014-09-12 16:47 ` Eric Bénard
2014-09-15 9:02 ` Nicolas Ferre
7 siblings, 2 replies; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 15:43 UTC (permalink / raw)
To: linux-arm-kernel
Document all the available compatibles for Atmel "SMART" SoCs.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
.../devicetree/bindings/arm/atmel-at91.txt | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 6e3e3e5c611f..2ef92e04ed10 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -1,6 +1,46 @@
Atmel AT91 device tree bindings.
================================
+Boards with a SoC of the Atmel AT91 or SMART family shall have the following
+properties:
+
+Required root node properties:
+compatible: must be one of:
+ * "atmel,rm9200"
+ * "atmel,at91sam9260"
+ * "atmel,at91sam9261"
+ * "atmel,at91sam9263"
+ * "atmel,at91sam9x5" for the x5 family, shall be extended with the specific SoC
+ compatible:
+ o "atmel,at91sam9g15"
+ o "atmel,at91sam9g25"
+ o "atmel,at91sam9g35"
+ o "atmel,at91sam9x25"
+ o "atmel,at91sam9x35"
+ * "atmel,at91sam9g20"
+ * "atmel,at91sam9g45"
+ * "atmel,at91sam9n12"
+ * "atmel,at91sam9rl"
+ * "atmel,sama5" for the cortexA5 family, shall be extended with the specific
+ SoC family:
+ o "atmel,sama5d3" shal be exteneded with the specific SoC compatible:
+ - "atmel,samad31"
+ - "atmel,samad33"
+ - "atmel,samad34"
+ - "atmel,samad35"
+ - "atmel,samad36"
+ o "atmel,sama5d4"
+
+
+In addition, the above compatible shall be extended with the specific
+SoC and board used. Currently known SoC compatibles are:
+ "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
+ "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
+ "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
+ "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
+ "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
+
+
PIT Timer required properties:
- compatible: Should be "atmel,at91sam9260-pit"
- reg: Should contain registers location and length
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCHv2 8/8] ARM: at91: document Atmel SMART compatibles
2014-09-12 15:43 ` [PATCHv2 8/8] ARM: at91: document Atmel SMART compatibles Alexandre Belloni
@ 2014-09-12 16:47 ` Eric Bénard
2014-09-12 17:36 ` Alexandre Belloni
2014-09-15 9:02 ` Nicolas Ferre
1 sibling, 1 reply; 15+ messages in thread
From: Eric Bénard @ 2014-09-12 16:47 UTC (permalink / raw)
To: linux-arm-kernel
Le Fri, 12 Sep 2014 17:43:07 +0200,
Alexandre Belloni <alexandre.belloni@free-electrons.com> a ?crit :
>
> Document all the available compatibles for Atmel "SMART" SoCs.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> .../devicetree/bindings/arm/atmel-at91.txt | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> index 6e3e3e5c611f..2ef92e04ed10 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> @@ -1,6 +1,46 @@
> Atmel AT91 device tree bindings.
> ================================
>
> +Boards with a SoC of the Atmel AT91 or SMART family shall have the following
> +properties:
> +
> +Required root node properties:
> +compatible: must be one of:
> + * "atmel,rm9200"
> + * "atmel,at91sam9260"
> + * "atmel,at91sam9261"
> + * "atmel,at91sam9263"
> + * "atmel,at91sam9x5" for the x5 family, shall be extended with the specific SoC
> + compatible:
> + o "atmel,at91sam9g15"
> + o "atmel,at91sam9g25"
> + o "atmel,at91sam9g35"
> + o "atmel,at91sam9x25"
> + o "atmel,at91sam9x35"
> + * "atmel,at91sam9g20"
> + * "atmel,at91sam9g45"
> + * "atmel,at91sam9n12"
> + * "atmel,at91sam9rl"
> + * "atmel,sama5" for the cortexA5 family, shall be extended with the specific
> + SoC family:
> + o "atmel,sama5d3" shal be exteneded with the specific SoC compatible:
^ extended
> + - "atmel,samad31"
> + - "atmel,samad33"
> + - "atmel,samad34"
> + - "atmel,samad35"
> + - "atmel,samad36"
> + o "atmel,sama5d4"
> +
> +
> +In addition, the above compatible shall be extended with the specific
> +SoC and board used. Currently known SoC compatibles are:
> + "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
> + "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
> + "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
> + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
> + "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
> +
> +
maybe remove those 10 last lines ;-)
Eric
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCHv2 8/8] ARM: at91: document Atmel SMART compatibles
2014-09-12 16:47 ` Eric Bénard
@ 2014-09-12 17:36 ` Alexandre Belloni
0 siblings, 0 replies; 15+ messages in thread
From: Alexandre Belloni @ 2014-09-12 17:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 12/09/2014 at 18:47:54 +0200, Eric B?nard wrote :
> > +
> > +
> > +In addition, the above compatible shall be extended with the specific
> > +SoC and board used. Currently known SoC compatibles are:
> > + "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
> > + "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
> > + "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
> > + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
> > + "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
> > +
> > +
> maybe remove those 10 last lines ;-)
>
I don't even know what they are doing here, I probably misclicked in the
wrong window at some point ;)
Thanks!
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCHv2 8/8] ARM: at91: document Atmel SMART compatibles
2014-09-12 15:43 ` [PATCHv2 8/8] ARM: at91: document Atmel SMART compatibles Alexandre Belloni
2014-09-12 16:47 ` Eric Bénard
@ 2014-09-15 9:02 ` Nicolas Ferre
1 sibling, 0 replies; 15+ messages in thread
From: Nicolas Ferre @ 2014-09-15 9:02 UTC (permalink / raw)
To: linux-arm-kernel
On 12/09/2014 17:43, Alexandre Belloni :
> Document all the available compatibles for Atmel "SMART" SoCs.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> .../devicetree/bindings/arm/atmel-at91.txt | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> index 6e3e3e5c611f..2ef92e04ed10 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> @@ -1,6 +1,46 @@
> Atmel AT91 device tree bindings.
> ================================
>
> +Boards with a SoC of the Atmel AT91 or SMART family shall have the following
> +properties:
> +
> +Required root node properties:
> +compatible: must be one of:
> + * "atmel,rm9200"
No, this one doesn't exists. Does it? It must be "atmel,at91rm9200".
> + * "atmel,at91sam9260"
> + * "atmel,at91sam9261"
> + * "atmel,at91sam9263"
> + * "atmel,at91sam9x5" for the x5 family, shall be extended with the specific SoC
> + compatible:
We call it the "5 series" or at91sam9x5 family, not the x5 family.
> + o "atmel,at91sam9g15"
> + o "atmel,at91sam9g25"
> + o "atmel,at91sam9g35"
> + o "atmel,at91sam9x25"
> + o "atmel,at91sam9x35"
> + * "atmel,at91sam9g20"
> + * "atmel,at91sam9g45"
> + * "atmel,at91sam9n12"
> + * "atmel,at91sam9rl"
> + * "atmel,sama5" for the cortexA5 family, shall be extended with the specific
for SoC using a Cortex-A5.
> + SoC family:
> + o "atmel,sama5d3" shal be exteneded with the specific SoC compatible:
s/shal/shall/
> + - "atmel,samad31"
samad31 => sama5d31
> + - "atmel,samad33"
> + - "atmel,samad34"
> + - "atmel,samad35"
> + - "atmel,samad36"
Ditto for all 4 above.
> + o "atmel,sama5d4"
Same here, you can also talk about a family:
o "atmel,sama5d41"
o "atmel,sama5d42"
o "atmel,sama5d43"
o "atmel,sama5d44"
> +
> +
> +In addition, the above compatible shall be extended with the specific
> +SoC and board used. Currently known SoC compatibles are:
> + "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
> + "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
> + "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
> + "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
> + "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
> +
> +
;-)
> PIT Timer required properties:
> - compatible: Should be "atmel,at91sam9260-pit"
> - reg: Should contain registers location and length
>
--
Nicolas Ferre
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