From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 4/7] ARM: l2c: Add support for overriding prefetch settings
Date: Sat, 20 Sep 2014 09:31:49 +0100 [thread overview]
Message-ID: <20140920083149.GI12379@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <20140919183007.GG29620@piout.net>
On Fri, Sep 19, 2014 at 08:30:07PM +0200, Alexandre Belloni wrote:
> On 19/09/2014 at 17:39:32 +0100, Russell King - ARM Linux wrote :
> > On Fri, Sep 19, 2014 at 11:50:01AM +0200, Alexandre Belloni wrote:
> > > On 26/08/2014 at 16:17:57 +0200, Tomasz Figa wrote :
> > > > Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
> > > > settings configured in registers leading to crashes if L2C is enabled
> > > > without overriding them. This patch introduces bindings to enable
> > > > prefetch settings to be specified from DT and necessary support in the
> > > > driver.
> > > >
> > > > Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> > >
> > > Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> > >
> > > It is working and useful on Atmel's sama5d4 were the bootloader is not
> > > configuring the L2C prefetch. However, I'm wondering whether we should
> > > add support for setting L310_PREFETCH_CTRL_DATA_PREFETCH and
> > > L310_PREFETCH_CTRL_INSTR_PREFETCH. I'm currently doing it by using
> > > ".l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
> > > L310_AUX_CTRL_INSTR_PREFETCH" (those are the same bits) but this has the
> > > disadvantage of displaying the "L2C: platform modifies aux control
> > > register:" twice.
> >
> > The L2C documentation, freely available from the ARM infocentre website,
> > has the answer to this for you.
> >
> > The two bits in the prefetch control register which control the data
> > and instruction prefetching are aliases of the aux control register.
> > If you set them to a value in one register, they are reflected in the
> > other.
> >
> > The reason for that is that once the L2 cache is enabled, writes to
> > the aux control register are no longer permitted, but it's safe to
> > enable and disable the prefetching with the cache already enabled.
> > This reason is even stated in the documentation.
> >
>
> Yeah, so my question still holds, should we have an other way to
> enable/disable I/D prefetch by adding two other DT bindings ?
Your question doesn't hold, because the above answers it conclusively.
No.
--
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.
next prev parent reply other threads:[~2014-09-20 8:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-26 14:17 [PATCH v4 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 1/7] ARM: l2c: Refactor the driver to use commit-like interface Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 4/7] ARM: l2c: Add support for overriding prefetch settings Tomasz Figa
2014-09-19 9:50 ` Alexandre Belloni
2014-09-19 16:39 ` Russell King - ARM Linux
2014-09-19 18:30 ` Alexandre Belloni
2014-09-20 8:31 ` Russell King - ARM Linux [this message]
2014-08-26 14:17 ` [PATCH v4 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Tomasz Figa
2014-09-15 8:58 ` Russell King - ARM Linux
2014-09-15 21:27 ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume Tomasz Figa
2014-09-15 9:03 ` Russell King - ARM Linux
2014-09-15 21:31 ` Tomasz Figa
2014-08-26 14:18 ` [PATCH v4 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller Tomasz Figa
2014-09-14 17:50 ` [PATCH v4 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Tomasz Figa
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20140920083149.GI12379@n2100.arm.linux.org.uk \
--to=linux@arm.linux.org.uk \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).