[PATCH 0/3] arm: ls1: add deep sleep support

[PATCH 0/3] arm: ls1: add deep sleep support

[Chenhui Zhao]

These patches are for supporting deep sleep on LS1.
They are based on the platform patches for LS1.

[PATCH 1/3] arm: ls1: add CPU hotplug platform support

[Chenhui Zhao]

From: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>

This implements CPU hotplug for ls1. When cpu is down, it will be put
in WFI state. When cpu is up, it will be waked by a IPI interrupt and
reinitialized.

Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
 arch/arm/mach-imx/common.h  |    4 ++
 arch/arm/mach-imx/hotplug.c |   90 +++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/platsmp.c |   22 ++++++++--
 arch/arm/mach-imx/src.c     |   21 ++++++++++
 4 files changed, 132 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 203ee73..2ca32fe 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -115,6 +115,7 @@ void tzic_handle_irq(struct pt_regs *);
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern u32 imx_get_cpu_arg(int cpu);
+extern u32 ls1_get_cpu_arg(int cpu);
 extern void imx_set_cpu_arg(int cpu, u32 arg);
 extern void v7_cpu_resume(void);
 #ifdef CONFIG_SMP
@@ -145,6 +146,9 @@ extern void imx6q_set_chicken_bit(void);
 extern void imx_cpu_die(unsigned int cpu);
 extern int imx_cpu_kill(unsigned int cpu);
 
+extern void ls1021a_cpu_die(unsigned int cpu);
+extern int ls1021a_cpu_kill(unsigned int cpu);
+
 #ifdef CONFIG_PM
 extern void imx6q_pm_init(void);
 extern void imx5_pm_init(void);
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 3daf1ed..646034f 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -14,6 +14,9 @@
 #include <linux/jiffies.h>
 #include <asm/cp15.h>
 #include <asm/proc-fns.h>
+#include<asm/smp.h>
+#include<asm/smp_plat.h>
+#include<asm/cacheflush.h>
 
 #include "common.h"
 
@@ -38,6 +41,22 @@ static inline void cpu_enter_lowpower(void)
 	  : "cc");
 }
 
+static inline void cpu_leave_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"	mrc     p15, 0, %0, c1, c0, 0\n"
+	"       orr     %0, %0, %1\n"
+	"       mcr     p15, 0, %0, c1, c0, 0\n"
+	"       mrc     p15, 0, %0, c1, c0, 1\n"
+	"       orr     %0, %0, %2\n"
+	"       mcr     p15, 0, %0, c1, c0, 1\n"
+	: "=&r" (v)
+	: "Ir" (CR_C), "Ir" (0x40)
+	: "cc");
+}
+
 /*
  * platform-specific code to shutdown a CPU
  *
@@ -66,3 +85,74 @@ int imx_cpu_kill(unsigned int cpu)
 	imx_set_cpu_arg(cpu, 0);
 	return 1;
 }
+
+static inline void ls1_do_lowpower(unsigned int cpu, int *spurious)
+{
+	/*
+	 * there is no power-control hardware on this platform, so all
+	 * we can do is put the core into WFI; this is safe as the calling
+	 * code will have already disabled interrupts
+	 */
+	for (;;) {
+		wfi();
+
+		if (pen_release == cpu_logical_map(cpu)) {
+			/*OK, proper wakeup, we're done*/
+			break;
+		}
+
+		/*
+		 * Getting here, means that we have come out of WFI without
+		 * having been woken up - this shouldn't happen
+		 *
+		 * Just note it happening - when we're woken, we can report
+		 * its occurrence.
+		 */
+		(*spurious)++;
+	}
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref ls1021a_cpu_die(unsigned int cpu)
+{
+	int spurious = 0;
+
+	v7_exit_coherency_flush(louis);
+
+	/*we're ready for shutdown now, so do it*/
+	ls1_do_lowpower(cpu, &spurious);
+
+	/*
+	 * bring this CPU back into the world of cache
+	 * coherency, and then restore interrupts
+	 */
+	cpu_leave_lowpower();
+
+	if (spurious)
+		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+
+	/*
+	 * Do not return to the idle loop - jump back to the secondary
+	 * cpu initialisation.  There's some initialisation which needs
+	 * to be repeated to undo the effects of taking the CPU offline.
+	 */
+	__asm__("mov    sp, %0\n"
+	"       mov     fp, #0\n"
+	"       b       ls1021a_secondary_startup"
+	:
+	: "r" (task_stack_page(current) + THREAD_SIZE - 8));
+}
+
+int ls1021a_cpu_kill(unsigned int cpu)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(50);
+
+	while (ls1_get_cpu_arg(cpu))
+		if (time_after(jiffies, timeout))
+			return 0;
+	return 1;
+}
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 5225b69..d262b32 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -29,6 +29,7 @@
 
 u32 g_diag_reg;
 static void __iomem *scu_base;
+void __iomem *dcfg_base;
 
 static struct map_desc scu_io_desc __initdata = {
 	/* .virtual and .pfn are run-time assigned */
@@ -196,19 +197,26 @@ static void __init ls1021a_smp_init_cpus(void)
 		set_cpu_possible(i, false);
 }
 
+void ls1021a_set_secondary_entry(void)
+{
+	unsigned long paddr;
+
+	if (dcfg_base) {
+		paddr = virt_to_phys(ls1021a_secondary_startup);
+		writel_relaxed(cpu_to_be32(paddr),
+				dcfg_base + DCFG_CCSR_SCRATCHRW1);
+	}
+}
+
 static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
 {
 	struct device_node *np;
-	void __iomem *dcfg_base;
-	unsigned long paddr;
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
 	dcfg_base = of_iomap(np, 0);
 	WARN_ON(!dcfg_base);
 
-	paddr = virt_to_phys(ls1021a_secondary_startup);
-	writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
-
+	ls1021a_set_secondary_entry();
 }
 
 struct smp_operations  ls1021a_smp_ops __initdata = {
@@ -216,4 +224,8 @@ struct smp_operations  ls1021a_smp_ops __initdata = {
 	.smp_prepare_cpus	= ls1021a_smp_prepare_cpus,
 	.smp_boot_secondary	= ls1021a_boot_secondary,
 	.smp_secondary_init	= ls1021a_secondary_init,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die                = ls1021a_cpu_die,
+	.cpu_kill               = ls1021a_cpu_kill,
+#endif
 };
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 10a6b1a..49508d6 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -30,6 +30,8 @@
 #define BP_SRC_SCR_CORE1_RST		14
 #define BP_SRC_SCR_CORE1_ENABLE		22
 
+#define CCSR_TWAITSR0         0x04C
+
 static void __iomem *src_base;
 static DEFINE_SPINLOCK(scr_lock);
 
@@ -114,6 +116,25 @@ void imx_set_cpu_arg(int cpu, u32 arg)
 	writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
 }
 
+u32 ls1_get_cpu_arg(int cpu)
+{
+	struct device_node *np;
+	void __iomem *ls1_rcpm_base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-rcpm-2.1");
+	if (!np) {
+		pr_err("%s(): Can not find the RCPM node.\n", __func__);
+		return -ENODEV;
+	}
+
+	ls1_rcpm_base = of_iomap(np, 0);
+	of_node_put(np);
+	WARN_ON(!ls1_rcpm_base);
+
+	cpu = cpu_logical_map(cpu);
+	return readl_relaxed(ls1_rcpm_base + CCSR_TWAITSR0) & (1 << cpu);
+}
+
 void imx_src_prepare_restart(void)
 {
 	u32 val;
-- 
1.7.3

[PATCH 1/3] arm: ls1: add CPU hotplug platform support

[Russell King - ARM Linux]

On Fri, Sep 26, 2014 at 07:25:01PM +0800, Chenhui Zhao wrote:
> +static inline void ls1_do_lowpower(unsigned int cpu, int *spurious)
> +{
> +	/*
> +	 * there is no power-control hardware on this platform, so all
> +	 * we can do is put the core into WFI; this is safe as the calling
> +	 * code will have already disabled interrupts
> +	 */
> +	for (;;) {
> +		wfi();
> +
> +		if (pen_release == cpu_logical_map(cpu)) {
> +			/*OK, proper wakeup, we're done*/
> +			break;
> +		}
> +
> +		/*
> +		 * Getting here, means that we have come out of WFI without
> +		 * having been woken up - this shouldn't happen
> +		 *
> +		 * Just note it happening - when we're woken, we can report
> +		 * its occurrence.
> +		 */
> +		(*spurious)++;
> +	}
> +}

This is pretty much unacceptable - this breaks kexec(), and suspend
support because your secondary CPUs aren't really sleeping, they're
sitting in a loop doing nothing.

In the kexec case, the code which the secondary CPU is executing can
be overwritten, which then means that the CPU ends up executing some
random code instead.

Do you really have no way to properly power down or reset the CPU
being unplugged?  If you don't, that's a *huge* oversight in this
modern age, and it means that you're pretty much stuck with having
these features disabled.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

[PATCH 1/3] arm: ls1: add CPU hotplug platform support

[Mark Rutland]

On Fri, Sep 26, 2014 at 01:20:04PM +0100, Russell King - ARM Linux wrote:
> On Fri, Sep 26, 2014 at 07:25:01PM +0800, Chenhui Zhao wrote:
> > +static inline void ls1_do_lowpower(unsigned int cpu, int *spurious)
> > +{
> > +	/*
> > +	 * there is no power-control hardware on this platform, so all
> > +	 * we can do is put the core into WFI; this is safe as the calling
> > +	 * code will have already disabled interrupts
> > +	 */
> > +	for (;;) {
> > +		wfi();
> > +
> > +		if (pen_release == cpu_logical_map(cpu)) {
> > +			/*OK, proper wakeup, we're done*/
> > +			break;
> > +		}
> > +
> > +		/*
> > +		 * Getting here, means that we have come out of WFI without
> > +		 * having been woken up - this shouldn't happen
> > +		 *
> > +		 * Just note it happening - when we're woken, we can report
> > +		 * its occurrence.
> > +		 */
> > +		(*spurious)++;
> > +	}
> > +}
> 
> This is pretty much unacceptable - this breaks kexec(), and suspend
> support because your secondary CPUs aren't really sleeping, they're
> sitting in a loop doing nothing.

Agreed.

This looks to be a carbon copy of the vexpress pseudo-hotplug in
arch/arm/mach-vexpress/hotplug.c, which is obviously broken in the way
you describe above. Perhaps we should go about ripping that out?

Mark.

[PATCH 1/3] arm: ls1: add CPU hotplug platform support

[Russell King - ARM Linux]

On Fri, Sep 26, 2014 at 01:46:14PM +0100, Mark Rutland wrote:
> On Fri, Sep 26, 2014 at 01:20:04PM +0100, Russell King - ARM Linux wrote:
> > On Fri, Sep 26, 2014 at 07:25:01PM +0800, Chenhui Zhao wrote:
> > > +static inline void ls1_do_lowpower(unsigned int cpu, int *spurious)
> > > +{
> > > +	/*
> > > +	 * there is no power-control hardware on this platform, so all
> > > +	 * we can do is put the core into WFI; this is safe as the calling
> > > +	 * code will have already disabled interrupts
> > > +	 */
> > > +	for (;;) {
> > > +		wfi();
> > > +
> > > +		if (pen_release == cpu_logical_map(cpu)) {
> > > +			/*OK, proper wakeup, we're done*/
> > > +			break;
> > > +		}
> > > +
> > > +		/*
> > > +		 * Getting here, means that we have come out of WFI without
> > > +		 * having been woken up - this shouldn't happen
> > > +		 *
> > > +		 * Just note it happening - when we're woken, we can report
> > > +		 * its occurrence.
> > > +		 */
> > > +		(*spurious)++;
> > > +	}
> > > +}
> > 
> > This is pretty much unacceptable - this breaks kexec(), and suspend
> > support because your secondary CPUs aren't really sleeping, they're
> > sitting in a loop doing nothing.
> 
> Agreed.
> 
> This looks to be a carbon copy of the vexpress pseudo-hotplug in
> arch/arm/mach-vexpress/hotplug.c, which is obviously broken in the way
> you describe above. Perhaps we should go about ripping that out?

The Versatile Express does not support suspend so the only problem case
is kexec.  However, isn't this support needed for big.LITTLE, and as
the Versatile Express is the platform which these features get developed
on, having working CPU hotplug seems rather fundamental for ARM kernel
feature development.

In that regard, Versatile Express is something of a special case.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

[PATCH 1/3] arm: ls1: add CPU hotplug platform support

[Mark Rutland]

> > This looks to be a carbon copy of the vexpress pseudo-hotplug in
> > arch/arm/mach-vexpress/hotplug.c, which is obviously broken in the way
> > you describe above. Perhaps we should go about ripping that out?
> 
> The Versatile Express does not support suspend so the only problem case
> is kexec.  However, isn't this support needed for big.LITTLE, and as
> the Versatile Express is the platform which these features get developed
> on, having working CPU hotplug seems rather fundamental for ARM kernel
> feature development.
> 
> In that regard, Versatile Express is something of a special case.

It is admittedly helpful during development to perform pseudo-hotplug on
Versatile Express. I have a local patch adding vexpress_cpu_disable so I
can test for bugs that only trigger if CPU0 is hotplugged.

Given that, perhaps we should make it clearer that Versatile Express is
not a reference implementation for CPU hotplug; add some Kconfig (e.g.
VEXPRESS_PSEUDO_HOTPLUG) that depends on !KEXEC && !SUSPEND, and putting
a note in hotplug.c stating it's not suitable as a reference
implementation.

...but perhaps that's overkill.

Mark.

[PATCH 1/3] arm: ls1: add CPU hotplug platform support

[Li Yang]

On Fri, Sep 26, 2014 at 9:20 PM, Mark Rutland <mark.rutland@arm.com> wrote:
>> > This looks to be a carbon copy of the vexpress pseudo-hotplug in
>> > arch/arm/mach-vexpress/hotplug.c, which is obviously broken in the way
>> > you describe above. Perhaps we should go about ripping that out?
>>
>> The Versatile Express does not support suspend so the only problem case
>> is kexec.  However, isn't this support needed for big.LITTLE, and as
>> the Versatile Express is the platform which these features get developed
>> on, having working CPU hotplug seems rather fundamental for ARM kernel
>> feature development.
>>
>> In that regard, Versatile Express is something of a special case.
>
> It is admittedly helpful during development to perform pseudo-hotplug on
> Versatile Express. I have a local patch adding vexpress_cpu_disable so I
> can test for bugs that only trigger if CPU0 is hotplugged.
>
> Given that, perhaps we should make it clearer that Versatile Express is
> not a reference implementation for CPU hotplug; add some Kconfig (e.g.
> VEXPRESS_PSEUDO_HOTPLUG) that depends on !KEXEC && !SUSPEND, and putting
> a note in hotplug.c stating it's not suitable as a reference
> implementation.
>
> ...but perhaps that's overkill.

I agree that the pseudo-hotplug is breaking the kexec.  However, I
don't think it breaks the system suspend case as tasks and interrupts
have been moved out of the non-booting CPU.  The pseudo-hotplug would
be even better than real hotplug as it introduces less latency.

Regards,
Leo

[PATCH 1/3] arm: ls1: add CPU hotplug platform support

[Russell King - ARM Linux]

On Sun, Sep 28, 2014 at 06:57:18PM +0800, Li Yang wrote:
> On Fri, Sep 26, 2014 at 9:20 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> >> > This looks to be a carbon copy of the vexpress pseudo-hotplug in
> >> > arch/arm/mach-vexpress/hotplug.c, which is obviously broken in the way
> >> > you describe above. Perhaps we should go about ripping that out?
> >>
> >> The Versatile Express does not support suspend so the only problem case
> >> is kexec.  However, isn't this support needed for big.LITTLE, and as
> >> the Versatile Express is the platform which these features get developed
> >> on, having working CPU hotplug seems rather fundamental for ARM kernel
> >> feature development.
> >>
> >> In that regard, Versatile Express is something of a special case.
> >
> > It is admittedly helpful during development to perform pseudo-hotplug on
> > Versatile Express. I have a local patch adding vexpress_cpu_disable so I
> > can test for bugs that only trigger if CPU0 is hotplugged.
> >
> > Given that, perhaps we should make it clearer that Versatile Express is
> > not a reference implementation for CPU hotplug; add some Kconfig (e.g.
> > VEXPRESS_PSEUDO_HOTPLUG) that depends on !KEXEC && !SUSPEND, and putting
> > a note in hotplug.c stating it's not suitable as a reference
> > implementation.
> >
> > ...but perhaps that's overkill.
> 
> I agree that the pseudo-hotplug is breaking the kexec.  However, I
> don't think it breaks the system suspend case as tasks and interrupts
> have been moved out of the non-booting CPU.  The pseudo-hotplug would
> be even better than real hotplug as it introduces less latency.

Sorry, that's not an acceptable reason to use it.

NAK.

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[PATCH 2/3] pm: add FSM configuration for deep sleep

[Chenhui Zhao]

For some Freescale's SoCs which support deep sleep, such as T1040,
LS1021, software will start a Finite State Machine (FSM) to control
the hardware precedure to enter deep sleep and return from it.

This patch configures parameters of the FSM preparing for deep sleep.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
 drivers/platform/Kconfig         |    1 +
 drivers/platform/Makefile        |    1 +
 drivers/platform/fsl/Kconfig     |   10 ++
 drivers/platform/fsl/Makefile    |    5 +
 drivers/platform/fsl/sleep_fsm.c |  281 ++++++++++++++++++++++++++++++++++++++
 drivers/platform/fsl/sleep_fsm.h |  100 ++++++++++++++
 6 files changed, 398 insertions(+), 0 deletions(-)
 create mode 100644 drivers/platform/fsl/Kconfig
 create mode 100644 drivers/platform/fsl/Makefile
 create mode 100644 drivers/platform/fsl/sleep_fsm.c
 create mode 100644 drivers/platform/fsl/sleep_fsm.h

diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 69616ae..54ada25 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -5,3 +5,4 @@ if GOLDFISH
 source "drivers/platform/goldfish/Kconfig"
 endif
 
+source "drivers/platform/fsl/Kconfig"
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index 8a44a4c..d0cce95 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -5,3 +5,4 @@
 obj-$(CONFIG_X86)		+= x86/
 obj-$(CONFIG_OLPC)		+= olpc/
 obj-$(CONFIG_GOLDFISH)		+= goldfish/
+obj-$(CONFIG_FSL_SOC)		+= fsl/
diff --git a/drivers/platform/fsl/Kconfig b/drivers/platform/fsl/Kconfig
new file mode 100644
index 0000000..72ed053
--- /dev/null
+++ b/drivers/platform/fsl/Kconfig
@@ -0,0 +1,10 @@
+#
+# Freescale Specific Power Management Drivers
+#
+
+config FSL_SLEEP_FSM
+	bool
+	help
+	  This driver configures a hardware FSM (Finite State Machine) for deep sleep.
+	  The FSM is used to finish clean-ups at the last stage of system entering deep
+	  sleep, and also wakes up system when a wake up event happens.
diff --git a/drivers/platform/fsl/Makefile b/drivers/platform/fsl/Makefile
new file mode 100644
index 0000000..d99ca0e
--- /dev/null
+++ b/drivers/platform/fsl/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for linux/drivers/platform/fsl
+# Freescale Specific Power Management Drivers
+#
+obj-$(CONFIG_FSL_SLEEP_FSM)	+= sleep_fsm.o
diff --git a/drivers/platform/fsl/sleep_fsm.c b/drivers/platform/fsl/sleep_fsm.c
new file mode 100644
index 0000000..d8478a1
--- /dev/null
+++ b/drivers/platform/fsl/sleep_fsm.c
@@ -0,0 +1,281 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/types.h>
+
+#include "sleep_fsm.h"
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in "8.4.3.8 Programming
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
+ * Power Management (RCPM)".
+ * The default value can be applied to T104x, LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+	/* EPGCR (Event Processor Global Control Register) */
+	{EPGCR, 0},
+	/* EPECR (Event Processor Event Control Registers) */
+	{EPECR0 + EPECR_STRIDE * 0, 0},
+	{EPECR0 + EPECR_STRIDE * 1, 0},
+	{EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+	{EPECR0 + EPECR_STRIDE * 3, 0x80000084},
+	{EPECR0 + EPECR_STRIDE * 4, 0x20000084},
+	{EPECR0 + EPECR_STRIDE * 5, 0x08000004},
+	{EPECR0 + EPECR_STRIDE * 6, 0x80000084},
+	{EPECR0 + EPECR_STRIDE * 7, 0x80000084},
+	{EPECR0 + EPECR_STRIDE * 8, 0x60000084},
+	{EPECR0 + EPECR_STRIDE * 9, 0x08000084},
+	{EPECR0 + EPECR_STRIDE * 10, 0x42000084},
+	{EPECR0 + EPECR_STRIDE * 11, 0x90000084},
+	{EPECR0 + EPECR_STRIDE * 12, 0x80000084},
+	{EPECR0 + EPECR_STRIDE * 13, 0x08000084},
+	{EPECR0 + EPECR_STRIDE * 14, 0x02000084},
+	/* This will be written just before entering deep sleep */
+	{EPECR0 + EPECR_STRIDE * 15, 0},
+	/*
+	 * EPEVTCR (Event Processor EVT Pin Control Registers)
+	 * SCU8 triger EVT2, and SCU11 triger EVT9
+	 */
+	{EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+	{EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
+	/* EPCMPR (Event Processor Counter Compare Registers) */
+	{EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
+	{EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+	{EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
+	{EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
+	/* EPCCR (Event Processor Counter Control Registers) */
+	{EPCCR0 + EPCCR_STRIDE * 0, 0},
+	{EPCCR0 + EPCCR_STRIDE * 1, 0},
+	{EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 3, 0},
+	{EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 6, 0},
+	{EPCCR0 + EPCCR_STRIDE * 7, 0},
+	{EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 13, 0},
+	{EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
+	{EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
+	/* EPSMCR (Event Processor SCU Mux Control Registers) */
+	{EPSMCR0 + EPSMCR_STRIDE * 0, 0},
+	{EPSMCR0 + EPSMCR_STRIDE * 1, 0},
+	{EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
+	{EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
+	{EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
+	{EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
+	{EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
+	{EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
+	{EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
+	{EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
+	{EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
+	{EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
+	{EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
+	{EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
+	{EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
+	{EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
+	/* EPACR (Event Processor Action Control Registers) */
+	{EPACR0 + EPACR_STRIDE * 0, 0},
+	{EPACR0 + EPACR_STRIDE * 1, 0},
+	{EPACR0 + EPACR_STRIDE * 2, 0},
+	{EPACR0 + EPACR_STRIDE * 3, 0x00000080},
+	{EPACR0 + EPACR_STRIDE * 4, 0},
+	{EPACR0 + EPACR_STRIDE * 5, 0x00000040},
+	{EPACR0 + EPACR_STRIDE * 6, 0},
+	{EPACR0 + EPACR_STRIDE * 7, 0},
+	{EPACR0 + EPACR_STRIDE * 8, 0},
+	{EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
+	{EPACR0 + EPACR_STRIDE * 10, 0x00000020},
+	{EPACR0 + EPACR_STRIDE * 11, 0},
+	{EPACR0 + EPACR_STRIDE * 12, 0x00000003},
+	{EPACR0 + EPACR_STRIDE * 13, 0x06000000},
+	{EPACR0 + EPACR_STRIDE * 14, 0x04000000},
+	{EPACR0 + EPACR_STRIDE * 15, 0x02000000},
+	/* EPIMCR (Event Processor Input Mux Control Registers) */
+	{EPIMCR0 + EPIMCR_STRIDE * 0, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 1, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 2, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 3, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 6, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 7, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 8, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 9, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 10, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 11, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 13, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 14, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 15, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 17, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 18, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 19, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 21, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 23, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 24, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 25, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 26, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 27, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
+	{EPIMCR0 + EPIMCR_STRIDE * 29, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 30, 0},
+	{EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
+	/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+	{EPXTRIGCR, 0x0000FFDF},
+	/* end */
+	{FSM_END_FLAG, 0},
+};
+
+struct fsm_reg_vals npc_default_val[] = {
+	/* NPC triggered Memory-Mapped Access Registers */
+	{NCR, 0x80000000},
+	{MCCR1, 0},
+	{MCSR1, 0},
+	{MMAR1LO, 0},
+	{MMAR1HI, 0},
+	{MMDR1, 0},
+	{MCSR2, 0},
+	{MMAR2LO, 0},
+	{MMAR2HI, 0},
+	{MMDR2, 0},
+	{MCSR3, 0x80000000},
+	{MMAR3LO, 0x000E2130},
+	{MMAR3HI, 0x00030000},
+	{MMDR3, 0x00020000},
+	/* end */
+	{FSM_END_FLAG, 0},
+};
+
+void fsm_write32(void __iomem *addr, u32 val)
+{
+#ifdef __arm__
+	iowrite32be(val, addr);
+#endif
+
+#ifdef __powerpc__
+	out_be32(addr, val);
+#endif
+}
+
+/**
+ * fsl_fsm_setup - Configure EPU's FSM registers
+ * @base: the base address of registers
+ * @val: Pointer to address-value pairs for FSM registers
+ */
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
+{
+	struct fsm_reg_vals *data = val;
+
+	BUG_ON(!base || !data);
+	while (data->offset != FSM_END_FLAG) {
+		fsm_write32(base + data->offset, data->value);
+		data++;
+	}
+}
+
+void fsl_epu_setup_default(void __iomem *epu_base)
+{
+	fsl_fsm_setup(epu_base, epu_default_val);
+}
+
+void fsl_npc_setup_default(void __iomem *npc_base)
+{
+	fsl_fsm_setup(npc_base, npc_default_val);
+}
+
+/**
+ * fsl_fsm_clean - Clear EPU's FSM registers
+ * @base: the base address of registers
+ * @val: Pointer to address-value pairs for FSM registers
+ */
+void fsl_fsm_clean(void __iomem *base, struct fsm_reg_vals *val)
+{
+	struct fsm_reg_vals *data = val;
+
+	BUG_ON(!base || !data);
+	while (data->offset != FSM_END_FLAG) {
+		fsm_write32(base + data->offset, 0);
+		data++;
+	}
+}
+
+void fsl_epu_clean_default(void __iomem *epu_base)
+{
+	u32 offset;
+
+	/* follow the exact sequence to clear the registers */
+	/* Clear EPACRn */
+	for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+		fsm_write32(epu_base + offset, 0);
+
+	/* Clear EPEVTCRn */
+	for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+		fsm_write32(epu_base + offset, 0);
+
+	/* Clear EPGCR */
+	fsm_write32(epu_base + EPGCR, 0);
+
+	/* Clear EPSMCRn */
+	for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+		fsm_write32(epu_base + offset, 0);
+
+	/* Clear EPCCRn */
+	for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+		fsm_write32(epu_base + offset, 0);
+
+	/* Clear EPCMPRn */
+	for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+		fsm_write32(epu_base + offset, 0);
+
+	/* Clear EPCTRn */
+	for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+		fsm_write32(epu_base + offset, 0);
+
+	/* Clear EPIMCRn */
+	for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+		fsm_write32(epu_base + offset, 0);
+
+	/* Clear EPXTRIGCRn */
+	fsm_write32(epu_base + EPXTRIGCR, 0);
+
+	/* Clear EPECRn */
+	for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+		fsm_write32(epu_base + offset, 0);
+}
diff --git a/drivers/platform/fsl/sleep_fsm.h b/drivers/platform/fsl/sleep_fsm.h
new file mode 100644
index 0000000..19334e2
--- /dev/null
+++ b/drivers/platform/fsl/sleep_fsm.h
@@ -0,0 +1,100 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _FSL_SLEEP_FSM_H
+#define _FSL_SLEEP_FSM_H
+
+#define FSL_STRIDE_4B	4
+#define FSL_STRIDE_8B	8
+
+/* End flag */
+#define FSM_END_FLAG		0xFFFFFFFFUL
+
+/* Block offsets */
+#define RCPM_BLOCK_OFFSET	0x00022000
+#define EPU_BLOCK_OFFSET	0x00000000
+#define NPC_BLOCK_OFFSET	0x00001000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR		0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0	0x050
+#define EPEVTCR9	0x074
+#define EPEVTCR_STRIDE	FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR	0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0		0x100
+#define EPIMCR31	0x17C
+#define EPIMCR_STRIDE	FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0		0x200
+#define EPSMCR15	0x278
+#define EPSMCR_STRIDE	FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0		0x300
+#define EPECR15		0x33C
+#define EPECR_STRIDE	FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0		0x400
+#define EPACR15		0x43C
+#define EPACR_STRIDE	FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0		0x800
+#define EPCCR15		0x83C
+#define EPCCR31		0x87C
+#define EPCCR_STRIDE	FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0		0x900
+#define EPCMPR15	0x93C
+#define EPCMPR31	0x97C
+#define EPCMPR_STRIDE	FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0		0xA00
+#define EPCTR31		0xA7C
+#define EPCTR_STRIDE	FSL_STRIDE_4B
+
+/* NPC triggered Memory-Mapped Access Registers */
+#define NCR		0x000
+#define MCCR1		0x0CC
+#define MCSR1		0x0D0
+#define MMAR1LO		0x0D4
+#define MMAR1HI		0x0D8
+#define MMDR1		0x0DC
+#define MCSR2		0x0E0
+#define MMAR2LO		0x0E4
+#define MMAR2HI		0x0E8
+#define MMDR2		0x0EC
+#define MCSR3		0x0F0
+#define MMAR3LO		0x0F4
+#define MMAR3HI		0x0F8
+#define MMDR3		0x0FC
+
+/* RCPM Core State Action Control Register 0 */
+#define CSTTACR0	0xB00
+
+/* RCPM Core Group 1 Configuration Register 0 */
+#define CG1CR0		0x31C
+
+struct fsm_reg_vals {
+	u32 offset;
+	u32 value;
+};
+
+#endif /* _FSL_SLEEP_FSM_H */
-- 
1.7.3

[PATCH 2/3] pm: add FSM configuration for deep sleep

[Russell King - ARM Linux]

On Fri, Sep 26, 2014 at 07:25:02PM +0800, Chenhui Zhao wrote:
> +void fsm_write32(void __iomem *addr, u32 val)
> +{
> +#ifdef __arm__
> +	iowrite32be(val, addr);
> +#endif
> +
> +#ifdef __powerpc__
> +	out_be32(addr, val);
> +#endif

The idea of iowrite* is that it should be able to address MMIO or IO
memory irrespective of the platform.  Why is PowerPC not implementing
this accessor, or why can't it be used for PowerPC?

This should just use iowrite32be(), and if it doesn't work on PowerPC,
PowerPC needs to be fixed.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

[PATCH 2/3] pm: add FSM configuration for deep sleep

[Russell King - ARM Linux]

On Fri, Sep 26, 2014 at 01:02:01PM +0100, Russell King - ARM Linux wrote:
> On Fri, Sep 26, 2014 at 07:25:02PM +0800, Chenhui Zhao wrote:
> > +void fsm_write32(void __iomem *addr, u32 val)
> > +{
> > +#ifdef __arm__
> > +	iowrite32be(val, addr);
> > +#endif
> > +
> > +#ifdef __powerpc__
> > +	out_be32(addr, val);
> > +#endif
> 
> The idea of iowrite* is that it should be able to address MMIO or IO
> memory irrespective of the platform.  Why is PowerPC not implementing
> this accessor, or why can't it be used for PowerPC?
> 
> This should just use iowrite32be(), and if it doesn't work on PowerPC,
> PowerPC needs to be fixed.

BenH tells me that this should be able to use iowrite32be() on PowerPC
too without problems, there should be no need to use the older out_be32()
accessors here.  Please can you look into using only iowrite32be() here?

Thanks.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

[PATCH 2/3] pm: add FSM configuration for deep sleep

[Chenhui Zhao]

On Fri, Sep 26, 2014 at 09:51:53PM +0100, Russell King - ARM Linux wrote:
> On Fri, Sep 26, 2014 at 01:02:01PM +0100, Russell King - ARM Linux wrote:
> > On Fri, Sep 26, 2014 at 07:25:02PM +0800, Chenhui Zhao wrote:
> > > +void fsm_write32(void __iomem *addr, u32 val)
> > > +{
> > > +#ifdef __arm__
> > > +	iowrite32be(val, addr);
> > > +#endif
> > > +
> > > +#ifdef __powerpc__
> > > +	out_be32(addr, val);
> > > +#endif
> > 
> > The idea of iowrite* is that it should be able to address MMIO or IO
> > memory irrespective of the platform.  Why is PowerPC not implementing
> > this accessor, or why can't it be used for PowerPC?
> > 
> > This should just use iowrite32be(), and if it doesn't work on PowerPC,
> > PowerPC needs to be fixed.
> 
> BenH tells me that this should be able to use iowrite32be() on PowerPC
> too without problems, there should be no need to use the older out_be32()
> accessors here.  Please can you look into using only iowrite32be() here?
> 
> Thanks.
> 

Thanks. I'll fix it.

Chenhui

[PATCH 3/3] arm: pm: add deep sleep support for LS1

[Chenhui Zhao]

LS1 supports deep sleep feature that can switch off most parts of
the SoC when it is in deep sleep state.

The DDR controller will also be powered off in deep sleep. Therefore,
copy the last stage code to enter deep sleep to SRAM and run it
with disabling MMU and caches.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
 arch/arm/mach-imx/Kconfig     |    1 +
 arch/arm/mach-imx/Makefile    |    1 +
 arch/arm/mach-imx/pm-ls1.c    |  329 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/sleep-ls1.S |  142 ++++++++++++++++++
 4 files changed, 473 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-imx/pm-ls1.c
 create mode 100644 arch/arm/mach-imx/sleep-ls1.S

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b85534c..716bb1b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -866,6 +866,7 @@ config SOC_LS1021A
 	select HAVE_SMP
 	select ARCH_LAYERSCAPE
 	select ZONE_DMA if ARM_LPAE
+	select FSL_SLEEP_FSM if PM
 
 	help
 	  This enable support for Freescale Layerscape LS1021A  processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 41b8044..9931528 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -102,6 +102,7 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
 
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+obj-$(CONFIG_SOC_LS1021A) += pm-ls1.o sleep-ls1.o
 endif
 
 # i.MX5 based machines
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c
new file mode 100644
index 0000000..621fdb4
--- /dev/null
+++ b/arch/arm/mach-imx/pm-ls1.c
@@ -0,0 +1,329 @@
+/*
+ * Support deep sleep feature for LS1
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General	 Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/cpu_pm.h>
+#include <asm/suspend.h>
+#include <asm/delay.h>
+#include <asm/cacheflush.h>
+
+#define FSL_SLEEP		0x1
+#define FSL_DEEP_SLEEP		0x2
+
+#define DCSR_EPU_EPECR0		0x300
+#define DCSR_RCPM_CG1CR0	0x31c
+#define DCSR_RCPM_CSTTACR0	0xb00
+
+/* in SCFG registers except for SPARECR registers, reverse bits in each byte */
+#define CCSR_SCFG_DPSLPCR	0
+#define CCSR_SCFG_DPSLPCR_VAL	0x00000080
+#define CCSR_SCFG_SPARECR2	0x504
+#define CCSR_SCFG_SPARECR3	0x508
+
+#define CCSR_DCFG_CRSTSR	0x400
+#define CCSR_DCFG_CRSTSR_VAL	0x00000008
+
+#define CCSR_RCPM_POWMGTCSR		0x130
+#define CCSR_RCPM_POWMGTCSR_LPM20_REQ	0x00100000
+#define CCSR_RCPM_POWMGTCSR_LPM20_ST	0x00000200
+#define CCSR_RCPM_POWMGTCSR_P_LPM20_ST	0x00000100
+#define CCSR_RCPM_CLPCL10SETR		0x1c4
+#define CCSR_RCPM_CLPCL10SETR_C0	0x1
+
+#define QIXIS_CTL_SYS			0x5
+#define QIXIS_CTL_SYS_EVTSW_MASK	0x0c
+#define QIXIS_CTL_SYS_EVTSW_IRQ		0x04
+
+#define QIXIS_PWR_CTL2		0x21
+#define QIXIS_PWR_CTL2_PCTL	0x2
+
+#define OCRAM_BASE	0x10000000
+#define OCRAM_SIZE	0x10000		/* 64K */
+/* use the last page of SRAM */
+#define SRAM_CODE_BASE_PHY	(OCRAM_BASE + OCRAM_SIZE - PAGE_SIZE)
+
+struct ls1_pm_baseaddr {
+	void __iomem *epu;
+	void __iomem *dcsr_rcpm1;
+	void __iomem *dcsr_rcpm2;
+	void __iomem *rcpm;
+	void __iomem *scfg;
+	void __iomem *dcfg;
+	void __iomem *fpga;
+	void __iomem *sram;
+};
+
+/* 128 bytes buffer for restoring data broke by DDR training initialization */
+#define DDR_BUF_SIZE	128
+static u8 ddr_buff[DDR_BUF_SIZE] __aligned(64);
+static struct ls1_pm_baseaddr ls1_pm_base;
+/* supported sleep modes by the present platform */
+static unsigned int sleep_modes;
+
+extern void ls1_do_deepsleep(unsigned long addr);
+extern void ls1_start_fsm(void);
+extern void ls1_deepsleep_resume(void);
+extern void ls1021a_set_secondary_entry(void);
+extern int ls1_sram_code_size;
+extern void fsl_epu_setup_default(void __iomem *epu_base);
+
+static void ls1_pm_iomap(void)
+{
+	struct device_node *np;
+	void *base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcsr-epu");
+	base = of_iomap(np, 0);
+	BUG_ON(!base);
+	ls1_pm_base.epu = base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcsr-rcpm");
+	base = of_iomap(np, 0);
+	BUG_ON(!base);
+	ls1_pm_base.dcsr_rcpm1 = base;
+	base = of_iomap(np, 1);
+	BUG_ON(!base);
+	ls1_pm_base.dcsr_rcpm2 = base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-scfg");
+	base = of_iomap(np, 0);
+	BUG_ON(!base);
+	ls1_pm_base.scfg = base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
+	base = of_iomap(np, 0);
+	BUG_ON(!base);
+	ls1_pm_base.dcfg = base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,ls1021aqds-fpga");
+	base = of_iomap(np, 0);
+	BUG_ON(!base);
+	ls1_pm_base.fpga = base;
+
+	base = ioremap(SRAM_CODE_BASE_PHY, PAGE_SIZE);
+	BUG_ON(!base);
+	ls1_pm_base.sram = base;
+}
+
+static void ls1_pm_uniomap(void)
+{
+	iounmap(ls1_pm_base.epu);
+	iounmap(ls1_pm_base.dcsr_rcpm1);
+	iounmap(ls1_pm_base.dcsr_rcpm2);
+	iounmap(ls1_pm_base.scfg);
+	iounmap(ls1_pm_base.dcfg);
+	iounmap(ls1_pm_base.fpga);
+	iounmap(ls1_pm_base.sram);
+}
+
+static void ls1_save_ddr(void *base)
+{
+	u32 ddr_buff_addr;
+
+	/*
+	 * DDR training initialization will break 128 bytes at the beginning
+	 * of DDR, therefore, save them so that the bootloader will restore
+	 * them. Assume that DDR is mapped to the address space started with
+	 * CONFIG_PAGE_OFFSET.
+	 */
+	memcpy(ddr_buff, (void *)CONFIG_PAGE_OFFSET, DDR_BUF_SIZE);
+
+	ddr_buff_addr = (u32)__pa(ddr_buff);
+
+	/*
+	 * the bootloader will restore the first 128 bytes of DDR from
+	 * the location indicated by the register SPARECR3
+	 */
+	writel_relaxed(ddr_buff_addr, base + CCSR_SCFG_SPARECR3);
+}
+
+static void ls1_set_resume_entry(void *base)
+{
+	u32 resume_addr;
+
+	/* the bootloader will finally jump to this address to resume kernel */
+	resume_addr = (u32)(__pa(ls1_deepsleep_resume));
+
+	/* use the register SPARECR2 to save the return entry */
+	writel_relaxed(resume_addr, base + CCSR_SCFG_SPARECR2);
+}
+
+static void ls1_copy_sram_code(void)
+{
+	memcpy(ls1_pm_base.sram, ls1_start_fsm, ls1_sram_code_size);
+}
+
+static int ls1_start_deepsleep(unsigned long addr)
+{
+	ls1_do_deepsleep(addr);
+
+	return 0;
+}
+
+void ls1_fsm_setup(void)
+{
+	iowrite32be(0x00001001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CSTTACR0);
+	iowrite32be(0x00000001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CG1CR0);
+
+	fsl_epu_setup_default(ls1_pm_base.epu);
+
+	/*
+	 * pull the MCKE signal(EVT4_B pin) low before enabling
+	 * deep sleep signals by FPGA
+	 */
+	iowrite32be(0x5, ls1_pm_base.epu + DCSR_EPU_EPECR0);
+}
+
+static inline void ls1_clrsetbits_le32(void __iomem *addr, u32 clear, u32 set)
+{
+	u32 tmp;
+
+	tmp = ioread32(addr);
+	tmp = (tmp & ~clear) | set;
+	iowrite32(tmp, addr);
+}
+
+static void ls1_enter_deepsleep(void)
+{
+	u32 tmp;
+
+	/* save DDR data */
+	ls1_save_ddr(ls1_pm_base.scfg);
+
+	/* save kernel resume entry */
+	ls1_set_resume_entry(ls1_pm_base.scfg);
+
+	/* Request to put cluster 0 in PCL10 state */
+	iowrite32be(CCSR_RCPM_CLPCL10SETR_C0,
+		ls1_pm_base.rcpm + CCSR_RCPM_CLPCL10SETR);
+
+	/* setup the registers of the EPU FSM for deep sleep */
+	ls1_fsm_setup();
+
+	/* enable deep sleep signals in FPGA */
+	tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+	iowrite8(tmp | QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+
+	/* enable Warm Device Reset */
+	ls1_clrsetbits_le32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
+			    CCSR_SCFG_DPSLPCR_VAL, CCSR_SCFG_DPSLPCR_VAL);
+
+	ls1_clrsetbits_le32(ls1_pm_base.dcfg + CCSR_DCFG_CRSTSR,
+			    CCSR_DCFG_CRSTSR_VAL, CCSR_DCFG_CRSTSR_VAL);
+
+	/* copy the last stage code to sram */
+	ls1_copy_sram_code();
+
+	cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
+
+	/* disable Warm Device Reset */
+	ls1_clrsetbits_le32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
+			    CCSR_SCFG_DPSLPCR_VAL, 0);
+
+	/* disable deep sleep signals in FPGA */
+	tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+	iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+
+	/* call smp_prepare_cpus */
+	ls1021a_set_secondary_entry();
+}
+
+static int ls1_suspend_enter(suspend_state_t state)
+{
+	int ret = 0;
+
+	switch (state) {
+	case PM_SUSPEND_STANDBY:
+		flush_cache_louis();
+		ls1_clrsetbits_le32(ls1_pm_base.rcpm + CCSR_RCPM_POWMGTCSR,
+				    CCSR_RCPM_POWMGTCSR_LPM20_REQ,
+				    CCSR_RCPM_POWMGTCSR_LPM20_REQ);
+
+		cpu_do_idle();
+		break;
+
+	case PM_SUSPEND_MEM:
+		ls1_enter_deepsleep();
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int ls1_suspend_valid(suspend_state_t state)
+{
+	if (state == PM_SUSPEND_STANDBY && (sleep_modes & FSL_SLEEP))
+		return 1;
+
+	if (state == PM_SUSPEND_MEM && (sleep_modes & FSL_DEEP_SLEEP))
+		return 1;
+
+	return 0;
+}
+
+static int ls1_suspend_begin(suspend_state_t state)
+{
+	ls1_pm_iomap();
+
+	return 0;
+}
+
+static void ls1_suspend_end(void)
+{
+	ls1_pm_uniomap();
+}
+
+static const struct platform_suspend_ops ls1_suspend_ops = {
+	.valid = ls1_suspend_valid,
+	.enter = ls1_suspend_enter,
+	.begin = ls1_suspend_begin,
+	.end = ls1_suspend_end,
+};
+
+
+static const struct of_device_id rcpm_matches[] = {
+	{
+		.compatible = "fsl,ls1021a-rcpm",
+		.data = (void *)(FSL_SLEEP | FSL_DEEP_SLEEP),
+	},
+	{}
+};
+
+static int __init ls1_pm_init(void)
+{
+	const struct of_device_id *match;
+	struct device_node *np;
+	void *base;
+
+	np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
+	if (!np) {
+		pr_err("%s: can't find the rcpm node.\n", __func__);
+		return -EINVAL;
+	}
+
+	base = of_iomap(np, 0);
+	of_node_put(np);
+	if (!base)
+		return -ENOMEM;
+
+	sleep_modes = (unsigned int)match->data;
+	ls1_pm_base.rcpm = base;
+	suspend_set_ops(&ls1_suspend_ops);
+	return 0;
+}
+arch_initcall(ls1_pm_init);
diff --git a/arch/arm/mach-imx/sleep-ls1.S b/arch/arm/mach-imx/sleep-ls1.S
new file mode 100644
index 0000000..1cdcbfe
--- /dev/null
+++ b/arch/arm/mach-imx/sleep-ls1.S
@@ -0,0 +1,142 @@
+/*
+ * Support deep sleep feature for LS1
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General	 Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/cache.h>
+
+#define CCSR_DDR_BASE			0x01080000
+#define CCSR_DDR_SDRAM_CFG_2		0x114
+
+#define CCSR_SCFG_BASE			0x01570000
+#define CCSR_SCFG_HRSTCR		0x1a8
+
+#define DCSR_EPU_BASE			0x20000000
+#define	DCSR_EPU_EPGCR			0x0
+#define DCSR_EPU_EPECR0			0x300
+#define DCSR_EPU_EPECR15		0x33c
+
+/* for big endian registers */
+.macro ls1_set_bits, addr, value
+	ldr	r4, \addr
+	ldr	r5, [r4]
+	ldr	r6, \value
+	rev	r6, r6
+	orr	r5, r5, r6
+	str	r5, [r4]
+.endm
+
+/* 1000 loops per round */
+.macro ls1_delay, count
+	mov	r0, \count
+11:	mov	r8, #1000
+12:	subs	r8, r8, #1
+	bne	12b
+	subs	r0, r0, #1
+	bne	11b
+.endm
+
+/*
+ * r0: the physical entry address of SRAM code
+ *
+ */
+ENTRY(ls1_do_deepsleep)
+	mov	r13, r0
+
+	/* flush cache */
+	bl	v7_flush_dcache_all
+
+	/* disable cache, C bit in SCTLR */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #(1 << 2)
+	mcr	p15, 0, r0, c1, c0, 0
+	isb
+
+	/* disable coherency, SMP bit in ACTLR */
+	mrc	p15, 0, r0, c1, c0, 1
+	bic	r0, r0, #(1 << 6)
+	mcr	p15, 0, r0, c1, c0, 1
+	isb
+	dsb
+
+	/* disable MMU, M bit in SCTLR */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #1
+	mcr	p15, 0, r0, c1, c0, 0
+	isb
+
+	/* jump to sram code using physical address */
+	bx	r13
+ENDPROC(ls1_do_deepsleep)
+
+/*
+ * The code will be copied to SRAM.
+ */
+	.align L1_CACHE_SHIFT
+ENTRY(ls1_start_fsm)
+	/* set HRSTCR */
+	ls1_set_bits	ls1_ccsr_scfg_hrstcr_addr, ls1_ccsr_scfg_hrstcr_val
+
+	/* Place DDR controller in self refresh mode */
+	ls1_set_bits	ls1_ddr_cfg2_addr, ls1_ddr_cfg2_val
+
+	ls1_delay	#2000
+
+	/* Set EVT4_B to lock the signal MCKE down */
+	ldr	r4, ls1_dcsr_epu_epecr0
+	ldr	r5, ls1_dcsr_epu_epecr0_val
+	rev	r5, r5
+	str	r5, [r4]
+
+	ls1_delay	#2000
+
+	/* Enable all EPU Counters */
+	ls1_set_bits	ls1_dcsr_epu_epgcr_addr, ls1_dcsr_epu_epgcr_val
+
+	/* Enable SCU15 */
+	ls1_set_bits	ls1_dcsr_epu_epecr15, ls1_dcsr_epu_epecr15_val
+
+	/* Enter WFI mode, and EPU FSM will start */
+20:	wfi
+	b	20b
+
+ls1_ccsr_scfg_hrstcr_addr:
+	.word	CCSR_SCFG_BASE + CCSR_SCFG_HRSTCR
+ls1_ccsr_scfg_hrstcr_val:
+	.word	0x01000000
+
+ls1_ddr_cfg2_addr:
+	.word	CCSR_DDR_BASE + CCSR_DDR_SDRAM_CFG_2
+ls1_ddr_cfg2_val:
+	.word	(1 << 31)
+
+ls1_dcsr_epu_epgcr_addr:
+	.word	DCSR_EPU_BASE + DCSR_EPU_EPGCR
+ls1_dcsr_epu_epgcr_val:
+	.word	0x80000000
+
+ls1_dcsr_epu_epecr0:
+	.word	DCSR_EPU_BASE + DCSR_EPU_EPECR0
+ls1_dcsr_epu_epecr0_val:
+	.word	0
+
+ls1_dcsr_epu_epecr15:
+	.word	DCSR_EPU_BASE + DCSR_EPU_EPECR15
+ls1_dcsr_epu_epecr15_val:
+	.word	0x90000004
+
+ENTRY(ls1_sram_code_size)
+	.word	. - ls1_start_fsm
+
+/* the bootloader will jump to here after wakeup from deep sleep  */
+	.align L1_CACHE_SHIFT
+ENTRY(ls1_deepsleep_resume)
+	b cpu_resume
-- 
1.7.3

[PATCH 3/3] arm: pm: add deep sleep support for LS1

[Russell King - ARM Linux]

On Fri, Sep 26, 2014 at 07:25:03PM +0800, Chenhui Zhao wrote:
> +static int ls1_start_deepsleep(unsigned long addr)
> +{
> +	ls1_do_deepsleep(addr);
> +
> +	return 0;
> +}
...
> +	cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);

What's the point of this function?  Why can't ls1_do_deepsleep() just
return zero?

> +/*
> + * r0: the physical entry address of SRAM code
> + *
> + */
> +ENTRY(ls1_do_deepsleep)
> +	mov	r13, r0
> +
> +	/* flush cache */
> +	bl	v7_flush_dcache_all

Please explain the purpose of this call via a comment in the code.

The generic code will have saved the CPU state, and will have called
flush_cache_louis() to flush the caches to the point of unification.

The only data which will have been loaded into the cache between that
point is the stack for the return from __cpu_suspend_save, and
speculative prefetches.

So, the only reason I can gather is that you need to flush data from
lower levels of the cache below the point of unification.

> +
> +	/* disable cache, C bit in SCTLR */
> +	mrc	p15, 0, r0, c1, c0, 0
> +	bic	r0, r0, #(1 << 2)
> +	mcr	p15, 0, r0, c1, c0, 0
> +	isb
> +
> +	/* disable coherency, SMP bit in ACTLR */
> +	mrc	p15, 0, r0, c1, c0, 1
> +	bic	r0, r0, #(1 << 6)
> +	mcr	p15, 0, r0, c1, c0, 1
> +	isb
> +	dsb
> +
> +	/* disable MMU, M bit in SCTLR */
> +	mrc	p15, 0, r0, c1, c0, 0
> +	bic	r0, r0, #1
> +	mcr	p15, 0, r0, c1, c0, 0
> +	isb
> +
> +	/* jump to sram code using physical address */
> +	bx	r13

This looks extremely fragile.  You are running in virtual space, and you
turn the MMU off.  You are reliant on the MMU still being on for the
following instructions to already be in the pipeline.  That's not a
very good assumption to make (we've made it in the past and it breaks
every so often when things change, eg when the code is no longer laid
out how we expect.)

You need to disable the MMU safely, which means using the identity map
page tables and executing code in the identity map region.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

[PATCH 3/3] arm: pm: add deep sleep support for LS1

[Chenhui Zhao]

On Fri, Sep 26, 2014 at 01:14:27PM +0100, Russell King - ARM Linux wrote:
> On Fri, Sep 26, 2014 at 07:25:03PM +0800, Chenhui Zhao wrote:
> > +static int ls1_start_deepsleep(unsigned long addr)
> > +{
> > +	ls1_do_deepsleep(addr);
> > +
> > +	return 0;
> > +}
> ...
> > +	cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
> 
> What's the point of this function?  Why can't ls1_do_deepsleep() just
> return zero?

Just leave space for adding C code in the future.

> 
> > +/*
> > + * r0: the physical entry address of SRAM code
> > + *
> > + */
> > +ENTRY(ls1_do_deepsleep)
> > +	mov	r13, r0
> > +
> > +	/* flush cache */
> > +	bl	v7_flush_dcache_all
> 
> Please explain the purpose of this call via a comment in the code.
> 
> The generic code will have saved the CPU state, and will have called
> flush_cache_louis() to flush the caches to the point of unification.
> 
> The only data which will have been loaded into the cache between that
> point is the stack for the return from __cpu_suspend_save, and
> speculative prefetches.
> 
> So, the only reason I can gather is that you need to flush data from
> lower levels of the cache below the point of unification.
> 

In deep sleep process, all caches will lost, so flush all caches to prevent
data loss.

> > +
> > +	/* disable cache, C bit in SCTLR */
> > +	mrc	p15, 0, r0, c1, c0, 0
> > +	bic	r0, r0, #(1 << 2)
> > +	mcr	p15, 0, r0, c1, c0, 0
> > +	isb
> > +
> > +	/* disable coherency, SMP bit in ACTLR */
> > +	mrc	p15, 0, r0, c1, c0, 1
> > +	bic	r0, r0, #(1 << 6)
> > +	mcr	p15, 0, r0, c1, c0, 1
> > +	isb
> > +	dsb
> > +
> > +	/* disable MMU, M bit in SCTLR */
> > +	mrc	p15, 0, r0, c1, c0, 0
> > +	bic	r0, r0, #1
> > +	mcr	p15, 0, r0, c1, c0, 0
> > +	isb
> > +
> > +	/* jump to sram code using physical address */
> > +	bx	r13
> 
> This looks extremely fragile.  You are running in virtual space, and you
> turn the MMU off.  You are reliant on the MMU still being on for the
> following instructions to already be in the pipeline.  That's not a
> very good assumption to make (we've made it in the past and it breaks
> every so often when things change, eg when the code is no longer laid
> out how we expect.)
> 
> You need to disable the MMU safely, which means using the identity map
> page tables and executing code in the identity map region.

Yes, the code will switch off MMU, and switch to physical address space.
On LS1021, the DDR memory located at the physical address space started from
0x80000000, the kernel space also started at 0x80000000 (CONFIG_PAGE_OFFSET = 0x80000000).
So the virtual address of kernel code is equal to the physical address.

Chenhui

[PATCH 3/3] arm: pm: add deep sleep support for LS1

[Russell King - ARM Linux]

On Sun, Sep 28, 2014 at 07:06:40PM +0800, Chenhui Zhao wrote:
> On Fri, Sep 26, 2014 at 01:14:27PM +0100, Russell King - ARM Linux wrote:
> > On Fri, Sep 26, 2014 at 07:25:03PM +0800, Chenhui Zhao wrote:
> > > +static int ls1_start_deepsleep(unsigned long addr)
> > > +{
> > > +	ls1_do_deepsleep(addr);
> > > +
> > > +	return 0;
> > > +}
> > ...
> > > +	cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
> > 
> > What's the point of this function?  Why can't ls1_do_deepsleep() just
> > return zero?
> 
> Just leave space for adding C code in the future.
> 
> > 
> > > +/*
> > > + * r0: the physical entry address of SRAM code
> > > + *
> > > + */
> > > +ENTRY(ls1_do_deepsleep)
> > > +	mov	r13, r0
> > > +
> > > +	/* flush cache */
> > > +	bl	v7_flush_dcache_all
> > 
> > Please explain the purpose of this call via a comment in the code.
> > 
> > The generic code will have saved the CPU state, and will have called
> > flush_cache_louis() to flush the caches to the point of unification.
> > 
> > The only data which will have been loaded into the cache between that
> > point is the stack for the return from __cpu_suspend_save, and
> > speculative prefetches.
> > 
> > So, the only reason I can gather is that you need to flush data from
> > lower levels of the cache below the point of unification.
> > 
> 
> In deep sleep process, all caches will lost, so flush all caches to prevent
> data loss.

You haven't answered my question.

> > > +
> > > +	/* disable cache, C bit in SCTLR */
> > > +	mrc	p15, 0, r0, c1, c0, 0
> > > +	bic	r0, r0, #(1 << 2)
> > > +	mcr	p15, 0, r0, c1, c0, 0
> > > +	isb
> > > +
> > > +	/* disable coherency, SMP bit in ACTLR */
> > > +	mrc	p15, 0, r0, c1, c0, 1
> > > +	bic	r0, r0, #(1 << 6)
> > > +	mcr	p15, 0, r0, c1, c0, 1
> > > +	isb
> > > +	dsb
> > > +
> > > +	/* disable MMU, M bit in SCTLR */
> > > +	mrc	p15, 0, r0, c1, c0, 0
> > > +	bic	r0, r0, #1
> > > +	mcr	p15, 0, r0, c1, c0, 0
> > > +	isb
> > > +
> > > +	/* jump to sram code using physical address */
> > > +	bx	r13
> > 
> > This looks extremely fragile.  You are running in virtual space, and you
> > turn the MMU off.  You are reliant on the MMU still being on for the
> > following instructions to already be in the pipeline.  That's not a
> > very good assumption to make (we've made it in the past and it breaks
> > every so often when things change, eg when the code is no longer laid
> > out how we expect.)
> > 
> > You need to disable the MMU safely, which means using the identity map
> > page tables and executing code in the identity map region.
> 
> Yes, the code will switch off MMU, and switch to physical address space.
> On LS1021, the DDR memory located at the physical address space started from
> 0x80000000, the kernel space also started at 0x80000000 (CONFIG_PAGE_OFFSET = 0x80000000).
> So the virtual address of kernel code is equal to the physical address.

You can't rely on that.

Sorry, NAK.

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[PATCH 3/3] arm: pm: add deep sleep support for LS1

[Chenhui Zhao]

On Sun, Sep 28, 2014 at 03:26:33PM +0100, Russell King - ARM Linux wrote:
> On Sun, Sep 28, 2014 at 07:06:40PM +0800, Chenhui Zhao wrote:
> > On Fri, Sep 26, 2014 at 01:14:27PM +0100, Russell King - ARM Linux wrote:
> > > On Fri, Sep 26, 2014 at 07:25:03PM +0800, Chenhui Zhao wrote:
> > > > +/*
> > > > + * r0: the physical entry address of SRAM code
> > > > + *
> > > > + */
> > > > +ENTRY(ls1_do_deepsleep)
> > > > +	mov	r13, r0
> > > > +
> > > > +	/* flush cache */
> > > > +	bl	v7_flush_dcache_all
> > > 
> > > Please explain the purpose of this call via a comment in the code.
> > > 
> > > The generic code will have saved the CPU state, and will have called
> > > flush_cache_louis() to flush the caches to the point of unification.
> > > 
> > > The only data which will have been loaded into the cache between that
> > > point is the stack for the return from __cpu_suspend_save, and
> > > speculative prefetches.
> > > 
> > > So, the only reason I can gather is that you need to flush data from
> > > lower levels of the cache below the point of unification.
> > > 
> > 
> > In deep sleep process, all caches will lost, so flush all caches to prevent
> > data loss.
> 
> You haven't answered my question.
> 

I want to flush L1 and L2 caches of Cortex-A7 in LS1021. However,
flush_cache_louis() only flushed L1 cache. Therefore, call
v7_flush_dcache_all() to flush L1 and L2 cache. 

> > > > +
> > > > +	/* disable cache, C bit in SCTLR */
> > > > +	mrc	p15, 0, r0, c1, c0, 0
> > > > +	bic	r0, r0, #(1 << 2)
> > > > +	mcr	p15, 0, r0, c1, c0, 0
> > > > +	isb
> > > > +
> > > > +	/* disable coherency, SMP bit in ACTLR */
> > > > +	mrc	p15, 0, r0, c1, c0, 1
> > > > +	bic	r0, r0, #(1 << 6)
> > > > +	mcr	p15, 0, r0, c1, c0, 1
> > > > +	isb
> > > > +	dsb
> > > > +
> > > > +	/* disable MMU, M bit in SCTLR */
> > > > +	mrc	p15, 0, r0, c1, c0, 0
> > > > +	bic	r0, r0, #1
> > > > +	mcr	p15, 0, r0, c1, c0, 0
> > > > +	isb
> > > > +
> > > > +	/* jump to sram code using physical address */
> > > > +	bx	r13
> > > 
> > > This looks extremely fragile.  You are running in virtual space, and you
> > > turn the MMU off.  You are reliant on the MMU still being on for the
> > > following instructions to already be in the pipeline.  That's not a
> > > very good assumption to make (we've made it in the past and it breaks
> > > every so often when things change, eg when the code is no longer laid
> > > out how we expect.)
> > > 
> > > You need to disable the MMU safely, which means using the identity map
> > > page tables and executing code in the identity map region.
> > 
> > Yes, the code will switch off MMU, and switch to physical address space.
> > On LS1021, the DDR memory located at the physical address space started from
> > 0x80000000, the kernel space also started at 0x80000000 (CONFIG_PAGE_OFFSET = 0x80000000).
> > So the virtual address of kernel code is equal to the physical address.
> 
> You can't rely on that.
> 
> Sorry, NAK.

I'll try to use a safer method to implement it.

Chenhui