From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/7] clk: sunxi: Specify number of child clocks for divs clocks
Date: Tue, 30 Sep 2014 17:40:43 +0200 [thread overview]
Message-ID: <20140930154043.GN4081@lukather> (raw)
In-Reply-To: <1411807795-6575-2-git-send-email-wens@csie.org>
On Sat, Sep 27, 2014 at 04:49:49PM +0800, Chen-Yu Tsai wrote:
> Currently sunxi_divs_clk_setup assumes the number of child clocks
> to be the same as the number of clock-output-names, and a maximum
> of SUNXI_DIVS_MAX_QTY child clocks.
>
> On sun6i, PLL6 only has 1 child clock, but the parent would be used
> as well, thereby also having it's own clock-output-names entry. This
> results in an extra bogus clock being registered.
Isn't PLL6 having two childs as well?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2014-09-30 15:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-27 8:49 [PATCH v2 0/6] clk: sun6i: Unify AHB1 clock and fix rate calculation Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 1/7] clk: sunxi: Specify number of child clocks for divs clocks Chen-Yu Tsai
2014-09-30 15:40 ` Maxime Ripard [this message]
2014-09-30 15:56 ` Chen-Yu Tsai
2014-10-03 14:05 ` Maxime Ripard
2014-09-27 8:49 ` [PATCH v2 2/7] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output Chen-Yu Tsai
2014-09-30 15:39 ` Maxime Ripard
2014-09-30 15:50 ` Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 3/7] ARM: sun6i: DT: Add PLL6 multiple outputs Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 4/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider Chen-Yu Tsai
2014-09-30 15:54 ` Maxime Ripard
2014-10-06 12:58 ` Chen-Yu Tsai
2014-10-06 13:44 ` Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 5/7] ARM: dts: sun6i: Unify ahb1 clock nodes Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 6/7] ARM: dts: sun8i: " Chen-Yu Tsai
2014-09-27 8:49 ` [PATCH v2 7/7] ARM: dts: sun6i: Add required ahb1 clock parent and rates for dma controller Chen-Yu Tsai
2014-09-30 15:55 ` Maxime Ripard
2014-10-09 3:01 ` Chen-Yu Tsai
2014-10-13 10:02 ` Maxime Ripard
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