[PATCH 6/7] arm64/kexec: Add core kexec support

Mark Rutland
2014-10-02T16:53:50Z

> > > I see that Geoff's patches flush dcaches for
> > > certain kexec stored pages using __flush_dcache_area()
> > > (in kexec_list_flush_cb()).
> > >
> > > arch/arm64/include/asm/cacheflush.h says following.
> > >
> > > * __flush_dcache_area(kaddr, size)
> > > *
> > > * Ensure that the data held in page is written back.
> > > * - kaddr - page address
> > > * - size - region size
> > >
> > > So looks like we are trying to write back anything which we will access
> > > after switching off MMU. If that's the case, I have two questions.
> > >
> > > - Why do we need to writeback that cacheline. After switching off MMU,
> > > will we not access same cacheline. I thought caches are VIPT and tag
> > > will still remain the same (but I might easily be wrong here).
> >
> > As I mention above, the initial cache flush by VA is to ensure that the
> > data is visible to the CPU once translation is disabled. I'm not sure I
> > follow your reasoning.
>
> I was assuming that even after we disable translations, cpu will still
> read data from dcache if it is available there. Looks like you are
> saying that once translation is disabled, data will be read from memory
> hence it is important to flush out dcache before disabling translation.
> Did I understand it right?

I believe you did.

When translation is disabled (i.e. SCTLR_ELx.M == 0), data accesses are
assigned Device-nGnRnE attributes regardless of whether the caches are
enabled (i.e. SCTLR_ELx.C == 1), and bypass the cache hierarchy. So
accesses to memory will go straight to PoC (essentially memory), and
won't hit in any cache.

However, instruction accesses are more complicated. They are always
assigned Normal memory attributes, and if the I-caches are enabled (i.e.
SCTLR_ELx.I == 1) they are cacheable regardless of whether translation
is enabled. So I-cache maintenance may be required when translation is
disabled.

Thanks,
Mark.