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From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC
Date: Wed, 22 Oct 2014 15:04:22 +0100	[thread overview]
Message-ID: <20141022140421.GL22642@leverpostej> (raw)
In-Reply-To: <1413985427-20918-6-git-send-email-ezequiel.garcia@free-electrons.com>

On Wed, Oct 22, 2014 at 02:43:45PM +0100, Ezequiel Garcia wrote:
> The Armada 375 SoC has a Cortex-A9 CPU, and so the PMU is available
> to be used. This commit enables it in the devicetree.
> 
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-375.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
> index de65714..f131cd2 100644
> --- a/arch/arm/boot/dts/armada-375.dtsi
> +++ b/arch/arm/boot/dts/armada-375.dtsi
> @@ -55,6 +55,11 @@
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a9-pmu";
> +		interrupts-extended = <&mpic 3>;
> +	};

Just to check - the interrupts from both CPUs are muxed into a single
line into the interrupt controller?

This isn't gonig to work at the moment -- the perf code will associate
this interrupt with CPU0 and you'll lose events on CPU1.

Hopefully there's a separate interrupt for CPU1?

Mark.

> +
>  	soc {
>  		compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
>  		#address-cells = <2>;
> -- 
> 2.1.0
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

  reply	other threads:[~2014-10-22 14:04 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-22 13:43 [PATCH 0/7] Armada 375/38x perf support, and a bonus irqchip driver simplification Ezequiel Garcia
2014-10-22 13:43 ` [PATCH 1/7] irqchip: armada-370-xp: Simplify interrupt map, mask and unmask Ezequiel Garcia
2014-10-31 16:36   ` Gregory CLEMENT
2014-11-04 15:11     ` Ezequiel Garcia
2014-11-10 17:09       ` Gregory CLEMENT
2014-10-22 13:43 ` [PATCH 2/7] irqchip: armada-370-xp: Initialize per cpu registers when CONFIG_SMP=N Ezequiel Garcia
2014-11-12 10:30   ` Gregory CLEMENT
2014-10-22 13:43 ` [PATCH 3/7] irqchip: armada-370-xp: Introduce a is_percpu_irq() helper for readability Ezequiel Garcia
2014-10-22 13:58   ` Mark Rutland
2014-10-22 15:14     ` Ezequiel Garcia
2014-10-22 13:43 ` [PATCH 4/7] irqchip: armada-370-xp: Enable Performance Counter interrupts Ezequiel Garcia
2014-10-22 13:43 ` [PATCH 5/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC Ezequiel Garcia
2014-10-22 14:04   ` Mark Rutland [this message]
2014-10-22 22:16     ` Ezequiel Garcia
2014-10-23  9:14       ` Thomas Petazzoni
2014-10-23 11:51         ` Ezequiel Garcia
2014-10-23 12:07           ` Thomas Petazzoni
2014-10-23 12:19             ` Ezequiel Garcia
2014-10-23 13:18             ` Mark Rutland
2014-10-31 16:23               ` Ezequiel Garcia
2014-10-23  9:41       ` Mark Rutland
2014-10-22 13:43 ` [PATCH 6/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC Ezequiel Garcia
2014-10-22 14:06   ` Mark Rutland
2014-10-22 22:18     ` Ezequiel Garcia
2014-10-22 13:43 ` [PATCH 7/7] ARM: mvebu: Enable perf support in mvebu_v7_defconfig Ezequiel Garcia
2014-10-22 14:11   ` Mark Rutland
2014-10-22 15:33     ` Ezequiel Garcia
2014-10-22 15:38       ` Mark Rutland
2014-11-09  5:23 ` [PATCH 0/7] Armada 375/38x perf support, and a bonus irqchip driver simplification Jason Cooper
2014-11-09  9:41   ` Thomas Petazzoni
2014-11-09 12:18     ` Ezequiel Garcia
2014-11-09 22:50       ` Jason Cooper
2014-11-23  0:45         ` Ezequiel Garcia

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