From: richardcochran@gmail.com (Richard Cochran)
To: linux-arm-kernel@lists.infradead.org
Subject: ARMADA 370 - Distributed Switch Architecture (dsa) - device tree
Date: Thu, 23 Oct 2014 10:32:02 +0200 [thread overview]
Message-ID: <20141023083202.GB4122@localhost.localdomain> (raw)
In-Reply-To: <543D2410.4060000@roeck-us.net>
On Tue, Oct 14, 2014 at 06:24:32AM -0700, Guenter Roeck wrote:
> I can not really tell if they are similar; I don't have the datasheet
> for the 6350/6351. The datasheet for the 6352 covers a couple of other
> switches, but not those two. The 6352 does support PTP; I can see that
> much in its datasheet. You could check if my 6352 driver works for you ;-).
(Sorry for the delay in replying.)
Here is my current set of definitions. Probably you can see whether
the 6352 is similar enough or not. I keep a text file with register
definitions, and a little tool to format the C-code output. If you
like this approach, we can add any other fields or bits you may need.
Using the macros, you can code like this.
u16 management, upstream = dsa_upstream_port(ds);
management = REG_READ(REG_GLOBAL2, SW_MANAGEMENT);
management |= RSVD_2_CPU;
REG_WRITE(REG_GLOBAL2, SW_MANAGEMENT, management);
REG_WRITE(REG_GLOBAL, MONITOR_DEST,
(upstream & CPU_DST_MASK) << CPU_DST_SHIFT);
That mostly eliminates the need for comment blocks explaining the
hardcoded numbers.
Thanks,
Richard
---
/* mv88e635x_reg.h
* Generated by regen.tcl on Tue Oct 14 19:39:45 CEST 2014
*/
#ifndef HAVE_MV88E635X_REGISTERS
#define HAVE_MV88E635X_REGISTERS
#define PORT_REGISTERS 0x0010
#define PORT_STATUS 0x0000
#define PHYSICAL_CONTROL 0x0001
#define JAMMING_CONTROL 0x0002
#define SWITCH_IDENTIFIER 0x0003
#define PORT_CONTROL 0x0004
#define PORT_CONTROL_1 0x0005
#define PORT_BASED_VLAN_MAP 0x0006
#define PORT_VLAN_ID_PRI 0x0007
#define PORT_CONTROL_2 0x0008
#define EGRESS_RATE_CTRL 0x0009
#define EGRESS_RATE_CTRL_2 0x000a
#define PORT_ASSOC_VECTOR 0x000b
#define PORT_ATU_CONTROL 0x000c
#define PRIORITY_OVERRIDE 0x000d
#define POLICY_CONTROL 0x000e
#define PORT_ETHERTYPE 0x000f
#define GLOBAL_1_REGISTERS 0x001b
#define GLOBAL_STATUS 0x0000
#define ATU_FID 0x0001
#define VTU_FID 0x0002
#define VTU_SID 0x0003
#define GLOBAL_CONTROL 0x0004
#define VTU_OPERATION 0x0005
#define VTU_VID 0x0006
#define VTU_DATA_PORTS_30 0x0007
#define VTU_DATA_PORTS_74 0x0008
#define VTU_DATA_PORTS_A8 0x0009
#define ATU_CONTROL 0x000a
#define ATU_OPERATION 0x000b
#define ATU_DATA 0x000c
#define ATU_MAC_01 0x000d
#define ATU_MAC_23 0x000e
#define ATU_MAC_45 0x000f
#define IEEE_TAG_PRIORITY 0x0018
#define IP_PRI_MAPPING 0x0019
#define MONITOR_DEST 0x001a
#define FREE_POOL 0x001b
#define GLOBAL_CONTROL_2 0x001c
#define STATS_OPERATION 0x001d
#define STATS_DATA_32 0x001e
#define STATS_DATA_10 0x001f
#define GLOBAL_2_REGISTERS 0x001c
#define INTERRUPT_SOURCE 0x0000
#define INTERRUPT_MASK 0x0001
#define MGMT_ENABLES_2X 0x0002
#define MGMT_ENABLES_0X 0x0003
#define FLOW_CONTROL_DELAYS 0x0004
#define SW_MANAGEMENT 0x0005
#define DEVICE_MAPPING 0x0006
#define TRUNK_MASK 0x0007
#define TRUNK_MAPPING 0x0008
#define INGRESS_RATE_CMD 0x0009
#define INGRESS_RATE_DATA 0x000a
#define CROSSPORT_VLAN_ADDR 0x000b
#define CROSSPORT_VLAN_DATA 0x000c
#define SWITCH_MAC 0x000d
#define ATU_STATS 0x000e
#define PRIORITY_OVERRIDES 0x000f
#define EEPROM_CMD 0x0014
#define EEPROM_DATA 0x0015
#define AVB_CMD 0x0016
#define AVB_DATA 0x0017
#define SMI_PHY_COMMAND 0x0018
#define SMI_PHY_DATA 0x0019
#define SCRATCH 0x001a
#define WATCH_DOG_CONTROL 0x001b
#define QOS_WEIGHTS 0x001c
#define PTP_PORT_REGISTERS 0x0000
#define PTP_PORT_CONFIG_0 0x0000
#define PTP_PORT_CONFIG_1 0x0001
#define PTP_PORT_CONFIG_2 0x0002
#define PTP_ARR0_STATUS 0x0008
#define PTP_ARR0_TIME_LOW 0x0009 /* Receive time stamp 0 [15:0] */
#define PTP_ARR0_TIME_HIGH 0x000a /* Receive time stamp 0 [31:16] */
#define PTP_ARR0_SEQID 0x000b /* Receive time stamp 0 sequence ID */
#define PTP_ARR1_STATUS 0x000c
#define PTP_ARR1_TIME_LOW 0x000d /* Receive time stamp 1 [15:0] */
#define PTP_ARR1_TIME_HIGH 0x000e /* Receive time stamp 1 [31:16] */
#define PTP_ARR1_SEQID 0x000f /* Receive time stamp 1 sequence ID */
#define PTP_DEP_STATUS 0x0010
#define PTP_DEP_TIME_LOW 0x0011 /* Transmit time stamp [15:0] */
#define PTP_DEP_TIME_HIGH 0x0012 /* Transmit time stamp [31:16] */
#define PTP_DEP_SEQID 0x0013 /* Transmit time stamp sequence ID */
#define PTP_PORT_DIS_CTRS 0x0015
#define TAI_GLOBAL_REGISTERS 0x000e
#define TAI_GLOBAL_CONFIG_0 0x0000
#define TSCLKPER 0x0001 /* Clock period in picoseconds */
#define TRIG_GEN_AMT_LOW 0x0002 /* Trig. generation amount [15:0] */
#define TRIG_GEN_AMT_HIGH 0x0003 /* Trig. generation amount [31:16] */
#define TRIG_CLK_COMP 0x0004 /* Addend in picoseconds */
#define TAI_GLOBAL_CONFIG_1 0x0005
#define TRIG_GEN_INT_STATUS 0x0008
#define EVENT_STATUS 0x0009
#define EVENT_TIME_LOW 0x000a
#define EVENT_TIME_HIGH 0x000b
#define PTP_TIME_LOW 0x000e
#define PTP_TIME_HIGH 0x000f
#define PTP_GLOBAL_REGISTERS 0x000f
#define PTP_ETHERTYPE 0x0000 /* PTP Ethertype */
#define MSG_ID_TS_EN 0x0001 /* Message ID time stamp enable */
#define TS_ARR_PTR 0x0002 /* Rx time stamp slot */
#define PTP_INT 0x0008 /* Per port PTP interrupt */
/* Bit definitions for the SWITCH_IDENTIFIER register */
#define PRODUCT_NUM_SHIFT (4) /* Product number or identifier */
#define PRODUCT_NUM_MASK (0xfff)
#define REV_IDENTIFIER_SHIFT (0)
#define REV_IDENTIFIER_MASK (0xf)
/* Bit definitions for the PORT_CONTROL register */
#define SA_FILTERING_SHIFT (14) /* Source address filter control */
#define SA_FILTERING_MASK (0x3)
#define EGRESS_MODE_SHIFT (12)
#define EGRESS_MODE_MASK (0x3)
#define HEADER_MODE (1<<11) /* Ingress/egress header mode */
#define IGMP_MLD_SNOOP (1<<10)
#define FRAME_MODE_SHIFT (8)
#define FRAME_MODE_MASK (0x3)
#define VLAN_TUNNEL (1<<7)
#define TAG_IF_BOTH (1<<6)
#define INITIAL_PRI_SHIFT (4)
#define INITIAL_PRI_MASK (0x3)
#define EGRESS_FLOODS_SHIFT (2)
#define EGRESS_FLOODS_MASK (0x3)
#define PORT_STATE_SHIFT (0)
#define PORT_STATE_MASK (0x3)
/* Bit definitions for the ATU_OPERATION register */
#define ATU_BUSY (1<<15) /* Address Translation Unit Busy */
#define ATU_OP_SHIFT (12) /* Address Translation Unit Opcode */
#define ATU_OP_MASK (0x7)
#define MAC_PRI_SHIFT (8) /* MAC Priority bits */
#define MAC_PRI_MASK (0x7)
#define AGEOUT_VIOLATION (1<<7)
#define MEMBER_VIOLATION (1<<6)
#define MISS_VIOLATION (1<<5)
#define ATUFULL_VIOLATION (1<<4)
/* Bit definitions for the ATU_DATA register */
#define TRUNK (1<<15) /* Trunk Mapped Address */
#define PORT_VEC_SHIFT (4) /* Port Vector */
#define PORT_VEC_MASK (0xff)
#define ENTRY_STATE_SHIFT (0) /* ATU Entry State */
#define ENTRY_STATE_MASK (0xf)
/* Bit definitions for the MONITOR_DEST register */
#define INGRESS_MON_DST_SHIFT (12) /* Ingress monitor destination */
#define INGRESS_MON_DST_MASK (0xf)
#define EGRESS_MON_DST_SHIFT (8) /* Egress monitor destination */
#define EGRESS_MON_DST_MASK (0xf)
#define CPU_DST_SHIFT (4) /* CPU destination port */
#define CPU_DST_MASK (0xf)
#define MIRROR_DST_SHIFT (0) /* Mirror destination port */
#define MIRROR_DST_MASK (0xf)
/* Bit definitions for the SW_MANAGEMENT register */
#define LOOPBACK_FILTER (1<<15)
#define FLOW_CTRL_MSG (1<<13)
#define FLOOD_BC (1<<12)
#define REMOVE_1P_TAG (1<<11)
#define ATU_AGE_INT_EN (1<<10)
#define TAG_FLOW_CONTROL (1<<9)
#define FORCE_FLOW_CTRL_PRI (1<<7)
#define FC_PRI_SHIFT (4) /* Flow control priority */
#define FC_PRI_MASK (0x7)
#define RSVD_2_CPU (1<<3)
#define MGMT_PRI_SHIFT (0)
#define MGMT_PRI_MASK (0x7)
/* Bit definitions for the AVB_CMD register */
#define AVB_BUSY (1<<15)
#define AVB_OP_SHIFT (12) /* AVB unit operation code */
#define AVB_OP_MASK (0x7)
#define AVB_PORT_SHIFT (8) /* Port index or 0xf for globals */
#define AVB_PORT_MASK (0xf)
#define AVB_BLOCK_SHIFT (5) /* Address block */
#define AVB_BLOCK_MASK (0x7)
#define AVB_ADDR_SHIFT (0)
#define AVB_ADDR_MASK (0x1f)
/* Bit definitions for the PTP_PORT_CONFIG_0 register */
#define TRANS_SPEC_SHIFT (12) /* Transport specific value */
#define TRANS_SPEC_MASK (0xf)
#define DIS_TSPEC_CHECK (1<<11) /* Disable transport check */
#define DIS_TS_OVERWRITE (1<<1) /* Disable time stamp overwriting */
#define DIS_PTP (1<<0) /* Disable time stamp logic */
/* Bit definitions for the PTP_PORT_CONFIG_1 register */
#define IP_JUMP_SHIFT (8) /* Internet Protocol jump */
#define IP_JUMP_MASK (0x3f)
#define ET_JUMP_SHIFT (0) /* Ethertype jump */
#define ET_JUMP_MASK (0x1f)
/* Bit definitions for the PTP_PORT_CONFIG_2 register */
#define PTP_DEP_INT_EN (1<<1) /* Transmit interrupt enable */
#define PTP_ARR_INT_EN (1<<0) /* Receive interrupt enable */
/* Bit definitions for the PTP_ARR0_STATUS register */
#define PTP_INT_STATUS_SHIFT (1) /* Time stamp interrupt status */
#define PTP_INT_STATUS_MASK (0x3)
#define PTP_TS_TIMEVALID (1<<0) /* Indicates time stamp valid */
/* Bit definitions for the PTP_PORT_DIS_CTRS register */
#define PTP_TS_DEPDISCTR_SHIFT (12) /* Tx event message discard count */
#define PTP_TS_DEPDISCTR_MASK (0xf)
#define PTP_NTS_DEPDISCTR_SHIFT (8) /* Tx general msg discard count */
#define PTP_NTS_DEPDISCTR_MASK (0xf)
#define PTP_TS_ARRDISCTR_SHIFT (4) /* Rx event message discard count */
#define PTP_TS_ARRDISCTR_MASK (0xf)
#define PTP_NTS_ARRDISCTR_SHIFT (0) /* Rx general msg discard count */
#define PTP_NTS_ARRDISCTR_MASK (0xf)
/* Bit definitions for the TAI_GLOBAL_CONFIG_0 register */
#define EVENT_CAP_OV (1<<15) /* Event capture overwrite */
#define EVENT_CTR_START (1<<14) /* Event counter start */
#define TRIG_GEN_INT_EN (1<<9) /* Trigger interrupt enable */
#define EVENT_CAP_INT_EN (1<<8) /* Event interrupt enable */
#define TIME_INC_DEC_EN (1<<3) /* Enable time adjustment */
#define MULTIPTP_SYNCMODE (1<<2) /* Multiple device sync mode */
#define TRIG_MODE (1<<1) /* Trigger Mode */
#define TRIG_GEN_REQ (1<<0) /* Trigger generation request */
/* Bit definitions for the TAI_GLOBAL_CONFIG_1 register */
#define PULSE_WIDTH_SHIFT (12) /* Pulse width in TSCLKPER units */
#define PULSE_WIDTH_MASK (0xf)
#define TIME_INC_DEC_OP (1<<11) /* Sign for TIME_INC_DEC_AMT */
#define TIME_INC_DEC_AMT_SHIFT (0) /* Time adjustment amount */
#define TIME_INC_DEC_AMT_MASK (0x7ff)
/* Bit definitions for the TRIG_GEN_INT_STATUS register */
#define TRIG_GEN_INT (1<<15) /* Trigger generation interrupt */
/* Bit definitions for the EVENT_STATUS register */
#define EVENT_INT (1<<15) /* Event capture interrupt */
#define EVENT_CAP_ERR (1<<9) /* Event capture error */
#define EVENT_CAP_VALID (1<<8) /* Event capture valid */
#define EVENT_CAP_CTR_SHIFT (0) /* Event capture counter */
#define EVENT_CAP_CTR_MASK (0xff)
/* Bit definitions for the MSG_ID_TS_EN register */
#define SYNC (1<<0)
#define DELAY_REQ (1<<1)
#define PDELAY_REQ (1<<2)
#define PDELAY_RESP (1<<3)
#define FOLLOW_UP (1<<8)
#define DELAY_RESP (1<<9)
#define PDELAY_RESP_FUP (1<<10)
#define ANNOUNCE (1<<11)
#define SIGNALING (1<<12)
#define MANAGEMENT (1<<13)
#endif
next prev parent reply other threads:[~2014-10-23 8:32 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-13 10:14 ARMADA 370 - Distributed Switch Architecture (dsa) - device tree post at twien.net
2014-10-13 11:19 ` Jason Cooper
2014-10-23 9:20 ` Thomas Petazzoni
2014-10-23 12:10 ` Jason Cooper
2014-10-23 12:57 ` post at twien.net
2014-10-23 14:05 ` Andrew Lunn
2014-10-23 14:19 ` post at twien.net
2014-10-13 13:19 ` Andrew Lunn
2014-10-13 18:25 ` Guenter Roeck
2014-10-14 6:05 ` post at twien.net
2014-10-14 13:30 ` Guenter Roeck
2014-10-14 11:35 ` Richard Cochran
2014-10-14 13:24 ` Guenter Roeck
2014-10-23 8:32 ` Richard Cochran [this message]
2014-10-14 2:08 ` Florian Fainelli
2014-10-14 11:14 ` post at twien.net
2014-10-14 16:14 ` Florian Fainelli
2014-10-15 13:42 ` post at twien.net
2014-10-15 13:47 ` Guenter Roeck
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