* [PATCH v7 01/12] clk: tegra: Implement memory-controller clock
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-14 1:53 ` Mike Turquette
2014-11-13 9:32 ` [PATCH v7 02/12] amba: Add Kconfig file Thierry Reding
` (11 subsequent siblings)
12 siblings, 1 reply; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The memory controller clock runs either at half or the same frequency as
the EMC clock.
Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Mike, as I said in the cover letter there are tight dependencies between the
patches in this series, so I'd like to get your Acked-by on this one so I can
take it through the Tegra tree along with the others.
Thanks,
Thierry
Changes in v4:
- use name and parent name parameters passed in when registering clock
Changes in v3:
- split registration into a separate function that can be reused for all
SoC generations, but pass in the name and parent parameters for
clarity as well as the register address (in case it ever changes) and
the EMC spin-lock since it isn't globally available
drivers/clk/tegra/clk-divider.c | 13 +++++++++++++
drivers/clk/tegra/clk-tegra114.c | 7 ++++++-
drivers/clk/tegra/clk-tegra124.c | 7 ++++++-
drivers/clk/tegra/clk-tegra20.c | 8 +++++++-
drivers/clk/tegra/clk-tegra30.c | 7 ++++++-
drivers/clk/tegra/clk.h | 2 ++
include/dt-bindings/clock/tegra114-car.h | 2 +-
include/dt-bindings/clock/tegra124-car.h | 2 +-
include/dt-bindings/clock/tegra20-car.h | 2 +-
9 files changed, 43 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 290f9c1a3749..59a5714dfe18 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -185,3 +185,16 @@ struct clk *tegra_clk_register_divider(const char *name,
return clk;
}
+
+static const struct clk_div_table mc_div_table[] = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 1 },
+ { .val = 0, .div = 0 },
+};
+
+struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
+ void __iomem *reg, spinlock_t *lock)
+{
+ return clk_register_divider_table(NULL, name, parent_name, 0, reg,
+ 16, 1, 0, mc_div_table, lock);
+}
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index f760f31d05c4..0b03d2cf7264 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -173,6 +173,7 @@ static DEFINE_SPINLOCK(pll_d_lock);
static DEFINE_SPINLOCK(pll_d2_lock);
static DEFINE_SPINLOCK(pll_u_lock);
static DEFINE_SPINLOCK(pll_re_lock);
+static DEFINE_SPINLOCK(emc_lock);
static struct div_nmp pllxc_nmp = {
.divm_shift = 0,
@@ -1228,7 +1229,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
ARRAY_SIZE(mux_pllmcp_clkm),
CLK_SET_RATE_NO_REPARENT,
clk_base + CLK_SOURCE_EMC,
- 29, 3, 0, NULL);
+ 29, 3, 0, &emc_lock);
+
+ clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+ &emc_lock);
+ clks[TEGRA114_CLK_MC] = clk;
for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
data = &tegra_periph_clk_list[i];
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index e3a85842ce0c..f5f9baca7bb6 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -132,6 +132,7 @@ static DEFINE_SPINLOCK(pll_d2_lock);
static DEFINE_SPINLOCK(pll_e_lock);
static DEFINE_SPINLOCK(pll_re_lock);
static DEFINE_SPINLOCK(pll_u_lock);
+static DEFINE_SPINLOCK(emc_lock);
/* possible OSC frequencies in Hz */
static unsigned long tegra124_input_freq[] = {
@@ -1127,7 +1128,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
ARRAY_SIZE(mux_pllmcp_clkm), 0,
clk_base + CLK_SOURCE_EMC,
- 29, 3, 0, NULL);
+ 29, 3, 0, &emc_lock);
+
+ clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+ &emc_lock);
+ clks[TEGRA124_CLK_MC] = clk;
/* cml0 */
clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index dace2b1b5ae6..41272dcc9e22 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -140,6 +140,8 @@ static struct cpu_clk_suspend_context {
static void __iomem *clk_base;
static void __iomem *pmc_base;
+static DEFINE_SPINLOCK(emc_lock);
+
#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \
TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
@@ -819,11 +821,15 @@ static void __init tegra20_periph_clk_init(void)
ARRAY_SIZE(mux_pllmcp_clkm),
CLK_SET_RATE_NO_REPARENT,
clk_base + CLK_SOURCE_EMC,
- 30, 2, 0, NULL);
+ 30, 2, 0, &emc_lock);
clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
57, periph_clk_enb_refcnt);
clks[TEGRA20_CLK_EMC] = clk;
+ clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+ &emc_lock);
+ clks[TEGRA20_CLK_MC] = clk;
+
/* dsi */
clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
48, periph_clk_enb_refcnt);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 5bbacd01094f..4b9d8bd3d0bf 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -177,6 +177,7 @@ static unsigned long input_freq;
static DEFINE_SPINLOCK(cml_lock);
static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(emc_lock);
#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \
@@ -1157,11 +1158,15 @@ static void __init tegra30_periph_clk_init(void)
ARRAY_SIZE(mux_pllmcp_clkm),
CLK_SET_RATE_NO_REPARENT,
clk_base + CLK_SOURCE_EMC,
- 30, 2, 0, NULL);
+ 30, 2, 0, &emc_lock);
clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
57, periph_clk_enb_refcnt);
clks[TEGRA30_CLK_EMC] = clk;
+ clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+ &emc_lock);
+ clks[TEGRA30_CLK_MC] = clk;
+
/* cml0 */
clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
0, 0, &cml_lock);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 16ec8d6bb87f..4e458aa8d45c 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -86,6 +86,8 @@ struct clk *tegra_clk_register_divider(const char *name,
const char *parent_name, void __iomem *reg,
unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
u8 frac_width, spinlock_t *lock);
+struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
+ void __iomem *reg, spinlock_t *lock);
/*
* Tegra PLL:
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index fc12621fb432..534c03f8ad72 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -49,7 +49,7 @@
#define TEGRA114_CLK_I2S0 30
/* 31 */
-/* 32 */
+#define TEGRA114_CLK_MC 32
/* 33 */
#define TEGRA114_CLK_APBDMA 34
/* 35 */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 6bac637fd635..af9bc9a3ddbc 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -48,7 +48,7 @@
#define TEGRA124_CLK_I2S0 30
/* 31 */
-/* 32 */
+#define TEGRA124_CLK_MC 32
/* 33 */
#define TEGRA124_CLK_APBDMA 34
/* 35 */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index 9406207cfac8..04500b243a4d 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -49,7 +49,7 @@
/* 30 */
#define TEGRA20_CLK_CACHE2 31
-#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_MC 32
#define TEGRA20_CLK_AHBDMA 33
#define TEGRA20_CLK_APBDMA 34
/* 35 */
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 01/12] clk: tegra: Implement memory-controller clock
2014-11-13 9:32 ` [PATCH v7 01/12] clk: tegra: Implement memory-controller clock Thierry Reding
@ 2014-11-14 1:53 ` Mike Turquette
2014-11-14 9:14 ` Thierry Reding
0 siblings, 1 reply; 18+ messages in thread
From: Mike Turquette @ 2014-11-14 1:53 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Thierry Reding (2014-11-13 01:32:26)
> From: Thierry Reding <treding@nvidia.com>
>
> The memory controller clock runs either at half or the same frequency as
> the EMC clock.
>
> Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Mike, as I said in the cover letter there are tight dependencies between the
> patches in this series, so I'd like to get your Acked-by on this one so I can
> take it through the Tegra tree along with the others.
Acked-by: Mike Turquette <mturquette@linaro.org>
>
> Thanks,
> Thierry
>
> Changes in v4:
> - use name and parent name parameters passed in when registering clock
>
> Changes in v3:
> - split registration into a separate function that can be reused for all
> SoC generations, but pass in the name and parent parameters for
> clarity as well as the register address (in case it ever changes) and
> the EMC spin-lock since it isn't globally available
>
> drivers/clk/tegra/clk-divider.c | 13 +++++++++++++
> drivers/clk/tegra/clk-tegra114.c | 7 ++++++-
> drivers/clk/tegra/clk-tegra124.c | 7 ++++++-
> drivers/clk/tegra/clk-tegra20.c | 8 +++++++-
> drivers/clk/tegra/clk-tegra30.c | 7 ++++++-
> drivers/clk/tegra/clk.h | 2 ++
> include/dt-bindings/clock/tegra114-car.h | 2 +-
> include/dt-bindings/clock/tegra124-car.h | 2 +-
> include/dt-bindings/clock/tegra20-car.h | 2 +-
> 9 files changed, 43 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> index 290f9c1a3749..59a5714dfe18 100644
> --- a/drivers/clk/tegra/clk-divider.c
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -185,3 +185,16 @@ struct clk *tegra_clk_register_divider(const char *name,
>
> return clk;
> }
> +
> +static const struct clk_div_table mc_div_table[] = {
> + { .val = 0, .div = 2 },
> + { .val = 1, .div = 1 },
> + { .val = 0, .div = 0 },
> +};
> +
> +struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
> + void __iomem *reg, spinlock_t *lock)
> +{
> + return clk_register_divider_table(NULL, name, parent_name, 0, reg,
> + 16, 1, 0, mc_div_table, lock);
> +}
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index f760f31d05c4..0b03d2cf7264 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -173,6 +173,7 @@ static DEFINE_SPINLOCK(pll_d_lock);
> static DEFINE_SPINLOCK(pll_d2_lock);
> static DEFINE_SPINLOCK(pll_u_lock);
> static DEFINE_SPINLOCK(pll_re_lock);
> +static DEFINE_SPINLOCK(emc_lock);
>
> static struct div_nmp pllxc_nmp = {
> .divm_shift = 0,
> @@ -1228,7 +1229,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
> ARRAY_SIZE(mux_pllmcp_clkm),
> CLK_SET_RATE_NO_REPARENT,
> clk_base + CLK_SOURCE_EMC,
> - 29, 3, 0, NULL);
> + 29, 3, 0, &emc_lock);
> +
> + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
> + &emc_lock);
> + clks[TEGRA114_CLK_MC] = clk;
>
> for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
> data = &tegra_periph_clk_list[i];
> diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
> index e3a85842ce0c..f5f9baca7bb6 100644
> --- a/drivers/clk/tegra/clk-tegra124.c
> +++ b/drivers/clk/tegra/clk-tegra124.c
> @@ -132,6 +132,7 @@ static DEFINE_SPINLOCK(pll_d2_lock);
> static DEFINE_SPINLOCK(pll_e_lock);
> static DEFINE_SPINLOCK(pll_re_lock);
> static DEFINE_SPINLOCK(pll_u_lock);
> +static DEFINE_SPINLOCK(emc_lock);
>
> /* possible OSC frequencies in Hz */
> static unsigned long tegra124_input_freq[] = {
> @@ -1127,7 +1128,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
> clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
> ARRAY_SIZE(mux_pllmcp_clkm), 0,
> clk_base + CLK_SOURCE_EMC,
> - 29, 3, 0, NULL);
> + 29, 3, 0, &emc_lock);
> +
> + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
> + &emc_lock);
> + clks[TEGRA124_CLK_MC] = clk;
>
> /* cml0 */
> clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index dace2b1b5ae6..41272dcc9e22 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -140,6 +140,8 @@ static struct cpu_clk_suspend_context {
> static void __iomem *clk_base;
> static void __iomem *pmc_base;
>
> +static DEFINE_SPINLOCK(emc_lock);
> +
> #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
> _clk_num, _gate_flags, _clk_id) \
> TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
> @@ -819,11 +821,15 @@ static void __init tegra20_periph_clk_init(void)
> ARRAY_SIZE(mux_pllmcp_clkm),
> CLK_SET_RATE_NO_REPARENT,
> clk_base + CLK_SOURCE_EMC,
> - 30, 2, 0, NULL);
> + 30, 2, 0, &emc_lock);
> clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
> 57, periph_clk_enb_refcnt);
> clks[TEGRA20_CLK_EMC] = clk;
>
> + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
> + &emc_lock);
> + clks[TEGRA20_CLK_MC] = clk;
> +
> /* dsi */
> clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
> 48, periph_clk_enb_refcnt);
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index 5bbacd01094f..4b9d8bd3d0bf 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -177,6 +177,7 @@ static unsigned long input_freq;
>
> static DEFINE_SPINLOCK(cml_lock);
> static DEFINE_SPINLOCK(pll_d_lock);
> +static DEFINE_SPINLOCK(emc_lock);
>
> #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
> _clk_num, _gate_flags, _clk_id) \
> @@ -1157,11 +1158,15 @@ static void __init tegra30_periph_clk_init(void)
> ARRAY_SIZE(mux_pllmcp_clkm),
> CLK_SET_RATE_NO_REPARENT,
> clk_base + CLK_SOURCE_EMC,
> - 30, 2, 0, NULL);
> + 30, 2, 0, &emc_lock);
> clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
> 57, periph_clk_enb_refcnt);
> clks[TEGRA30_CLK_EMC] = clk;
>
> + clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
> + &emc_lock);
> + clks[TEGRA30_CLK_MC] = clk;
> +
> /* cml0 */
> clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
> 0, 0, &cml_lock);
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 16ec8d6bb87f..4e458aa8d45c 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -86,6 +86,8 @@ struct clk *tegra_clk_register_divider(const char *name,
> const char *parent_name, void __iomem *reg,
> unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
> u8 frac_width, spinlock_t *lock);
> +struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
> + void __iomem *reg, spinlock_t *lock);
>
> /*
> * Tegra PLL:
> diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
> index fc12621fb432..534c03f8ad72 100644
> --- a/include/dt-bindings/clock/tegra114-car.h
> +++ b/include/dt-bindings/clock/tegra114-car.h
> @@ -49,7 +49,7 @@
> #define TEGRA114_CLK_I2S0 30
> /* 31 */
>
> -/* 32 */
> +#define TEGRA114_CLK_MC 32
> /* 33 */
> #define TEGRA114_CLK_APBDMA 34
> /* 35 */
> diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
> index 6bac637fd635..af9bc9a3ddbc 100644
> --- a/include/dt-bindings/clock/tegra124-car.h
> +++ b/include/dt-bindings/clock/tegra124-car.h
> @@ -48,7 +48,7 @@
> #define TEGRA124_CLK_I2S0 30
> /* 31 */
>
> -/* 32 */
> +#define TEGRA124_CLK_MC 32
> /* 33 */
> #define TEGRA124_CLK_APBDMA 34
> /* 35 */
> diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
> index 9406207cfac8..04500b243a4d 100644
> --- a/include/dt-bindings/clock/tegra20-car.h
> +++ b/include/dt-bindings/clock/tegra20-car.h
> @@ -49,7 +49,7 @@
> /* 30 */
> #define TEGRA20_CLK_CACHE2 31
>
> -#define TEGRA20_CLK_MEM 32
> +#define TEGRA20_CLK_MC 32
> #define TEGRA20_CLK_AHBDMA 33
> #define TEGRA20_CLK_APBDMA 34
> /* 35 */
> --
> 2.1.3
>
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v7 01/12] clk: tegra: Implement memory-controller clock
2014-11-14 1:53 ` Mike Turquette
@ 2014-11-14 9:14 ` Thierry Reding
0 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-14 9:14 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 13, 2014 at 05:53:56PM -0800, Mike Turquette wrote:
> Quoting Thierry Reding (2014-11-13 01:32:26)
> > From: Thierry Reding <treding@nvidia.com>
> >
> > The memory controller clock runs either at half or the same frequency as
> > the EMC clock.
> >
> > Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > Mike, as I said in the cover letter there are tight dependencies between the
> > patches in this series, so I'd like to get your Acked-by on this one so I can
> > take it through the Tegra tree along with the others.
>
> Acked-by: Mike Turquette <mturquette@linaro.org>
Thanks Mike,
Thierry
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v7 02/12] amba: Add Kconfig file
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
2014-11-13 9:32 ` [PATCH v7 01/12] clk: tegra: Implement memory-controller clock Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 03/12] ARM: tegra: Move AHB Kconfig to drivers/amba Thierry Reding
` (10 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Rather than duplicate the ARM_AMBA Kconfig symbol in both 32-bit and
64-bit ARM architectures, move the common definition to drivers/amba
where dependent drivers will be located.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Hi Russell, Will, Catalin,
As explained in the cover-letter there are tight dependencies between the
patches in this series, so for simplicity I'd like to take this patch through
the Tegra tree with your Acked-by.
Thanks,
Thierry
arch/arm/Kconfig | 3 ---
arch/arm64/Kconfig | 3 ---
drivers/amba/Kconfig | 2 ++
3 files changed, 2 insertions(+), 6 deletions(-)
create mode 100644 drivers/amba/Kconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9d580d0e89a9..21fbf144a9fd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1242,9 +1242,6 @@ source "arch/arm/common/Kconfig"
menu "Bus support"
-config ARM_AMBA
- bool
-
config ISA
bool
help
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 58b657e41410..fbb2a148add4 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -169,9 +169,6 @@ endmenu
menu "Bus support"
-config ARM_AMBA
- bool
-
config PCI
bool "PCI support"
help
diff --git a/drivers/amba/Kconfig b/drivers/amba/Kconfig
new file mode 100644
index 000000000000..d1cba6a9b3b8
--- /dev/null
+++ b/drivers/amba/Kconfig
@@ -0,0 +1,2 @@
+config ARM_AMBA
+ bool
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 03/12] ARM: tegra: Move AHB Kconfig to drivers/amba
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
2014-11-13 9:32 ` [PATCH v7 01/12] clk: tegra: Implement memory-controller clock Thierry Reding
2014-11-13 9:32 ` [PATCH v7 02/12] amba: Add Kconfig file Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 04/12] of: Add NVIDIA Tegra memory controller binding Thierry Reding
` (9 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
This will allow the Kconfig option to be shared among 32-bit and 64-bit
ARM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Hi Russell,
As explained in the cover-letter there are tight dependencies between the
patches in this series, so for simplicity I'd like to take this patch through
the Tegra tree with your Acked-by.
Thanks,
Thierry
Changes in v4:
- add precursory patch introducing drivers/amba/Kconfig, rebase on top
Changes in v3:
- select ARM_AMBA from ARCH_TEGRA to enable the TEGRA_AHB driver
arch/arm/mach-tegra/Kconfig | 9 +--------
drivers/Kconfig | 2 ++
drivers/amba/Kconfig | 12 ++++++++++++
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 095399618ca5..d0be9a1ef6b8 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,6 +2,7 @@ menuconfig ARCH_TEGRA
bool "NVIDIA Tegra" if ARCH_MULTI_V7
select ARCH_REQUIRE_GPIOLIB
select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
+ select ARM_AMBA
select ARM_GIC
select CLKSRC_MMIO
select HAVE_ARM_SCU if SMP
@@ -59,12 +60,4 @@ config ARCH_TEGRA_124_SOC
Support for NVIDIA Tegra T124 processor family, based on the
ARM CortexA15MP CPU
-config TEGRA_AHB
- bool "Enable AHB driver for NVIDIA Tegra SoCs"
- default y
- help
- Adds AHB configuration functionality for NVIDIA Tegra SoCs,
- which controls AHB bus master arbitration and some
- performance parameters(priority, prefech size).
-
endif
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 569ff7886dc3..694d5a70d6ce 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -1,5 +1,7 @@
menu "Device Drivers"
+source "drivers/amba/Kconfig"
+
source "drivers/base/Kconfig"
source "drivers/bus/Kconfig"
diff --git a/drivers/amba/Kconfig b/drivers/amba/Kconfig
index d1cba6a9b3b8..4a5c9d279059 100644
--- a/drivers/amba/Kconfig
+++ b/drivers/amba/Kconfig
@@ -1,2 +1,14 @@
config ARM_AMBA
bool
+
+if ARM_AMBA
+
+config TEGRA_AHB
+ bool "Enable AHB driver for NVIDIA Tegra SoCs"
+ default y if ARCH_TEGRA
+ help
+ Adds AHB configuration functionality for NVIDIA Tegra SoCs,
+ which controls AHB bus master arbitration and some performance
+ parameters (priority, prefetch size).
+
+endif
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 04/12] of: Add NVIDIA Tegra memory controller binding
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (2 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 03/12] ARM: tegra: Move AHB Kconfig to drivers/amba Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 06/12] ARM: tegra: Add memory controller support for Tegra30 Thierry Reding
` (8 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.
In addition, the memory controller implements an SMMU (IOMMU) which can
translate I/O virtual addresses to physical addresses for clients. This
is useful for scatter-gather operation on devices that don't support it
natively and for virtualization or process separation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- add missing clocks and clock-names properties
- add example
.../memory-controllers/nvidia,tegra-mc.txt | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
new file mode 100644
index 000000000000..f3db93c85eea
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
@@ -0,0 +1,36 @@
+NVIDIA Tegra Memory Controller device tree bindings
+===================================================
+
+Required properties:
+- compatible: Should be "nvidia,tegra<chip>-mc"
+- reg: Physical base address and length of the controller's registers.
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - mc: the module's clock input
+- interrupts: The interrupt outputs from the controller.
+- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
+ the SWGROUP of the master.
+
+This device implements an IOMMU that complies with the generic IOMMU binding.
+See ../iommu/iommu.txt for details.
+
+Example:
+--------
+
+ mc: memory-controller at 0,70019000 {
+ compatible = "nvidia,tegra124-mc";
+ reg = <0x0 0x70019000 0x0 0x1000>;
+ clocks = <&tegra_car TEGRA124_CLK_MC>;
+ clock-names = "mc";
+
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <1>;
+ };
+
+ sdhci at 0,700b0000 {
+ compatible = "nvidia,tegra124-sdhci";
+ ...
+ iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
+ };
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 06/12] ARM: tegra: Add memory controller support for Tegra30
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (3 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 04/12] of: Add NVIDIA Tegra memory controller binding Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 07/12] ARM: tegra: Add memory controller support for Tegra114 Thierry Reding
` (7 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Collapses the old memory-controller and IOMMU device tree nodes into a
single node to more accurately describe the hardware.
While this is an incompatible change there are no users of the IOMMU on
Tegra, even though a driver has existed for some time.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra30.dtsi | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index b270b9e3d455..0d20058afe9d 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -615,23 +615,15 @@
clock-names = "pclk", "clk32k_in";
};
- memory-controller at 7000f000 {
+ mc: memory-controller at 7000f000 {
compatible = "nvidia,tegra30-mc";
- reg = <0x7000f000 0x010
- 0x7000f03c 0x1b4
- 0x7000f200 0x028
- 0x7000f284 0x17c>;
+ reg = <0x7000f000 0x400>;
+ clocks = <&tegra_car TEGRA30_CLK_MC>;
+ clock-names = "mc";
+
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- };
- iommu at 7000f010 {
- compatible = "nvidia,tegra30-smmu";
- reg = <0x7000f010 0x02c
- 0x7000f1f0 0x010
- 0x7000f228 0x05c>;
- nvidia,#asids = <4>; /* # of ASIDs */
- dma-window = <0 0x40000000>; /* IOVA start & length */
- nvidia,ahb = <&ahb>;
+ #iommu-cells = <1>;
};
fuse at 7000f800 {
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 07/12] ARM: tegra: Add memory controller support for Tegra114
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (4 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 06/12] ARM: tegra: Add memory controller support for Tegra30 Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 08/12] ARM: tegra: Add memory controller support for Tegra124 Thierry Reding
` (6 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Add the device tree node for the memory controller found on Tegra114
SoCs. The memory controller integrates an IOMMU (called SMMU) as well as
various knobs to tweak memory accesses by the various clients.
The old IOMMU device tree node is collapsed into the memory controller
node to more accurately describe the hardware. While this change is
incompatible, the IOMMU driver has never had any users so the change is
not going to cause any breakage.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra114.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 222f3b3f4dd5..e22eeca0979a 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -498,15 +498,15 @@
reset-names = "fuse";
};
- iommu at 70019010 {
- compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
- reg = <0x70019010 0x02c
- 0x700191f0 0x010
- 0x70019228 0x074>;
- nvidia,#asids = <4>;
- dma-window = <0 0x40000000>;
- nvidia,swgroups = <0x18659fe>;
- nvidia,ahb = <&ahb>;
+ mc: memory-controller at 70019000 {
+ compatible = "nvidia,tegra114-mc";
+ reg = <0x70019000 0x1000>;
+ clocks = <&tegra_car TEGRA114_CLK_MC>;
+ clock-names = "mc";
+
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <1>;
};
ahub at 70080000 {
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 08/12] ARM: tegra: Add memory controller support for Tegra124
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (5 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 07/12] ARM: tegra: Add memory controller support for Tegra114 Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 09/12] ARM: tegra: Enable IOMMU for display controllers on Tegra30 Thierry Reding
` (5 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Add the memory controller and wire up the interrupt that is used to
report errors. Provide a reference to the memory controller clock and
mark the device as being an IOMMU by adding an #iommu-cells property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra124.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index dde226e87356..29b60074bafa 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -553,6 +553,17 @@
reset-names = "fuse";
};
+ mc: memory-controller at 0,70019000 {
+ compatible = "nvidia,tegra124-mc";
+ reg = <0x0 0x70019000 0x0 0x1000>;
+ clocks = <&tegra_car TEGRA124_CLK_MC>;
+ clock-names = "mc";
+
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <1>;
+ };
+
sata at 0,70020000 {
compatible = "nvidia,tegra124-ahci";
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 09/12] ARM: tegra: Enable IOMMU for display controllers on Tegra30
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (6 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 08/12] ARM: tegra: Add memory controller support for Tegra124 Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 10/12] ARM: tegra: Enable IOMMU for display controllers on Tegra114 Thierry Reding
` (4 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Add iommus properties to the device tree nodes for the two display
controllers found on Tegra30. This will allow the display controllers to
map physically non-contiguous buffers to I/O virtual contiguous address
spaces so that they can be used for scan-out.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra30.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 0d20058afe9d..99475f6e76a3 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,5 +1,6 @@
#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/memory/tegra30-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -166,6 +167,8 @@
resets = <&tegra_car 27>;
reset-names = "dc";
+ iommus = <&mc TEGRA_SWGROUP_DC>;
+
nvidia,head = <0>;
rgb {
@@ -183,6 +186,8 @@
resets = <&tegra_car 26>;
reset-names = "dc";
+ iommus = <&mc TEGRA_SWGROUP_DCB>;
+
nvidia,head = <1>;
rgb {
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 10/12] ARM: tegra: Enable IOMMU for display controllers on Tegra114
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (7 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 09/12] ARM: tegra: Enable IOMMU for display controllers on Tegra30 Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 11/12] ARM: tegra: Enable IOMMU for display controllers on Tegra124 Thierry Reding
` (3 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Add iommus properties to the device tree nodes for the two display
controllers found on Tegra114. This will allow the display controllers
to map physically non-contiguous buffers to I/O virtual contiguous
address spaces so that they can be used for scan-out.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra114.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index e22eeca0979a..4296b5398bf5 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,5 +1,6 @@
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/memory/tegra114-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -50,6 +51,8 @@
resets = <&tegra_car 27>;
reset-names = "dc";
+ iommus = <&mc TEGRA_SWGROUP_DC>;
+
nvidia,head = <0>;
rgb {
@@ -67,6 +70,8 @@
resets = <&tegra_car 26>;
reset-names = "dc";
+ iommus = <&mc TEGRA_SWGROUP_DCB>;
+
nvidia,head = <1>;
rgb {
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 11/12] ARM: tegra: Enable IOMMU for display controllers on Tegra124
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (8 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 10/12] ARM: tegra: Enable IOMMU for display controllers on Tegra114 Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 9:32 ` [PATCH v7 12/12] memory: tegra: Add Tegra132 support Thierry Reding
` (2 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Add iommus properties to the device tree nodes for the two display
controllers found on Tegra124. This will allow the display controllers
to map physically non-contiguous buffers to I/O virtual contiguous
address spaces so that they can be used for scan-out.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/tegra124.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 29b60074bafa..4be06c6ea0c8 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,5 +1,6 @@
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/memory/tegra124-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -103,6 +104,8 @@
resets = <&tegra_car 27>;
reset-names = "dc";
+ iommus = <&mc TEGRA_SWGROUP_DC>;
+
nvidia,head = <0>;
};
@@ -116,6 +119,8 @@
resets = <&tegra_car 26>;
reset-names = "dc";
+ iommus = <&mc TEGRA_SWGROUP_DCB>;
+
nvidia,head = <1>;
};
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 12/12] memory: tegra: Add Tegra132 support
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (9 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 11/12] ARM: tegra: Enable IOMMU for display controllers on Tegra124 Thierry Reding
@ 2014-11-13 9:32 ` Thierry Reding
2014-11-13 10:12 ` [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Arnd Bergmann
[not found] ` <1415871157-21968-6-git-send-email-thierry.reding@gmail.com>
12 siblings, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 9:32 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v7:
- update help text
drivers/iommu/Kconfig | 2 +-
drivers/memory/tegra/Makefile | 1 +
drivers/memory/tegra/mc.c | 3 +++
drivers/memory/tegra/mc.h | 4 ++++
drivers/memory/tegra/tegra124.c | 33 +++++++++++++++++++++++++++++++++
5 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 30f0e61341c5..11518808417d 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -183,7 +183,7 @@ config TEGRA_IOMMU_SMMU
select IOMMU_API
help
This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
- SoCs (Tegra30 up to Tegra124).
+ SoCs (Tegra30 up to Tegra132).
config EXYNOS_IOMMU
bool "Exynos IOMMU Support"
diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile
index 0d9f497b786c..9d4f4319b527 100644
--- a/drivers/memory/tegra/Makefile
+++ b/drivers/memory/tegra/Makefile
@@ -3,5 +3,6 @@ tegra-mc-y := mc.o
tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
+tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index fe3c44e7e1d1..9b7c1645fd59 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -58,6 +58,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
#ifdef CONFIG_ARCH_TEGRA_124_SOC
{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
#endif
+#ifdef CONFIG_ARCH_TEGRA_132_SOC
+ { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
+#endif
{ }
};
MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index 28b1528f4fa0..f714c309b960 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -50,4 +50,8 @@ extern const struct tegra_mc_soc tegra114_mc_soc;
extern const struct tegra_mc_soc tegra124_mc_soc;
#endif
+#ifdef CONFIG_ARCH_TEGRA_132_SOC
+extern const struct tegra_mc_soc tegra132_mc_soc;
+#endif
+
#endif /* MEMORY_TEGRA_MC_H */
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 278d40b854c1..ccd19d83ee91 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -993,3 +993,36 @@ const struct tegra_mc_soc tegra124_mc_soc = {
.smmu = &tegra124_smmu_soc,
};
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
+
+#ifdef CONFIG_ARCH_TEGRA_132_SOC
+static void tegra132_flush_dcache(struct page *page, unsigned long offset,
+ size_t size)
+{
+ void *virt = page_address(page) + offset;
+
+ __flush_dcache_area(virt, size);
+}
+
+static const struct tegra_smmu_ops tegra132_smmu_ops = {
+ .flush_dcache = tegra132_flush_dcache,
+};
+
+static const struct tegra_smmu_soc tegra132_smmu_soc = {
+ .clients = tegra124_mc_clients,
+ .num_clients = ARRAY_SIZE(tegra124_mc_clients),
+ .swgroups = tegra124_swgroups,
+ .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
+ .supports_round_robin_arbitration = true,
+ .supports_request_limit = true,
+ .num_asids = 128,
+ .ops = &tegra132_smmu_ops,
+};
+
+const struct tegra_mc_soc tegra132_mc_soc = {
+ .clients = tegra124_mc_clients,
+ .num_clients = ARRAY_SIZE(tegra124_mc_clients),
+ .num_address_bits = 34,
+ .atom_size = 32,
+ .smmu = &tegra132_smmu_soc,
+};
+#endif /* CONFIG_ARCH_TEGRA_132_SOC */
--
2.1.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support
2014-11-13 9:32 [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Thierry Reding
` (10 preceding siblings ...)
2014-11-13 9:32 ` [PATCH v7 12/12] memory: tegra: Add Tegra132 support Thierry Reding
@ 2014-11-13 10:12 ` Arnd Bergmann
2014-11-13 10:40 ` Mikko Perttunen
2014-11-13 11:16 ` Thierry Reding
[not found] ` <1415871157-21968-6-git-send-email-thierry.reding@gmail.com>
12 siblings, 2 replies; 18+ messages in thread
From: Arnd Bergmann @ 2014-11-13 10:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 13 November 2014 10:32:25 Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> This is the sixth installment in the Tegra IOMMU and memory controller
> support series. This version addresses the final outstanding comments from
> Olof about using proper Kconfig symbols to track the dependencies. It also
> splits up the driver into one part that implements the memory controller
> only and a second part that implements the SMMU. This plays nicely with
> the new Kconfig options introduced.
>
> Patch 1 is a preparatory patch that exposes the memory controller clock.
>
> Patches 2 and 3 is a pair of precursory patches needed to make this all
> work on 64-bit ARM in the future.
>
> The device tree binding for the Tegra memory controller is added in patch
> 4 and patch 5 is the bulk of the series that move the existing memory
> controller and IOMMU drivers into the new unified driver that supports
> Tegra30, Tegra114 and Tegra124.
I just noticed that patch 5 has never made it into my inbox in any of the
submissions. Did it get filtered by the mailing list?
Arnd
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support
2014-11-13 10:12 ` [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Arnd Bergmann
@ 2014-11-13 10:40 ` Mikko Perttunen
2014-11-13 11:16 ` Thierry Reding
1 sibling, 0 replies; 18+ messages in thread
From: Mikko Perttunen @ 2014-11-13 10:40 UTC (permalink / raw)
To: linux-arm-kernel
On 11/13/2014 12:12 PM, Arnd Bergmann wrote:
> On Thursday 13 November 2014 10:32:25 Thierry Reding wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> This is the sixth installment in the Tegra IOMMU and memory controller
>> support series. This version addresses the final outstanding comments from
>> Olof about using proper Kconfig symbols to track the dependencies. It also
>> splits up the driver into one part that implements the memory controller
>> only and a second part that implements the SMMU. This plays nicely with
>> the new Kconfig options introduced.
>>
>> Patch 1 is a preparatory patch that exposes the memory controller clock.
>>
>> Patches 2 and 3 is a pair of precursory patches needed to make this all
>> work on 64-bit ARM in the future.
>>
>> The device tree binding for the Tegra memory controller is added in patch
>> 4 and patch 5 is the bulk of the series that move the existing memory
>> controller and IOMMU drivers into the new unified driver that supports
>> Tegra30, Tegra114 and Tegra124.
>
> I just noticed that patch 5 has never made it into my inbox in any of the
> submissions. Did it get filtered by the mailing list?
I have received patch 5 just fine through linux-tegra. The patch is
rather long though, so something filtering it wouldn't be that surprising.
>
> Arnd
Mikko
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support
2014-11-13 10:12 ` [PATCH v7 00/12] NVIDIA Tegra memory controller and IOMMU support Arnd Bergmann
2014-11-13 10:40 ` Mikko Perttunen
@ 2014-11-13 11:16 ` Thierry Reding
1 sibling, 0 replies; 18+ messages in thread
From: Thierry Reding @ 2014-11-13 11:16 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 13, 2014 at 11:12:20AM +0100, Arnd Bergmann wrote:
> On Thursday 13 November 2014 10:32:25 Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > This is the sixth installment in the Tegra IOMMU and memory controller
> > support series. This version addresses the final outstanding comments from
> > Olof about using proper Kconfig symbols to track the dependencies. It also
> > splits up the driver into one part that implements the memory controller
> > only and a second part that implements the SMMU. This plays nicely with
> > the new Kconfig options introduced.
> >
> > Patch 1 is a preparatory patch that exposes the memory controller clock.
> >
> > Patches 2 and 3 is a pair of precursory patches needed to make this all
> > work on 64-bit ARM in the future.
> >
> > The device tree binding for the Tegra memory controller is added in patch
> > 4 and patch 5 is the bulk of the series that move the existing memory
> > controller and IOMMU drivers into the new unified driver that supports
> > Tegra30, Tegra114 and Tegra124.
>
> I just noticed that patch 5 has never made it into my inbox in any of the
> submissions. Did it get filtered by the mailing list?
Yes, linux-arm-kernel says it needs moderator approval. Do you want me
to bounce it to you directly?
Thierry
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^ permalink raw reply [flat|nested] 18+ messages in thread
[parent not found: <1415871157-21968-6-git-send-email-thierry.reding@gmail.com>]
* [PATCH v7 05/12] memory: Add NVIDIA Tegra memory controller support
[not found] ` <1415871157-21968-6-git-send-email-thierry.reding@gmail.com>
@ 2014-11-17 13:47 ` Joerg Roedel
0 siblings, 0 replies; 18+ messages in thread
From: Joerg Roedel @ 2014-11-17 13:47 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 13, 2014 at 10:32:30AM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The memory controller on NVIDIA Tegra exposes various knobs that can be
> used to tune the behaviour of the clients attached to it.
>
> Currently this driver sets up the latency allowance registers to the HW
> defaults. Eventually an API should be exported by this driver (via a
> custom API or a generic subsystem) to allow clients to register latency
> requirements.
>
> This driver also registers an IOMMU (SMMU) that's implemented by the
> memory controller. It is supported on Tegra30, Tegra114 and Tegra124
> currently. Tegra20 has a GART instead.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Hi Joerg,
>
> As I mentioned in the cover-letter, I would like to take this whole series
> through the Tegra tree to simplify dependency handling. Can I have your
> Acked-by on this patch?
Sure!
> drivers/iommu/Kconfig | 12 +-
> drivers/iommu/tegra-smmu.c | 1601 ++++++++++--------------------
> drivers/memory/Kconfig | 12 +-
> drivers/memory/Makefile | 3 +-
> drivers/memory/tegra/Kconfig | 7 +
> drivers/memory/tegra/Makefile | 7 +
> drivers/memory/tegra/mc.c | 301 ++++++
> drivers/memory/tegra/mc.h | 53 +
> drivers/memory/tegra/tegra114.c | 948 ++++++++++++++++++
> drivers/memory/tegra/tegra124.c | 995 +++++++++++++++++++
> drivers/memory/tegra/tegra30.c | 970 ++++++++++++++++++
> drivers/memory/tegra30-mc.c | 377 -------
> include/dt-bindings/memory/tegra114-mc.h | 25 +
> include/dt-bindings/memory/tegra124-mc.h | 31 +
> include/dt-bindings/memory/tegra30-mc.h | 24 +
> include/soc/tegra/mc.h | 107 ++
> 16 files changed, 3992 insertions(+), 1481 deletions(-)
Acked-by: Joerg Roedel <jroedel@suse.de>
^ permalink raw reply [flat|nested] 18+ messages in thread