some question about TCR setting

[mark.rutland@arm.com (Mark Rutland)]

On Mon, Nov 17, 2014 at 01:03:06PM +0000, Russell King - ARM Linux wrote:
> On Mon, Nov 17, 2014 at 12:09:52PM +0000, Mark Rutland wrote:
> > On Sun, Nov 16, 2014 at 04:52:11PM +0000, Russell King - ARM Linux wrote:
> > > The access type is included on the bus along with the address and other
> > > attributes.  This includes whether it's sharable, and the cache attributes.
> > > A MMU page walker may be implemented such that it is capable of accessing
> > > L2 cache.
> > 
> > Or L1, depending on the implementation of the memory system. The logic
> > which walks the page tables is essentially another coherent observer, so
> > it doesn't necessarily matter precisely where it is attached.
> ...
> > To further this point, provided the TCR is programmed with the same
> > attributes the kernel uses to access the page tables, no cache
> > maintenance is necessary, as the CPU(s) and page table walker(s) are
> > coherent.
> 
> That depends on the implementation - whether the MMU page table walker
> can read from the L1 cache.  If you were correct in all cases, we could
> get rid of:
> 
>         ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
> 
> in proc-v7-2level.S - but obviously we think that ARMv7 is unable to read
> from L1 when walking the page tables.
> 
> > This is what we do for ARMv7 and arm64.
> 
> From the code, it looks like we don't for ARMv7.

My bad, I was assuming ARMv7 with the multiprocessor extensions rather
than baseline ARMv7.

Thanks,
Mark,