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From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs
Date: Thu, 27 Nov 2014 22:51:00 +0000	[thread overview]
Message-ID: <20141127225100.GA3840@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <1416224909-4290-1-git-send-email-m.szyprowski@samsung.com>

On Mon, Nov 17, 2014 at 12:48:22PM +0100, Marek Szyprowski wrote:
> This is an updated patchset, which intends to add support for L2 cache
> on Exynos4 SoCs on boards running under secure firmware, which requires
> certain initialization steps to be done with help of firmware, as
> selected registers are writable only from secure mode.
> 
> First four patches extend existing support for secure write in L2C driver
> to account for design of secure firmware running on Exynos. Namely:
>  1) direct read access to certain registers is needed on Exynos, because
>     secure firmware calls set several registers at once,
>  2) not all boards are running secure firmware, so .write_sec callback
>     needs to be installed in Exynos firmware ops initialization code,
>  3) write access to {DATA,TAG}_LATENCY_CTRL registers fron non-secure world
>     is not allowed and so must use l2c_write_sec as well,
>  4) on certain boards, default value of prefetch register is incorrect
>     and must be overridden at L2C initialization.
> For boards running with firmware that provides access to individual
> L2C registers this series should introduce no functional changes. However
> since the driver is widely used on other platforms I'd like to kindly ask
> any interested people for testing.
> 
> Further three patches add implementation of .write_sec and .configure
> callbacks for Exynos secure firmware and necessary DT nodes to enable
> L2 cache.
> 
> Changes in this version tested on Exynos4412-based TRATS2 and OdroidU3+
> boards (both with secure firmware). There should be no functional change
> for Exynos boards running without secure firmware. I do not have access
> to affected non-Exynos boards, so I could not test on them.

So, I applied this series, and now I get a conflicts between my tree and
arm-soc for:

arch/arm/mach-exynos/firmware.c
arch/arm/mach-exynos/sleep.S

So, I'm going to un-stage the exynos bits, and we'll have to work out
some way to handle those.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

  parent reply	other threads:[~2014-11-27 22:51 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-17 11:48 [PATCH v9 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Marek Szyprowski
2014-11-17 11:48 ` [PATCH v9 1/7] ARM: l2c: Refactor the driver to use commit-like interface Marek Szyprowski
2014-11-17 11:48 ` [PATCH v9 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C Marek Szyprowski
2014-11-17 11:48 ` [PATCH v9 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL Marek Szyprowski
2014-11-17 11:48 ` [PATCH v9 4/7] ARM: l2c: Add support for overriding prefetch settings Marek Szyprowski
2014-11-17 11:48 ` [PATCH v9 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Marek Szyprowski
2014-11-17 11:48 ` [PATCH v9 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume Marek Szyprowski
2014-11-17 11:48 ` [PATCH v9 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller Marek Szyprowski
2014-11-27 22:51 ` Russell King - ARM Linux [this message]
2014-11-28  8:55   ` [PATCH v9 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Marek Szyprowski
2014-11-28 11:11     ` Arnd Bergmann
2014-12-03 16:03       ` Russell King - ARM Linux
2014-12-03 20:26         ` Arnd Bergmann
  -- strict thread matches above, loose matches on Subject: below --
2014-11-17 11:47 Marek Szyprowski

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