[PATCH 0/5] irqchip: kill the GIC routable domain

[PATCH 0/5] irqchip: kill the GIC routable domain

[Marc Zyngier]

After my series removing the gic_arch_extn hack, I figured that the
next step was to expunge the GIC driver of the routable domain horror.

There is a few reasons for this:

- The allocation of interrupts in this domain is fairly similar to
  what we do for MSI (see the GICv2m driver), and stacked domains have
  proved to be a fitting solution.

- The current description in DT is currently entierely inaccurate, and
  as we already broke it for the OMAP WUGEN block, we might as well do
  it again for the TI crossbar.

- The way crossbar, WUGEN and GIC interract is quite complex (this is
  effectively a stack of three interrupt controllers with interesting
  exceptions and braindead routing), and stacked domains are the right
  abstraction for that.

- Other platforms (Freescale Vybrid) are starting to come up with the
  same type of things, and it'd be good to avoid them following the
  same broken model.

- It removes a few lines from the code base so it can't completely be
  a bad idea!

So this patch series does exactly that: make the crossbar a stacked
interrupt controller that only takes care of setting up the routing,
fix the DTs to represent the actual HW, and remove a bit of the
craziness from the GIC code.

As for the previous series:

- I haven't been able to test this at all, I don't have access to the
  HW. TI people, please test and post fixes, as I expect I introduced
  a few bugs.

- This actively *breaks* existing setups. If you boot a new kernel
  with an old DT, interrupt routing *will* be broken. Old kernels on a
  new DT won't boot either! You've been warned. This really outline
  the necessity of actually describing the HW in device trees...

As for the patches, they are on top of 3.18-rc7 + tip/irq/irqdomain-arm +
the gic_arch_extn removal series.

I've pushed the code to:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die

Comments welcome,

	 M.

Marc Zyngier (5):
  genirq: Add irqchip_set_wake_parent
  irqchip: crossbar: convert dra7 crossbar to stacked domains
  DT: update ti,irq-crossbar binding
  irqchip: GIC: get rid of routable domain
  DT: arm,gic: kill arm,routable-irqs

 Documentation/devicetree/bindings/arm/gic.txt      |   6 -
 .../devicetree/bindings/arm/omap/crossbar.txt      |  18 +-
 arch/arm/boot/dts/dra7.dtsi                        |  10 +-
 arch/arm/boot/dts/dra72x.dtsi                      |   3 +-
 arch/arm/boot/dts/dra74x.dtsi                      |   5 +-
 arch/arm/mach-omap2/omap4-common.c                 |   4 -
 drivers/irqchip/irq-crossbar.c                     | 202 ++++++++++++---------
 drivers/irqchip/irq-gic.c                          |  59 +-----
 include/linux/irq.h                                |   1 +
 include/linux/irqchip/arm-gic.h                    |   6 -
 include/linux/irqchip/irq-crossbar.h               |  11 --
 kernel/irq/chip.c                                  |  16 ++
 12 files changed, 153 insertions(+), 188 deletions(-)
 delete mode 100644 include/linux/irqchip/irq-crossbar.h

-- 
2.1.3

[PATCH 1/5] genirq: Add irqchip_set_wake_parent

[Marc Zyngier]

This proves to be usefull with stacked domains.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 include/linux/irq.h |  1 +
 kernel/irq/chip.c   | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 8badf34..7de85b8 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -459,6 +459,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
 extern int irq_chip_set_affinity_parent(struct irq_data *data,
 					const struct cpumask *dest,
 					bool force);
+extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
 #endif
 
 static inline void irq_chip_write_msi_msg(struct irq_data *data,
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 6f1c7a5..96c190b 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
 
 	return -ENOSYS;
 }
+
+/**
+ * irq_chip_set_wake - Set/reset wake-up on the parent interrupt
+ * @data:	Pointer to interrupt specific data
+ * @on:		Whether to set or reset the wake-up capability of this irq
+ *
+ * Conditional, as the underlying parent chip might not implement it.
+ */
+int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
+{
+	data = data->parent_data;
+	if (data->chip->irq_set_wake)
+		return data->chip->irq_set_wake(data, on);
+
+	return -ENOSYS;
+}
 #endif
 
 /**
-- 
2.1.3

[PATCH 2/5] irqchip: crossbar: convert dra7 crossbar to stacked domains

[Marc Zyngier]

Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.

Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.

Unfortunately, as the DT bindings failed to acknoledge the fact
that this is actually yet another interrupt controller (the
third, actually), we have yet another breakage. Oh well.

Full untested, will crash and burn, blah blah blah.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/boot/dts/dra7.dtsi          |  10 +-
 arch/arm/boot/dts/dra72x.dtsi        |   3 +-
 arch/arm/boot/dts/dra74x.dtsi        |   5 +-
 arch/arm/mach-omap2/omap4-common.c   |   4 -
 drivers/irqchip/irq-crossbar.c       | 202 ++++++++++++++++++++---------------
 include/linux/irqchip/irq-crossbar.h |  11 --
 6 files changed, 126 insertions(+), 109 deletions(-)
 delete mode 100644 include/linux/irqchip/irq-crossbar.h

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 49ad4b3..43509e9 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -13,7 +13,6 @@
 #include "skeleton.dtsi"
 
 #define MAX_SOURCES 400
-#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
 
 / {
 	#address-cells = <1>;
@@ -49,7 +48,6 @@
 		compatible = "arm,cortex-a15-gic";
 		interrupt-controller;
 		#interrupt-cells = <3>;
-		arm,routable-irqs = <192>;
 		reg = <0x48211000 0x1000>,
 		      <0x48212000 0x1000>,
 		      <0x48214000 0x2000>,
@@ -93,8 +91,8 @@
 		ti,hwmods = "l3_main_1", "l3_main_2";
 		reg = <0x44000000 0x1000000>,
 		      <0x45000000 0x1000>;
-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
+		interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
 		prm: prm at 4ae06000 {
 			compatible = "ti,dra7-prm";
@@ -1265,9 +1263,11 @@
 			status = "disabled";
 		};
 
-		crossbar_mpu: crossbar at 4a020000 {
+		crossbar_mpu: crossbar at 4a002a48 {
 			compatible = "ti,irq-crossbar";
 			reg = <0x4a002a48 0x130>;
+			interrupt-controller;
+			interrupt-parent = <&wakeupgen>;
 			ti,max-irqs = <160>;
 			ti,max-crossbar-sources = <MAX_SOURCES>;
 			ti,reg-size = <2>;
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index e5a3d23..f7fb0d0 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -25,6 +25,7 @@
 
 	pmu {
 		compatible = "arm,cortex-a15-pmu";
-		interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wakeupgen>;
+		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 3be544c..7e0d3a6 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -41,7 +41,8 @@
 
 	pmu {
 		compatible = "arm,cortex-a15-pmu";
-		interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wakeupgen>;
+		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 	};
 };
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 0465448..021ceb5 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,7 +22,6 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
-#include <linux/irqchip/irq-crossbar.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
 #include <linux/genalloc.h>
@@ -274,8 +273,5 @@ void __init omap_gic_of_init(void)
 	WARN_ON(!twd_base);
 
 skip_errata_init:
-#ifdef CONFIG_IRQ_CROSSBAR
-	irqcrossbar_init();
-#endif
 	irqchip_init();
 }
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index bbbaf5d..b44915a 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -11,11 +11,12 @@
  */
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/slab.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/irqchip/irq-crossbar.h>
+
+#include "irqchip.h"
 
 #define IRQ_FREE	-1
 #define IRQ_RESERVED	-2
@@ -33,6 +34,7 @@
  * @write: register write function pointer
  */
 struct crossbar_device {
+	raw_spinlock_t lock;
 	uint int_max;
 	uint safe_map;
 	uint max_crossbar_sources;
@@ -44,72 +46,97 @@ struct crossbar_device {
 
 static struct crossbar_device *cb;
 
-static inline void crossbar_writel(int irq_no, int cb_no)
+static void crossbar_writel(int irq_no, int cb_no)
 {
 	writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
 }
 
-static inline void crossbar_writew(int irq_no, int cb_no)
+static void crossbar_writew(int irq_no, int cb_no)
 {
 	writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
 }
 
-static inline void crossbar_writeb(int irq_no, int cb_no)
+static void crossbar_writeb(int irq_no, int cb_no)
 {
 	writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
 }
 
-static inline int get_prev_map_irq(int cb_no)
-{
-	int i;
-
-	for (i = cb->int_max - 1; i >= 0; i--)
-		if (cb->irq_map[i] == cb_no)
-			return i;
-
-	return -ENODEV;
-}
+static struct irq_chip crossbar_chip = {
+	.name		= "CBAR",
+	.irq_eoi	= irq_chip_eoi_parent,
+	.irq_mask	= irq_chip_mask_parent,
+	.irq_unmask	= irq_chip_unmask_parent,
+	.irq_retrigger	= irq_chip_retrigger_hierarchy,
+	.irq_set_wake	= irq_chip_set_wake_parent,
+};
 
-static inline int allocate_free_irq(int cb_no)
+static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
+			    irq_hw_number_t hwirq)
 {
+	struct of_phandle_args args;
 	int i;
+	int err;
 
+	raw_spin_lock(&cb->lock);
 	for (i = cb->int_max - 1; i >= 0; i--) {
 		if (cb->irq_map[i] == IRQ_FREE) {
-			cb->irq_map[i] = cb_no;
-			return i;
+			cb->irq_map[i] = hwirq;
+			break;
 		}
 	}
+	raw_spin_unlock(&cb->lock);
 
-	return -ENODEV;
-}
+	if (i < 0)
+		return -ENODEV;
 
-static inline bool needs_crossbar_write(irq_hw_number_t hw)
-{
-	int cb_no;
+	args.np = domain->parent->of_node;
+	args.args_count = 3;
+	args.args[0] = 0;	/* SPI */
+	args.args[1] = i;
+	args.args[2] = IRQ_TYPE_LEVEL_HIGH;
 
-	if (hw > GIC_IRQ_START) {
-		cb_no = cb->irq_map[hw - GIC_IRQ_START];
-		if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
-			return true;
-	}
+	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
+	if (err)
+		cb->irq_map[i] = IRQ_FREE;
+	else
+		cb->write(hwirq, i);
 
-	return false;
+	return err;
 }
 
-static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
-			       irq_hw_number_t hw)
+static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
+				 unsigned int nr_irqs, void *data)
 {
-	if (needs_crossbar_write(hw))
-		cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
+	struct of_phandle_args *args = data;
+	irq_hw_number_t hwirq;
+	int i;
+
+	if (args->args_count != 3)
+		return -EINVAL;	/* Not GIC compliant */
+	if (args->args[0] != 0)
+		return -EINVAL;	/* No PPI should point to this domain */
+
+	hwirq = args->args[1];
+	if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
+		return -EINVAL;	/* Can't deal with this */
+
+	for (i = 0; i < nr_irqs; i++) {
+		int err = allocate_gic_irq(d, virq + i, hwirq + i);
+		if (err)
+			return err;
+
+		irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
+					      &crossbar_chip, NULL);
+	}
 
 	return 0;
 }
 
 /**
- * crossbar_domain_unmap - unmap a crossbar<->irq connection
+ * crossbar_domain_free - unmap/free a crossbar<->irq connection
  * @d: domain of irq to unmap
- * @irq: virq number
+ * @virq: virq number
+ * @nr_irqs: number of irqs to free
  *
  * We do not maintain a use count of total number of map/unmap
  * calls for a particular irq to find out if a irq can be really
@@ -117,14 +144,19 @@ static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
  * after which irq is anyways unusable. So an explicit map has to be called
  * after that.
  */
-static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
+static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
+				 unsigned int nr_irqs)
 {
-	irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
+	int i;
 
-	if (needs_crossbar_write(hw)) {
-		cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
-		cb->write(hw - GIC_IRQ_START, cb->safe_map);
+	raw_spin_lock(&cb->lock);
+	for (i = 0; i < nr_irqs; i++) {
+		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
+		irq_domain_reset_irq_data(d);
+		cb->irq_map[d->hwirq] = IRQ_FREE;
+		cb->write(d->hwirq, cb->safe_map);
 	}
+	raw_spin_unlock(&cb->lock);
 }
 
 static int crossbar_domain_xlate(struct irq_domain *d,
@@ -133,44 +165,22 @@ static int crossbar_domain_xlate(struct irq_domain *d,
 				 unsigned long *out_hwirq,
 				 unsigned int *out_type)
 {
-	int ret;
-	int req_num = intspec[1];
-	int direct_map_num;
-
-	if (req_num >= cb->max_crossbar_sources) {
-		direct_map_num = req_num - cb->max_crossbar_sources;
-		if (direct_map_num < cb->int_max) {
-			ret = cb->irq_map[direct_map_num];
-			if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
-				/* We use the interrupt num as h/w irq num */
-				ret = direct_map_num;
-				goto found;
-			}
-		}
-
-		pr_err("%s: requested crossbar number %d > max %d\n",
-		       __func__, req_num, cb->max_crossbar_sources);
-		return -EINVAL;
-	}
-
-	ret = get_prev_map_irq(req_num);
-	if (ret >= 0)
-		goto found;
-
-	ret = allocate_free_irq(req_num);
-
-	if (ret < 0)
-		return ret;
-
-found:
-	*out_hwirq = ret + GIC_IRQ_START;
+	if (d->of_node != controller)
+		return -EINVAL;	/* Shouldn't happen, really... */
+	if (intsize != 3)
+		return -EINVAL;	/* Not GIC compliant */
+	if (intspec[0] != 0)
+		return -EINVAL;	/* No PPI should point to this domain */
+
+	*out_hwirq = intspec[1];
+	*out_type = intspec[2];
 	return 0;
 }
 
-static const struct irq_domain_ops routable_irq_domain_ops = {
-	.map = crossbar_domain_map,
-	.unmap = crossbar_domain_unmap,
-	.xlate = crossbar_domain_xlate
+static const struct irq_domain_ops crossbar_domain_ops = {
+	.alloc	= crossbar_domain_alloc,
+	.free	= crossbar_domain_free,
+	.xlate	= crossbar_domain_xlate,
 };
 
 static int __init crossbar_of_init(struct device_node *node)
@@ -293,7 +303,8 @@ static int __init crossbar_of_init(struct device_node *node)
 		cb->write(i, cb->safe_map);
 	}
 
-	register_routable_domain_ops(&routable_irq_domain_ops);
+	raw_spin_lock_init(&cb->lock);
+
 	return 0;
 
 err_reg_offset:
@@ -309,18 +320,37 @@ err_cb:
 	return ret;
 }
 
-static const struct of_device_id crossbar_match[] __initconst = {
-	{ .compatible = "ti,irq-crossbar" },
-	{}
-};
-
-int __init irqcrossbar_init(void)
+static int __init irqcrossbar_init(struct device_node *node,
+				   struct device_node *parent)
 {
-	struct device_node *np;
-	np = of_find_matching_node(NULL, crossbar_match);
-	if (!np)
+	struct irq_domain *parent_domain, *domain;
+	int err;
+
+	if (!parent) {
+		pr_err("%s: no parent, giving up\n", node->full_name);
 		return -ENODEV;
+	}
+
+	parent_domain = irq_find_host(parent);
+	if (!parent_domain) {
+		pr_err("%s: unable to obtain parent domain\n", node->full_name);
+		return -ENXIO;
+	}
+
+	err = crossbar_of_init(node);
+	if (err)
+		return err;
+
+	domain = irq_domain_add_hierarchy(parent_domain, 0,
+					  cb->max_crossbar_sources,
+					  node, &crossbar_domain_ops,
+					  NULL);
+	if (!domain) {
+		pr_err("%s: failed to allocated domain\n", node->full_name);
+		return -ENOMEM;
+	}
 
-	crossbar_of_init(np);
 	return 0;
 }
+
+IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irqcrossbar", irqcrossbar_init);
diff --git a/include/linux/irqchip/irq-crossbar.h b/include/linux/irqchip/irq-crossbar.h
deleted file mode 100644
index e5537b8..0000000
--- a/include/linux/irqchip/irq-crossbar.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- *  drivers/irqchip/irq-crossbar.h
- *
- *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-int irqcrossbar_init(void);
-- 
2.1.3

[PATCH 3/5] DT: update ti,irq-crossbar binding

[Marc Zyngier]

Make it look like a real interrupt controller.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 .../devicetree/bindings/arm/omap/crossbar.txt          | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db3..a9b28d7 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
 Required properties:
 - compatible : Should be "ti,irq-crossbar"
 - reg: Base address and the size of the crossbar registers.
-- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
 - ti,reg-size: Size of a individual register in bytes. Every individual
 	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
   when the interrupt controller irq is unused (when not provided, default is 0)
 
 Examples:
-		crossbar_mpu: @4a020000 {
+		crossbar_mpu: crossbar at 4a002a48 {
 			compatible = "ti,irq-crossbar";
 			reg = <0x4a002a48 0x130>;
 			ti,max-irqs = <160>;
 			ti,max-crossbar-sources = <400>;
 			ti,reg-size = <2>;
-			ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
+			ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
 			ti,irqs-skip = <10 133 139 140>;
 		};
 
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details.
 
 An interrupt consumer on an SoC using crossbar will use:
 	interrupts = <GIC_SPI request_number interrupt_level>
-When the request number is between 0 to that described by
-"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
-request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
-quirky hardware mapping direct to GIC.
 
 Example:
 	device_x at 0x4a023000 {
@@ -55,9 +53,3 @@ Example:
 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		...
 	};
-
-	device_y at 0x4a033000 {
-		/* Direct mapped GIC SPI 1 used */
-		interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
-		...
-	};
-- 
2.1.3

[PATCH 4/5] irqchip: GIC: get rid of routable domain

[Marc Zyngier]

The only user of the so called "routable domain" functionnality
now being fixed, let's clean up the GIC.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 drivers/irqchip/irq-gic.c       | 59 ++++-------------------------------------
 include/linux/irqchip/arm-gic.h |  6 -----
 2 files changed, 5 insertions(+), 60 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 540f23c..ad2ca50 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -742,15 +742,12 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 		irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
 				    handle_fasteoi_irq, NULL, NULL);
 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
-		gic_routable_irq_domain_ops->map(d, irq, hw);
 	}
 	return 0;
 }
 
 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
 {
-	gic_routable_irq_domain_ops->unmap(d, irq);
 }
 
 static int gic_irq_domain_xlate(struct irq_domain *d,
@@ -769,16 +766,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
 	*out_hwirq = intspec[1] + 16;
 
 	/* For SPIs, we need to add 16 more to get the GIC irq ID number */
-	if (!intspec[0]) {
-		ret = gic_routable_irq_domain_ops->xlate(d, controller,
-							 intspec,
-							 intsize,
-							 out_hwirq,
-							 out_type);
-
-		if (IS_ERR_VALUE(ret))
-			return ret;
-	}
+	if (!intspec[0])
+		*out_hwirq += 16;
 
 	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
 
@@ -835,37 +824,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
 	.xlate = gic_irq_domain_xlate,
 };
 
-/* Default functions for routable irq domain */
-static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
-			      irq_hw_number_t hw)
-{
-	return 0;
-}
-
-static void gic_routable_irq_domain_unmap(struct irq_domain *d,
-					  unsigned int irq)
-{
-}
-
-static int gic_routable_irq_domain_xlate(struct irq_domain *d,
-				struct device_node *controller,
-				const u32 *intspec, unsigned int intsize,
-				unsigned long *out_hwirq,
-				unsigned int *out_type)
-{
-	*out_hwirq += 16;
-	return 0;
-}
-
-static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
-	.map = gic_routable_irq_domain_map,
-	.unmap = gic_routable_irq_domain_unmap,
-	.xlate = gic_routable_irq_domain_xlate,
-};
-
-const struct irq_domain_ops *gic_routable_irq_domain_ops =
-					&gic_default_routable_irq_domain_ops;
-
 void gic_set_irqchip_flags(unsigned long flags)
 {
 	gic_chip.flags |= flags;
@@ -878,7 +836,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 	irq_hw_number_t hwirq_base;
 	struct gic_chip_data *gic;
 	int gic_irqs, irq_base, i;
-	int nr_routable_irqs;
 
 	BUG_ON(gic_nr >= MAX_GIC_NR);
 
@@ -934,15 +891,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 	gic->gic_irqs = gic_irqs;
 
 	if (node) {		/* DT case */
-		const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops;
-
-		if (!of_property_read_u32(node, "arm,routable-irqs",
-					  &nr_routable_irqs)) {
-			ops = &gic_irq_domain_ops;
-			gic_irqs = nr_routable_irqs;
-		}
-
-		gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
+		gic->domain = irq_domain_add_linear(node, gic_irqs,
+						    &gic_irq_domain_hierarchy_ops,
+						    gic);
 	} else {		/* Non-DT case */
 		/*
 		 * For primary GICs, skip over SGIs.
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 4637213..9de976b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -114,11 +114,5 @@ int gic_get_cpu_id(unsigned int cpu);
 void gic_migrate_target(unsigned int new_cpu_id);
 unsigned long gic_get_sgir_physaddr(void);
 
-extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
-static inline void __init register_routable_domain_ops
-					(const struct irq_domain_ops *ops)
-{
-	gic_routable_irq_domain_ops = ops;
-}
 #endif /* __ASSEMBLY */
 #endif
-- 
2.1.3

[PATCH 5/5] DT: arm,gic: kill arm,routable-irqs

[Marc Zyngier]

Nobody will regret it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 Documentation/devicetree/bindings/arm/gic.txt | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 375147e..c279ef9 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -51,11 +51,6 @@ Optional
   regions, used when the GIC doesn't have banked registers. The offset is
   cpu-offset * cpu-nr.
 
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
-		  connected from the peripherals, but are routed dynamically
-		  by a crossbar/multiplexer preceding the GIC. The GIC irq
-		  input line is assigned dynamically when the corresponding
-		  peripheral's crossbar line is mapped.
 Example:
 
 	intc: interrupt-controller at fff11000 {
@@ -63,7 +58,6 @@ Example:
 		#interrupt-cells = <3>;
 		#address-cells = <1>;
 		interrupt-controller;
-		arm,routable-irqs = <160>;
 		reg = <0xfff11000 0x1000>,
 		      <0xfff10100 0x100>;
 	};
-- 
2.1.3

[PATCH 1/5] genirq: Add irqchip_set_wake_parent

[Stefan Agner]

Thanks for the CC, interesting read for me, good preparation for the
next revision of my Vybrid patchset. One thing I stumbled upon below:

On 2014-12-06 14:46, Marc Zyngier wrote:
> This proves to be usefull with stacked domains.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  include/linux/irq.h |  1 +
>  kernel/irq/chip.c   | 16 ++++++++++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/include/linux/irq.h b/include/linux/irq.h
> index 8badf34..7de85b8 100644
> --- a/include/linux/irq.h
> +++ b/include/linux/irq.h
> @@ -459,6 +459,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
>  extern int irq_chip_set_affinity_parent(struct irq_data *data,
>  					const struct cpumask *dest,
>  					bool force);
> +extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
>  #endif
>  
>  static inline void irq_chip_write_msi_msg(struct irq_data *data,
> diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
> index 6f1c7a5..96c190b 100644
> --- a/kernel/irq/chip.c
> +++ b/kernel/irq/chip.c
> @@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
>  
>  	return -ENOSYS;
>  }
> +
> +/**
> + * irq_chip_set_wake - Set/reset wake-up on the parent interrupt
                       ^
This should be irq_chip_set_wake_parent I guess...


> + * @data:	Pointer to interrupt specific data
> + * @on:		Whether to set or reset the wake-up capability of this irq
> + *
> + * Conditional, as the underlying parent chip might not implement it.
> + */
> +int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
> +{
> +	data = data->parent_data;
> +	if (data->chip->irq_set_wake)
> +		return data->chip->irq_set_wake(data, on);
> +
> +	return -ENOSYS;
> +}
>  #endif
>  
>  /**

[PATCH 0/5] irqchip: kill the GIC routable domain

[Nishanth Menon]

On 13:46-20141206, Marc Zyngier wrote:
> After my series removing the gic_arch_extn hack, I figured that the
> next step was to expunge the GIC driver of the routable domain horror.
> 
> There is a few reasons for this:
> 
> - The allocation of interrupts in this domain is fairly similar to
>   what we do for MSI (see the GICv2m driver), and stacked domains have
>   proved to be a fitting solution.
> 
> - The current description in DT is currently entierely inaccurate, and
>   as we already broke it for the OMAP WUGEN block, we might as well do
>   it again for the TI crossbar.
> 
> - The way crossbar, WUGEN and GIC interract is quite complex (this is
>   effectively a stack of three interrupt controllers with interesting
>   exceptions and braindead routing), and stacked domains are the right
>   abstraction for that.
> 
> - Other platforms (Freescale Vybrid) are starting to come up with the
>   same type of things, and it'd be good to avoid them following the
>   same broken model.
> 
> - It removes a few lines from the code base so it can't completely be
>   a bad idea!
> 
> So this patch series does exactly that: make the crossbar a stacked
> interrupt controller that only takes care of setting up the routing,
> fix the DTs to represent the actual HW, and remove a bit of the
> craziness from the GIC code.
> 
> As for the previous series:
> 
> - I haven't been able to test this at all, I don't have access to the
>   HW. TI people, please test and post fixes, as I expect I introduced
>   a few bugs.
> 
> - This actively *breaks* existing setups. If you boot a new kernel
>   with an old DT, interrupt routing *will* be broken. Old kernels on a
>   new DT won't boot either! You've been warned. This really outline
>   the necessity of actually describing the HW in device trees...
> 
> As for the patches, they are on top of 3.18-rc7 + tip/irq/irqdomain-arm +
> the gic_arch_extn removal series.
> 
> I've pushed the code to:
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die
> 
> Comments welcome,
> 
> 	 M.
> 
> Marc Zyngier (5):
>   genirq: Add irqchip_set_wake_parent
>   irqchip: crossbar: convert dra7 crossbar to stacked domains
>   DT: update ti,irq-crossbar binding
>   irqchip: GIC: get rid of routable domain
>   DT: arm,gic: kill arm,routable-irqs
> 
>  Documentation/devicetree/bindings/arm/gic.txt      |   6 -
>  .../devicetree/bindings/arm/omap/crossbar.txt      |  18 +-
>  arch/arm/boot/dts/dra7.dtsi                        |  10 +-
>  arch/arm/boot/dts/dra72x.dtsi                      |   3 +-
>  arch/arm/boot/dts/dra74x.dtsi                      |   5 +-
>  arch/arm/mach-omap2/omap4-common.c                 |   4 -
>  drivers/irqchip/irq-crossbar.c                     | 202 ++++++++++++---------
>  drivers/irqchip/irq-gic.c                          |  59 +-----
>  include/linux/irq.h                                |   1 +
>  include/linux/irqchip/arm-gic.h                    |   6 -
>  include/linux/irqchip/irq-crossbar.h               |  11 --
>  kernel/irq/chip.c                                  |  16 ++
>  12 files changed, 153 insertions(+), 188 deletions(-)
>  delete mode 100644 include/linux/irqchip/irq-crossbar.h
> 
> -- 
> 2.1.3
> 

	Patches are available here:
	https://patchwork.kernel.org/patch/5449231/
	https://patchwork.kernel.org/patch/5449241/
	https://patchwork.kernel.org/patch/5449271/
	https://patchwork.kernel.org/patch/5449261/
	https://patchwork.kernel.org/patch/5449251/

-- 
Regards,
Nishanth Menon

[PATCH 0/5] irqchip: kill the GIC routable domain

[Nishanth Menon]

Marc,

On 11:16-20141207, Nishanth Menon wrote:
> On 13:46-20141206, Marc Zyngier wrote:
> > After my series removing the gic_arch_extn hack, I figured that the
> > next step was to expunge the GIC driver of the routable domain horror.
> > 
> > There is a few reasons for this:
> > 
> > - The allocation of interrupts in this domain is fairly similar to
> >   what we do for MSI (see the GICv2m driver), and stacked domains have
> >   proved to be a fitting solution.
> > 
> > - The current description in DT is currently entierely inaccurate, and
> >   as we already broke it for the OMAP WUGEN block, we might as well do
> >   it again for the TI crossbar.
> > 
> > - The way crossbar, WUGEN and GIC interract is quite complex (this is
> >   effectively a stack of three interrupt controllers with interesting
> >   exceptions and braindead routing), and stacked domains are the right
> >   abstraction for that.
> > 
> > - Other platforms (Freescale Vybrid) are starting to come up with the
> >   same type of things, and it'd be good to avoid them following the
> >   same broken model.
> > 
> > - It removes a few lines from the code base so it can't completely be
> >   a bad idea!
> > 
> > So this patch series does exactly that: make the crossbar a stacked
> > interrupt controller that only takes care of setting up the routing,
> > fix the DTs to represent the actual HW, and remove a bit of the
> > craziness from the GIC code.
> > 
> > As for the previous series:
> > 
> > - I haven't been able to test this at all, I don't have access to the
> >   HW. TI people, please test and post fixes, as I expect I introduced
> >   a few bugs.
> > 
> > - This actively *breaks* existing setups. If you boot a new kernel
> >   with an old DT, interrupt routing *will* be broken. Old kernels on a
> >   new DT won't boot either! You've been warned. This really outline
> >   the necessity of actually describing the HW in device trees...
> > 
> > As for the patches, they are on top of 3.18-rc7 + tip/irq/irqdomain-arm +
> > the gic_arch_extn removal series.
> > 
> > I've pushed the code to:
> > git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die
> > 
> > Comments welcome,
> > 
> > 	 M.
> > 
> > Marc Zyngier (5):
> >   genirq: Add irqchip_set_wake_parent
> >   irqchip: crossbar: convert dra7 crossbar to stacked domains
> >   DT: update ti,irq-crossbar binding
> >   irqchip: GIC: get rid of routable domain
> >   DT: arm,gic: kill arm,routable-irqs
> > 
> >  Documentation/devicetree/bindings/arm/gic.txt      |   6 -
> >  .../devicetree/bindings/arm/omap/crossbar.txt      |  18 +-
> >  arch/arm/boot/dts/dra7.dtsi                        |  10 +-
> >  arch/arm/boot/dts/dra72x.dtsi                      |   3 +-
> >  arch/arm/boot/dts/dra74x.dtsi                      |   5 +-
> >  arch/arm/mach-omap2/omap4-common.c                 |   4 -
> >  drivers/irqchip/irq-crossbar.c                     | 202 ++++++++++++---------
> >  drivers/irqchip/irq-gic.c                          |  59 +-----
> >  include/linux/irq.h                                |   1 +
> >  include/linux/irqchip/arm-gic.h                    |   6 -
> >  include/linux/irqchip/irq-crossbar.h               |  11 --
> >  kernel/irq/chip.c                                  |  16 ++
> >  12 files changed, 153 insertions(+), 188 deletions(-)
> >  delete mode 100644 include/linux/irqchip/irq-crossbar.h
> > 
> > -- 
> > 2.1.3
> > 
> 
> 	Patches are available here:
> 	https://patchwork.kernel.org/patch/5449231/
> 	https://patchwork.kernel.org/patch/5449241/
> 	https://patchwork.kernel.org/patch/5449271/
> 	https://patchwork.kernel.org/patch/5449261/
> 	https://patchwork.kernel.org/patch/5449251/

dra7xx-evm(3.18-rc7):  Boot PASS: http://slexy.org/raw/s2PXWFB47A
dra7xx-evm(irq branch):  Boot FAIL: http://slexy.org/raw/s2xMgD4zkP

Would you want me to debug more - dts changes perhaps?

-- 
Regards,
Nishanth Menon

[PATCH 0/5] irqchip: kill the GIC routable domain

[Marc Zyngier]

On 07/12/14 18:03, Nishanth Menon wrote:
> Marc,
> 
> On 11:16-20141207, Nishanth Menon wrote:
>> On 13:46-20141206, Marc Zyngier wrote:
>>> After my series removing the gic_arch_extn hack, I figured that the
>>> next step was to expunge the GIC driver of the routable domain horror.
>>>
>>> There is a few reasons for this:
>>>
>>> - The allocation of interrupts in this domain is fairly similar to
>>>   what we do for MSI (see the GICv2m driver), and stacked domains have
>>>   proved to be a fitting solution.
>>>
>>> - The current description in DT is currently entierely inaccurate, and
>>>   as we already broke it for the OMAP WUGEN block, we might as well do
>>>   it again for the TI crossbar.
>>>
>>> - The way crossbar, WUGEN and GIC interract is quite complex (this is
>>>   effectively a stack of three interrupt controllers with interesting
>>>   exceptions and braindead routing), and stacked domains are the right
>>>   abstraction for that.
>>>
>>> - Other platforms (Freescale Vybrid) are starting to come up with the
>>>   same type of things, and it'd be good to avoid them following the
>>>   same broken model.
>>>
>>> - It removes a few lines from the code base so it can't completely be
>>>   a bad idea!
>>>
>>> So this patch series does exactly that: make the crossbar a stacked
>>> interrupt controller that only takes care of setting up the routing,
>>> fix the DTs to represent the actual HW, and remove a bit of the
>>> craziness from the GIC code.
>>>
>>> As for the previous series:
>>>
>>> - I haven't been able to test this at all, I don't have access to the
>>>   HW. TI people, please test and post fixes, as I expect I introduced
>>>   a few bugs.
>>>
>>> - This actively *breaks* existing setups. If you boot a new kernel
>>>   with an old DT, interrupt routing *will* be broken. Old kernels on a
>>>   new DT won't boot either! You've been warned. This really outline
>>>   the necessity of actually describing the HW in device trees...
>>>
>>> As for the patches, they are on top of 3.18-rc7 + tip/irq/irqdomain-arm +
>>> the gic_arch_extn removal series.
>>>
>>> I've pushed the code to:
>>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/die-gic-arch-extn-die-die-die
>>>
>>> Comments welcome,
>>>
>>> 	 M.
>>>
>>> Marc Zyngier (5):
>>>   genirq: Add irqchip_set_wake_parent
>>>   irqchip: crossbar: convert dra7 crossbar to stacked domains
>>>   DT: update ti,irq-crossbar binding
>>>   irqchip: GIC: get rid of routable domain
>>>   DT: arm,gic: kill arm,routable-irqs
>>>
>>>  Documentation/devicetree/bindings/arm/gic.txt      |   6 -
>>>  .../devicetree/bindings/arm/omap/crossbar.txt      |  18 +-
>>>  arch/arm/boot/dts/dra7.dtsi                        |  10 +-
>>>  arch/arm/boot/dts/dra72x.dtsi                      |   3 +-
>>>  arch/arm/boot/dts/dra74x.dtsi                      |   5 +-
>>>  arch/arm/mach-omap2/omap4-common.c                 |   4 -
>>>  drivers/irqchip/irq-crossbar.c                     | 202 ++++++++++++---------
>>>  drivers/irqchip/irq-gic.c                          |  59 +-----
>>>  include/linux/irq.h                                |   1 +
>>>  include/linux/irqchip/arm-gic.h                    |   6 -
>>>  include/linux/irqchip/irq-crossbar.h               |  11 --
>>>  kernel/irq/chip.c                                  |  16 ++
>>>  12 files changed, 153 insertions(+), 188 deletions(-)
>>>  delete mode 100644 include/linux/irqchip/irq-crossbar.h
>>>
>>> -- 
>>> 2.1.3
>>>
>>
>> 	Patches are available here:
>> 	https://patchwork.kernel.org/patch/5449231/
>> 	https://patchwork.kernel.org/patch/5449241/
>> 	https://patchwork.kernel.org/patch/5449271/
>> 	https://patchwork.kernel.org/patch/5449261/
>> 	https://patchwork.kernel.org/patch/5449251/
> 
> dra7xx-evm(3.18-rc7):  Boot PASS: http://slexy.org/raw/s2PXWFB47A
> dra7xx-evm(irq branch):  Boot FAIL: http://slexy.org/raw/s2xMgD4zkP
> 
> Would you want me to debug more - dts changes perhaps?

Yes, it would be useful to find out. One thing that strikes me is that
the kernel boots all the way, so I assume IRQs are actually up and running.

One thing though. The "irq" branch shows this:
[   15.359025] pbias_mmc_omap5: disabling

and the MMC subsystem never initializes. I'm pretty sure this is
related. Config option?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH 1/5] genirq: Add irqchip_set_wake_parent

[Marc Zyngier]

On 06/12/14 15:34, Stefan Agner wrote:
> Thanks for the CC, interesting read for me, good preparation for the
> next revision of my Vybrid patchset. One thing I stumbled upon below:
> 
> On 2014-12-06 14:46, Marc Zyngier wrote:
>> This proves to be usefull with stacked domains.
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>>  include/linux/irq.h |  1 +
>>  kernel/irq/chip.c   | 16 ++++++++++++++++
>>  2 files changed, 17 insertions(+)
>>
>> diff --git a/include/linux/irq.h b/include/linux/irq.h
>> index 8badf34..7de85b8 100644
>> --- a/include/linux/irq.h
>> +++ b/include/linux/irq.h
>> @@ -459,6 +459,7 @@ extern void irq_chip_eoi_parent(struct irq_data *data);
>>  extern int irq_chip_set_affinity_parent(struct irq_data *data,
>>  					const struct cpumask *dest,
>>  					bool force);
>> +extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
>>  #endif
>>  
>>  static inline void irq_chip_write_msi_msg(struct irq_data *data,
>> diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
>> index 6f1c7a5..96c190b 100644
>> --- a/kernel/irq/chip.c
>> +++ b/kernel/irq/chip.c
>> @@ -948,6 +948,22 @@ int irq_chip_retrigger_hierarchy(struct irq_data *data)
>>  
>>  	return -ENOSYS;
>>  }
>> +
>> +/**
>> + * irq_chip_set_wake - Set/reset wake-up on the parent interrupt
>                        ^
> This should be irq_chip_set_wake_parent I guess...

Good call.

Thanks!

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH 0/5] irqchip: kill the GIC routable domain

[Nishanth Menon]

On 09:10-20141208, Marc Zyngier wrote:
> On 07/12/14 18:03, Nishanth Menon wrote:
[..]
> > dra7xx-evm(3.18-rc7):  Boot PASS: http://slexy.org/raw/s2PXWFB47A
> > dra7xx-evm(irq branch):  Boot FAIL: http://slexy.org/raw/s2xMgD4zkP
> > 
> > Would you want me to debug more - dts changes perhaps?
> 
> Yes, it would be useful to find out. One thing that strikes me is that
> the kernel boots all the way, so I assume IRQs are actually up and running.

Nope, we dont usually need peripheral interrupts untill we use them..
mmc is the first to use it, followed by serial port of course :)..
> 
> One thing though. The "irq" branch shows this:
> [   15.359025] pbias_mmc_omap5: disabling
> 
> and the MMC subsystem never initializes. I'm pretty sure this is
> related. Config option?
nope. just the request mmc card was never detected (crossbar was
misconfigured)

Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
assume you will squash as needed and repost with linux-omap mailing list
in CC.

I increased the scope of testing knowing that WUGEN is present in many
A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
my testing.. Also a few notes:

Stuff like: am437x is a bit questionable (interrupt-parent probably should be wugen?)
175:          0       GIC  39  tps65218 

OMAP5: (should be wugen?)
308:       4323          0       GIC 106  OMAP UART2
411:          0          0       GIC 151  twl6040
405:          1          0       GIC  39  palmas

OMAP4 serial port is flaky -> not sure if it is due to routing of GIC to UART2 and not via WUGEN
IRQ branch: with my fix applied:
---------------------------------
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2aN42JkKi
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s21w2OG3hL
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s21Tlp6ZLq
 4:  am37x-evm:  Boot PASS: http://slexy.org/raw/s21Vqp6P1B
 5:  am437x-sk:  Boot PASS: http://slexy.org/raw/s2UhY45mJc
 6: am43xx-epos:  Boot PASS: http://slexy.org/raw/s20l5l2fj4
 7: am43xx-gpevm:  Boot PASS: http://slexy.org/raw/s2aRwhAtau
 8: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2GbGmM7xU
 9: beagleboard-vanilla:  Boot PASS: http://slexy.org/raw/s209bMoHPd
10: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2IzmRPyVI
11: beaglebone:  Boot PASS: http://slexy.org/raw/s2053lNp5G
12: craneboard:  Boot PASS: http://slexy.org/raw/s2kKkEoR4A
13: dra72x-evm:  Boot FAIL: http://slexy.org/raw/s21jb0oCBm (this one is known -> mmc node is missing)
14: dra7xx-evm:  Boot PASS: http://slexy.org/raw/s2ho2KH2rh
15: OMAP3430-Labrador(LDP):  Boot PASS: http://slexy.org/raw/s21U4McCJp
16:       n900:  Boot PASS: http://slexy.org/raw/s2Np9wQrYd
17:  omap5-evm:  Boot PASS: http://slexy.org/raw/s21Dd4tS2M
18: pandaboard-es:  Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not expected)
19: pandaboard-vanilla:  Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not expected)
20:    sdp2430:  Boot PASS: http://slexy.org/raw/s21AygxGRg
21:    sdp3430:  Boot PASS: http://slexy.org/raw/s207290wN9
TOTAL = 21 boards, Booted Boards = 18, No Boot boards = 3

comparitive reference v3.18-rc7:
--------------------------------
 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s2ASdqrwQx
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s208zUIeql
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s20dx70o4a
 4:  am37x-evm:  Boot FAIL: http://slexy.org/raw/s20qKJVqIQ (ignore this: board farm issue/PMIC power script issue - unrelated and known).
 5:  am437x-sk:  Boot PASS: http://slexy.org/raw/s20K8unGsM
 6: am43xx-epos:  Boot PASS: http://slexy.org/raw/s21hPfz6DC
 7: am43xx-gpevm:  Boot PASS: http://slexy.org/raw/s2voHleSYO
 8: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s208GPH7nx
 9: beagleboard-vanilla:  Boot PASS: http://slexy.org/raw/s20jOW13Ig
10: beaglebone-black:  Boot PASS: http://slexy.org/raw/s2I60jGnCI
11: beaglebone:  Boot PASS: http://slexy.org/raw/s29u4NiShX
12: craneboard:  Boot PASS: http://slexy.org/raw/s2T7etBuGm
13: dra72x-evm:  Boot FAIL: http://slexy.org/raw/s21dmHgoXn (known issue - mmc node is missing)
14: dra7xx-evm:  Boot PASS: http://slexy.org/raw/s21cFgrB0f
15: OMAP3430-Labrador(LDP):  Boot PASS: http://slexy.org/raw/s2FBPPQ3ML
16:       n900:  Boot PASS: http://slexy.org/raw/s2RmlkVWvN
17:  omap5-evm:  Boot PASS: http://slexy.org/raw/s2YKl1szpz
18: pandaboard-es:  Boot PASS: http://slexy.org/raw/s2hvXLDMoS
19: pandaboard-vanilla:  Boot PASS: http://slexy.org/raw/s2056IOHsT
20:    sdp2430:  Boot PASS: http://slexy.org/raw/s2PYPNr7jm
21:    sdp3430:  Boot PASS: http://slexy.org/raw/s2Iyc9K8I6
TOTAL = 21 boards, Booted Boards = 19, No Boot boards = 2

I suggest skipping 3.19 if possible and giving it a more detailed time
in linux-next with omap4 etc being more thoroughly being tested before
letting it through, if possible.

[1] ------------- diff ------------
 arch/arm/boot/dts/dra7-evm.dts |    2 +-
 arch/arm/boot/dts/dra7.dtsi    |   23 +++++++++++++----------
 drivers/irqchip/irq-crossbar.c |    4 ++--
 3 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index c6ce625..d024429 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -323,7 +323,7 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart1_pins>;
-	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 			      <&dra7_pmx_core 0x3e0>;
 };
 
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 43509e9..a7aa7c4 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -94,6 +94,8 @@
 		interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 				      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+		interrupt-parent = <&crossbar_mpu>;
+
 		prm: prm at 4ae06000 {
 			compatible = "ti,dra7-prm";
 			reg = <0x4ae06000 0x3000>;
@@ -339,7 +341,7 @@
 		uart1: serial at 4806a000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806a000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -348,7 +350,7 @@
 		uart2: serial at 4806c000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806c000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -357,7 +359,7 @@
 		uart3: serial at 48020000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48020000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -366,7 +368,7 @@
 		uart4: serial at 4806e000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4806e000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
                         status = "disabled";
@@ -375,7 +377,7 @@
 		uart5: serial at 48066000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48066000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart5";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -384,7 +386,7 @@
 		uart6: serial at 48068000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48068000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart6";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -393,7 +395,7 @@
 		uart7: serial at 48420000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48420000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart7";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -402,7 +404,7 @@
 		uart8: serial at 48422000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48422000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart8";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -411,7 +413,7 @@
 		uart9: serial at 48424000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x48424000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart9";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -420,7 +422,7 @@
 		uart10: serial at 4ae2b000 {
 			compatible = "ti,omap4-uart";
 			reg = <0x4ae2b000 0x100>;
-			interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&crossbar_mpu GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart10";
 			clock-frequency = <48000000>;
 			status = "disabled";
@@ -1268,6 +1270,7 @@
 			reg = <0x4a002a48 0x130>;
 			interrupt-controller;
 			interrupt-parent = <&wakeupgen>;
+			#interrupt-cells = <3>;
 			ti,max-irqs = <160>;
 			ti,max-crossbar-sources = <MAX_SOURCES>;
 			ti,reg-size = <2>;
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index b44915a..f7daff0 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -99,7 +99,7 @@ static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
 	if (err)
 		cb->irq_map[i] = IRQ_FREE;
 	else
-		cb->write(hwirq, i);
+		cb->write(i, hwirq);
 
 	return err;
 }
@@ -353,4 +353,4 @@ static int __init irqcrossbar_init(struct device_node *node,
 	return 0;
 }
 
-IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irqcrossbar", irqcrossbar_init);
+IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);
-- 
1.7.9.5

-- 
Regards,
Nishanth Menon

[PATCH 0/5] irqchip: kill the GIC routable domain

[Marc Zyngier]

On 08/12/14 22:41, Nishanth Menon wrote:

> Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
> assume you will squash as needed and repost with linux-omap mailing list
> in CC.

Brilliant. I'll squash that into my tree and repost at some point.

> I increased the scope of testing knowing that WUGEN is present in many
> A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
> my testing.. Also a few notes:
> 
> Stuff like: am437x is a bit questionable (interrupt-parent probably should be wugen?)
> 175:          0       GIC  39  tps65218 
> 
> OMAP5: (should be wugen?)
> 308:       4323          0       GIC 106  OMAP UART2
> 411:          0          0       GIC 151  twl6040
> 405:          1          0       GIC  39  palmas

Well, I can't really tell. Someone with access to the documentation
should be able to find out.

> OMAP4 serial port is flaky -> not sure if it is due to routing of GIC to UART2 and not via WUGEN
> IRQ branch: with my fix applied:
> ---------------------------------

[...]

> 18: pandaboard-es:  Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not expected)
> 19: pandaboard-vanilla:  Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not expected)

If I read the log correctly, the serial port stops responding after a while?

[...]

> I suggest skipping 3.19 if possible and giving it a more detailed time
> in linux-next with omap4 etc being more thoroughly being tested before
> letting it through, if possible.

None of that code is for 3.19 (that ship has sailed a long time ago). My
plan is to hit 3.20, so it should be in -next by -rc4 or so.

> [1] ------------- diff ------------
>  arch/arm/boot/dts/dra7-evm.dts |    2 +-
>  arch/arm/boot/dts/dra7.dtsi    |   23 +++++++++++++----------
>  drivers/irqchip/irq-crossbar.c |    4 ++--
>  3 files changed, 16 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index c6ce625..d024429 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -323,7 +323,7 @@
>  	status = "okay";
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&uart1_pins>;
> -	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> +	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
>  			      <&dra7_pmx_core 0x3e0>;
>  };

Ah, I obviously missed quite a few of these...

[...]

> diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
> index b44915a..f7daff0 100644
> --- a/drivers/irqchip/irq-crossbar.c
> +++ b/drivers/irqchip/irq-crossbar.c
> @@ -99,7 +99,7 @@ static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
>  	if (err)
>  		cb->irq_map[i] = IRQ_FREE;
>  	else
> -		cb->write(hwirq, i);
> +		cb->write(i, hwirq);
>  
>  	return err;
>  }
> @@ -353,4 +353,4 @@ static int __init irqcrossbar_init(struct device_node *node,
>  	return 0;
>  }
>  
> -IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irqcrossbar", irqcrossbar_init);
> +IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);

Ah, nice catch. Thanks a lot for the testing and the fixes. I'll try to
get a panda up and running (I'm sure I have one collecting dust
somewhere), and see if I can get it to behave.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH 0/5] irqchip: kill the GIC routable domain

[Nishanth Menon]

On 09:53-20141209, Marc Zyngier wrote:
> On 08/12/14 22:41, Nishanth Menon wrote:
> 
> > Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
> > assume you will squash as needed and repost with linux-omap mailing list
> > in CC.
> 
> Brilliant. I'll squash that into my tree and repost at some point.

K, it will be nice to have a reflow of the series based on v3.19-rc1
since there are dts dependencies and we dont want folks to have
regressions on their platforms of choice..

Obviously, my tests are basic boot tests and should get a few weeks(as
you already mentioned) on linux-next to get properly soaked

> 
> > I increased the scope of testing knowing that WUGEN is present in many
> > A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
> > my testing.. Also a few notes:
> > 
> > Stuff like: am437x is a bit questionable (interrupt-parent probably should be wugen?)
> > 175:          0       GIC  39  tps65218 
> > 
> > OMAP5: (should be wugen?)
> > 308:       4323          0       GIC 106  OMAP UART2
> > 411:          0          0       GIC 151  twl6040
> > 405:          1          0       GIC  39  palmas
> 
> Well, I can't really tell. Someone with access to the documentation
> should be able to find out.

AM437x: http://www.ti.com/lit/pdf/spruhl7
OMAP5: http://www.ti.com/lit/pdf/swpu249

yeah, we should be able to do them as well - trivially since they follow
the same structure as other SoCs without crossbar.

> 
> > OMAP4 serial port is flaky -> not sure if it is due to routing of GIC to UART2 and not via WUGEN
> > IRQ branch: with my fix applied:
> > ---------------------------------
> 
> [...]
> 
> > 18: pandaboard-es:  Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not expected)
> > 19: pandaboard-vanilla:  Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not expected)
> 
> If I read the log correctly, the serial port stops responding after a while?

yeah - dug at the omap4 ones a bit, obviously once the deeper c states
are hit, we'd like wakeupgen to wakeup CPU else we will be "sluggish" in
the sense that the event is detected when some other wakeupgen enabled
interrupt takes place.

Adding the following makes my panda work fine.
1: pandaboard-es:  Boot PASS: http://slexy.org/raw/s20o8DaBvh
2: pandaboard-vanilla:  Boot PASS: http://slexy.org/raw/s222JndDdh


diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 1505135..8b6d50e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -371,8 +371,8 @@
 	twl: twl at 48 {
 		reg = <0x48>;
 		/* IRQ# = 7 */
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
-		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to wakeupgen to gic */
+		interrupt-parent = <&wakeupgen>;
 	};
 
 	twl6040: twl at 4b {
@@ -383,8 +383,8 @@
 		pinctrl-0 = <&twl6040_pins>;
 
 		/* IRQ# = 119 */
-		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
-		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to wakeupgen to gic */
+		interrupt-parent = <&wakeupgen>;
 		ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;  /* gpio line 127 */
 
 		vio-supply = <&v1v8>;
@@ -479,17 +479,17 @@
 };
 
 &uart2 {
-	interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+	interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
 			       &omap4_pmx_core OMAP4_UART2_RX>;
 };
 
 &uart3 {
-	interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+	interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
 			       &omap4_pmx_core OMAP4_UART3_RX>;
 };
 
 &uart4 {
-	interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+	interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
 			       &omap4_pmx_core OMAP4_UART4_RX>;
 };
 
-- 
Regards,
Nishanth Menon

[PATCH 0/5] irqchip: kill the GIC routable domain

[Marc Zyngier]

On 09/12/14 18:17, Nishanth Menon wrote:
> On 09:53-20141209, Marc Zyngier wrote:
>> On 08/12/14 22:41, Nishanth Menon wrote:
>>
>>> Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
>>> assume you will squash as needed and repost with linux-omap mailing list
>>> in CC.
>>
>> Brilliant. I'll squash that into my tree and repost at some point.
> 
> K, it will be nice to have a reflow of the series based on v3.19-rc1
> since there are dts dependencies and we dont want folks to have
> regressions on their platforms of choice..
> 
> Obviously, my tests are basic boot tests and should get a few weeks(as
> you already mentioned) on linux-next to get properly soaked
> 
>>
>>> I increased the scope of testing knowing that WUGEN is present in many
>>> A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
>>> my testing.. Also a few notes:
>>>
>>> Stuff like: am437x is a bit questionable (interrupt-parent probably should be wugen?)
>>> 175:          0       GIC  39  tps65218 
>>>
>>> OMAP5: (should be wugen?)
>>> 308:       4323          0       GIC 106  OMAP UART2
>>> 411:          0          0       GIC 151  twl6040
>>> 405:          1          0       GIC  39  palmas
>>
>> Well, I can't really tell. Someone with access to the documentation
>> should be able to find out.
> 
> AM437x: http://www.ti.com/lit/pdf/spruhl7
> OMAP5: http://www.ti.com/lit/pdf/swpu249
> 
> yeah, we should be able to do them as well - trivially since they follow
> the same structure as other SoCs without crossbar.

Done some stuff in that department.

>>
>>> OMAP4 serial port is flaky -> not sure if it is due to routing of GIC to UART2 and not via WUGEN
>>> IRQ branch: with my fix applied:
>>> ---------------------------------
>>
>> [...]
>>
>>> 18: pandaboard-es:  Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not expected)
>>> 19: pandaboard-vanilla:  Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not expected)
>>
>> If I read the log correctly, the serial port stops responding after a while?
> 
> yeah - dug at the omap4 ones a bit, obviously once the deeper c states
> are hit, we'd like wakeupgen to wakeup CPU else we will be "sluggish" in
> the sense that the event is detected when some other wakeupgen enabled
> interrupt takes place.

I realised that as well once I got a panda up and running.

> Adding the following makes my panda work fine.
> 1: pandaboard-es:  Boot PASS: http://slexy.org/raw/s20o8DaBvh
> 2: pandaboard-vanilla:  Boot PASS: http://slexy.org/raw/s222JndDdh
> 
> 
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index 1505135..8b6d50e 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -371,8 +371,8 @@
>  	twl: twl at 48 {
>  		reg = <0x48>;
>  		/* IRQ# = 7 */
> -		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
> -		interrupt-parent = <&gic>;
> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to wakeupgen to gic */
> +		interrupt-parent = <&wakeupgen>;
>  	};

[...]

I already fixed those in my tree, in a slightly different way: no need
to have an interrupt parent at all, as we're going to inherit the
default anyway.

I've pushed another version of the branch, with the crossbar rework
sitting *before* the WUGEN hacks. That should hopefully make bisection work.

If you can give it a shake, that'd be most appreciated. I'll repost the
branch in a couple of days.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH 0/5] irqchip: kill the GIC routable domain

[Nishanth Menon]

On 12/09/2014 12:40 PM, Marc Zyngier wrote:
> On 09/12/14 18:17, Nishanth Menon wrote:
>> On 09:53-20141209, Marc Zyngier wrote:
>>> On 08/12/14 22:41, Nishanth Menon wrote:
>>>
>>>> Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
>>>> assume you will squash as needed and repost with linux-omap mailing list
>>>> in CC.
>>>
>>> Brilliant. I'll squash that into my tree and repost at some point.
>>
>> K, it will be nice to have a reflow of the series based on v3.19-rc1
>> since there are dts dependencies and we dont want folks to have
>> regressions on their platforms of choice..
>>
>> Obviously, my tests are basic boot tests and should get a few weeks(as
>> you already mentioned) on linux-next to get properly soaked
>>
>>>
>>>> I increased the scope of testing knowing that WUGEN is present in many
>>>> A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
>>>> my testing.. Also a few notes:
>>>>
>>>> Stuff like: am437x is a bit questionable (interrupt-parent probably should be wugen?)
>>>> 175:          0       GIC  39  tps65218 
>>>>
>>>> OMAP5: (should be wugen?)
>>>> 308:       4323          0       GIC 106  OMAP UART2
>>>> 411:          0          0       GIC 151  twl6040
>>>> 405:          1          0       GIC  39  palmas
>>>
>>> Well, I can't really tell. Someone with access to the documentation
>>> should be able to find out.
>>
>> AM437x: http://www.ti.com/lit/pdf/spruhl7
>> OMAP5: http://www.ti.com/lit/pdf/swpu249
>>
>> yeah, we should be able to do them as well - trivially since they follow
>> the same structure as other SoCs without crossbar.
> 
> Done some stuff in that department.
> 
>>>
>>>> OMAP4 serial port is flaky -> not sure if it is due to routing of GIC to UART2 and not via WUGEN
>>>> IRQ branch: with my fix applied:
>>>> ---------------------------------
>>>
>>> [...]
>>>
>>>> 18: pandaboard-es:  Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not expected)
>>>> 19: pandaboard-vanilla:  Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not expected)
>>>
>>> If I read the log correctly, the serial port stops responding after a while?
>>
>> yeah - dug at the omap4 ones a bit, obviously once the deeper c states
>> are hit, we'd like wakeupgen to wakeup CPU else we will be "sluggish" in
>> the sense that the event is detected when some other wakeupgen enabled
>> interrupt takes place.
> 
> I realised that as well once I got a panda up and running.
> 
>> Adding the following makes my panda work fine.
>> 1: pandaboard-es:  Boot PASS: http://slexy.org/raw/s20o8DaBvh
>> 2: pandaboard-vanilla:  Boot PASS: http://slexy.org/raw/s222JndDdh
>>
>>
>> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> index 1505135..8b6d50e 100644
>> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
>> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
>> @@ -371,8 +371,8 @@
>>  	twl: twl at 48 {
>>  		reg = <0x48>;
>>  		/* IRQ# = 7 */
>> -		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
>> -		interrupt-parent = <&gic>;
>> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to wakeupgen to gic */
>> +		interrupt-parent = <&wakeupgen>;
>>  	};
> 
> [...]
> 
> I already fixed those in my tree, in a slightly different way: no need
> to have an interrupt parent at all, as we're going to inherit the
> default anyway.
> 
> I've pushed another version of the branch, with the crossbar rework
> sitting *before* the WUGEN hacks. That should hopefully make bisection work.
> 
> If you can give it a shake, that'd be most appreciated. I'll repost the
> branch in a couple of days.
> 

Did a quick run.. and thought of testing power management and found
that CPUFreq for my platforms are broken in v3.18-rc7 and my scripts
broke (so much for my cronjob testing daily boot... now I gotta add
some PM test as well.. Sigh..) anyways.. just boot log..

based on
irq/die-gic-arch-extn-die-die-die c0024cb irqchip: gic: Drop support
for gic_arch_extn


 1: am335x-evm:  Boot PASS: http://slexy.org/raw/s201YeK4dW
 2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20nydiyVx
 3: am3517-evm:  Boot PASS: http://slexy.org/raw/s2aTrenePo
 4:  am437x-sk:  Boot FAIL: http://slexy.org/raw/s20NNiEa4W
 5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2gghhhyOy
 6: am43xx-gpevm:  Boot PASS: http://slexy.org/raw/s2LY4Cb75N
 7: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2e8iJMUXu
 8: beagleboard-vanilla:  Boot PASS: http://slexy.org/raw/s20wqxUmvr
 9: beaglebone-black:  Boot PASS: http://slexy.org/raw/s21I0g2Ba3
10: beaglebone:  Boot PASS: http://slexy.org/raw/s2lpED0qW4
11: craneboard:  Boot PASS: http://slexy.org/raw/s230RKflY3
12: dra72x-evm:  Boot FAIL: http://slexy.org/raw/s21fWVnjaB
13: dra7xx-evm:  Boot PASS: http://slexy.org/raw/s20yEhfruO
14: OMAP3430-Labrador(LDP):  Boot PASS: http://slexy.org/raw/s20qZaXwz0
15:       n900:  Boot PASS: http://slexy.org/raw/s21LNTXZP7
16:  omap5-evm:  Boot PASS: http://slexy.org/raw/s2WF8eAcK2
17: pandaboard-es:  Boot PASS: http://slexy.org/raw/s21PVo7ENF
18: pandaboard-vanilla:  Boot PASS: http://slexy.org/raw/s2BcMbSrVF
19:    sdp2430:  Boot PASS: http://slexy.org/raw/s24LgXbav1
20:    sdp3430:  Boot PASS: http://slexy.org/raw/s21IaKdkUs
TOTAL = 20 boards, Booted Boards = 18, No Boot boards = 2


will try to first try and save a bit of cpufreq and reinstate my
scripts and once you post based on 3.19-rc1, will do a retest..

-- 
Regards,
Nishanth Menon

[PATCH 0/5] irqchip: kill the GIC routable domain

[Jason Cooper]

On Tue, Dec 09, 2014 at 06:40:35PM +0000, Marc Zyngier wrote:
> On 09/12/14 18:17, Nishanth Menon wrote:
> > On 09:53-20141209, Marc Zyngier wrote:
> >> On 08/12/14 22:41, Nishanth Menon wrote:
> >>
> >>> Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
> >>> assume you will squash as needed and repost with linux-omap mailing list
> >>> in CC.
> >>
> >> Brilliant. I'll squash that into my tree and repost at some point.
> > 
> > K, it will be nice to have a reflow of the series based on v3.19-rc1
> > since there are dts dependencies and we dont want folks to have
> > regressions on their platforms of choice..
> > 
> > Obviously, my tests are basic boot tests and should get a few weeks(as
> > you already mentioned) on linux-next to get properly soaked
> > 
> >>
> >>> I increased the scope of testing knowing that WUGEN is present in many
> >>> A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
> >>> my testing.. Also a few notes:
> >>>
> >>> Stuff like: am437x is a bit questionable (interrupt-parent probably should be wugen?)
> >>> 175:          0       GIC  39  tps65218 
> >>>
> >>> OMAP5: (should be wugen?)
> >>> 308:       4323          0       GIC 106  OMAP UART2
> >>> 411:          0          0       GIC 151  twl6040
> >>> 405:          1          0       GIC  39  palmas
> >>
> >> Well, I can't really tell. Someone with access to the documentation
> >> should be able to find out.
> > 
> > AM437x: http://www.ti.com/lit/pdf/spruhl7
> > OMAP5: http://www.ti.com/lit/pdf/swpu249
> > 
> > yeah, we should be able to do them as well - trivially since they follow
> > the same structure as other SoCs without crossbar.
> 
> Done some stuff in that department.
> 
> >>
> >>> OMAP4 serial port is flaky -> not sure if it is due to routing of GIC to UART2 and not via WUGEN
> >>> IRQ branch: with my fix applied:
> >>> ---------------------------------
> >>
> >> [...]
> >>
> >>> 18: pandaboard-es:  Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not expected)
> >>> 19: pandaboard-vanilla:  Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not expected)
> >>
> >> If I read the log correctly, the serial port stops responding after a while?
> > 
> > yeah - dug at the omap4 ones a bit, obviously once the deeper c states
> > are hit, we'd like wakeupgen to wakeup CPU else we will be "sluggish" in
> > the sense that the event is detected when some other wakeupgen enabled
> > interrupt takes place.
> 
> I realised that as well once I got a panda up and running.
> 
> > Adding the following makes my panda work fine.
> > 1: pandaboard-es:  Boot PASS: http://slexy.org/raw/s20o8DaBvh
> > 2: pandaboard-vanilla:  Boot PASS: http://slexy.org/raw/s222JndDdh
> > 
> > 
> > diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> > index 1505135..8b6d50e 100644
> > --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> > +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> > @@ -371,8 +371,8 @@
> >  	twl: twl at 48 {
> >  		reg = <0x48>;
> >  		/* IRQ# = 7 */
> > -		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
> > -		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to wakeupgen to gic */
> > +		interrupt-parent = <&wakeupgen>;
> >  	};
> 
> [...]
> 
> I already fixed those in my tree, in a slightly different way: no need
> to have an interrupt parent at all, as we're going to inherit the
> default anyway.
> 
> I've pushed another version of the branch, with the crossbar rework
> sitting *before* the WUGEN hacks. That should hopefully make bisection work.
> 
> If you can give it a shake, that'd be most appreciated. I'll repost the
> branch in a couple of days.

Hmmm, I'm sensing a pattern here :)  My email, only to the MLs, was
messed up for a few days.  I probably missed it in there...

thx,

Jason.

[PATCH 0/5] irqchip: kill the GIC routable domain

[Nishanth Menon]

On 12:21-20141210, Nishanth Menon wrote:
> On 12/09/2014 12:40 PM, Marc Zyngier wrote:
> > On 09/12/14 18:17, Nishanth Menon wrote:
> >> On 09:53-20141209, Marc Zyngier wrote:
> >>> On 08/12/14 22:41, Nishanth Menon wrote:
> >>>
> >>>> Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
> >>>> assume you will squash as needed and repost with linux-omap mailing list
> >>>> in CC.
> >>>
> >>> Brilliant. I'll squash that into my tree and repost at some point.
> >>
> >> K, it will be nice to have a reflow of the series based on v3.19-rc1
> >> since there are dts dependencies and we dont want folks to have
> >> regressions on their platforms of choice..
> >>
> >> Obviously, my tests are basic boot tests and should get a few weeks(as
> >> you already mentioned) on linux-next to get properly soaked
> >>
> >>>
> >>>> I increased the scope of testing knowing that WUGEN is present in many
> >>>> A9 based TI platforms as well.. and at least OMAP4 showed flakiness in
> >>>> my testing.. Also a few notes:
> >>>>
> >>>> Stuff like: am437x is a bit questionable (interrupt-parent probably should be wugen?)
> >>>> 175:          0       GIC  39  tps65218 
> >>>>
> >>>> OMAP5: (should be wugen?)
> >>>> 308:       4323          0       GIC 106  OMAP UART2
> >>>> 411:          0          0       GIC 151  twl6040
> >>>> 405:          1          0       GIC  39  palmas
> >>>
> >>> Well, I can't really tell. Someone with access to the documentation
> >>> should be able to find out.
> >>
> >> AM437x: http://www.ti.com/lit/pdf/spruhl7
> >> OMAP5: http://www.ti.com/lit/pdf/swpu249
> >>
> >> yeah, we should be able to do them as well - trivially since they follow
> >> the same structure as other SoCs without crossbar.
> > 
> > Done some stuff in that department.
> > 
> >>>
> >>>> OMAP4 serial port is flaky -> not sure if it is due to routing of GIC to UART2 and not via WUGEN
> >>>> IRQ branch: with my fix applied:
> >>>> ---------------------------------
> >>>
> >>> [...]
> >>>
> >>>> 18: pandaboard-es:  Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not expected)
> >>>> 19: pandaboard-vanilla:  Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not expected)
> >>>
> >>> If I read the log correctly, the serial port stops responding after a while?
> >>
> >> yeah - dug at the omap4 ones a bit, obviously once the deeper c states
> >> are hit, we'd like wakeupgen to wakeup CPU else we will be "sluggish" in
> >> the sense that the event is detected when some other wakeupgen enabled
> >> interrupt takes place.
> > 
> > I realised that as well once I got a panda up and running.
> > 
> >> Adding the following makes my panda work fine.
> >> 1: pandaboard-es:  Boot PASS: http://slexy.org/raw/s20o8DaBvh
> >> 2: pandaboard-vanilla:  Boot PASS: http://slexy.org/raw/s222JndDdh
> >>
> >>
> >> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> >> index 1505135..8b6d50e 100644
> >> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> >> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> >> @@ -371,8 +371,8 @@
> >>  	twl: twl at 48 {
> >>  		reg = <0x48>;
> >>  		/* IRQ# = 7 */
> >> -		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
> >> -		interrupt-parent = <&gic>;
> >> +		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to wakeupgen to gic */
> >> +		interrupt-parent = <&wakeupgen>;
> >>  	};
> > 
> > [...]
> > 
> > I already fixed those in my tree, in a slightly different way: no need
> > to have an interrupt parent at all, as we're going to inherit the
> > default anyway.
> > 
> > I've pushed another version of the branch, with the crossbar rework
> > sitting *before* the WUGEN hacks. That should hopefully make bisection work.
> > 
> > If you can give it a shake, that'd be most appreciated. I'll repost the
> > branch in a couple of days.
> > 
> 
> Did a quick run.. and thought of testing power management and found
> that CPUFreq for my platforms are broken in v3.18-rc7 and my scripts
> broke (so much for my cronjob testing daily boot... now I gotta add
> some PM test as well.. Sigh..) anyways.. just boot log..
> 
> based on
> irq/die-gic-arch-extn-die-die-die c0024cb irqchip: gic: Drop support
> for gic_arch_extn
> 
> 
>  1: am335x-evm:  Boot PASS: http://slexy.org/raw/s201YeK4dW
>  2:  am335x-sk:  Boot PASS: http://slexy.org/raw/s20nydiyVx
>  3: am3517-evm:  Boot PASS: http://slexy.org/raw/s2aTrenePo
>  4:  am437x-sk:  Boot FAIL: http://slexy.org/raw/s20NNiEa4W
>  5: am43xx-epos:  Boot PASS: http://slexy.org/raw/s2gghhhyOy
>  6: am43xx-gpevm:  Boot PASS: http://slexy.org/raw/s2LY4Cb75N
>  7: BeagleBoard-XM:  Boot PASS: http://slexy.org/raw/s2e8iJMUXu
>  8: beagleboard-vanilla:  Boot PASS: http://slexy.org/raw/s20wqxUmvr
>  9: beaglebone-black:  Boot PASS: http://slexy.org/raw/s21I0g2Ba3
> 10: beaglebone:  Boot PASS: http://slexy.org/raw/s2lpED0qW4
> 11: craneboard:  Boot PASS: http://slexy.org/raw/s230RKflY3
> 12: dra72x-evm:  Boot FAIL: http://slexy.org/raw/s21fWVnjaB
> 13: dra7xx-evm:  Boot PASS: http://slexy.org/raw/s20yEhfruO
> 14: OMAP3430-Labrador(LDP):  Boot PASS: http://slexy.org/raw/s20qZaXwz0
> 15:       n900:  Boot PASS: http://slexy.org/raw/s21LNTXZP7
> 16:  omap5-evm:  Boot PASS: http://slexy.org/raw/s2WF8eAcK2
> 17: pandaboard-es:  Boot PASS: http://slexy.org/raw/s21PVo7ENF
> 18: pandaboard-vanilla:  Boot PASS: http://slexy.org/raw/s2BcMbSrVF
> 19:    sdp2430:  Boot PASS: http://slexy.org/raw/s24LgXbav1
> 20:    sdp3430:  Boot PASS: http://slexy.org/raw/s21IaKdkUs
> TOTAL = 20 boards, Booted Boards = 18, No Boot boards = 2
> 
> 
> will try to first try and save a bit of cpufreq and reinstate my
> scripts and once you post based on 3.19-rc1, will do a retest..

Assuming you are yet to post a renewed revision with the vacation going
on.. :).. Hopefully this does not mess up Tony's plans for 3.20 queue.

-- 
Regards,
Nishanth Menon