* [PATCH v3 0/3] SoCFPGA: L3 NIC driver
@ 2014-11-29 20:14 Steffen Trumtrar
2014-11-29 20:14 ` [PATCH v3 1/3] Documentation: dt: add Altera L3 NIC bindings Steffen Trumtrar
` (5 more replies)
0 siblings, 6 replies; 20+ messages in thread
From: Steffen Trumtrar @ 2014-11-29 20:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi!
This series adds support for the SoCFPGA L3 NIC. As the memory range has
a lot of holes, where you can not read from, syscon can not be used for
this IP core. Instead add a new driver, that knows about all the allowed
ranges and guards the access via regmap.
Changes in v3:
- Split out the devicetree binding in its own patch
Regards,
Steffen
Steffen Trumtrar (3):
Documentation: dt: add Altera L3 NIC bindings
ARM: socfpga: Add driver for the L3 interconnect
ARM: dts: socfpga: Add l3nic node
.../bindings/soc/socfpga/altr,l3-nic.txt | 15 ++
arch/arm/boot/dts/socfpga.dtsi | 5 +
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/socfpga/Kconfig | 10 +
drivers/soc/socfpga/Makefile | 1 +
drivers/soc/socfpga/l3nic.c | 221 +++++++++++++++++++++
include/soc/socfpga/gpv.h | 63 ++++++
include/soc/socfpga/l3regs.h | 192 ++++++++++++++++++
9 files changed, 509 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt
create mode 100644 drivers/soc/socfpga/Kconfig
create mode 100644 drivers/soc/socfpga/Makefile
create mode 100644 drivers/soc/socfpga/l3nic.c
create mode 100644 include/soc/socfpga/gpv.h
create mode 100644 include/soc/socfpga/l3regs.h
--
2.1.3
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v3 1/3] Documentation: dt: add Altera L3 NIC bindings 2014-11-29 20:14 [PATCH v3 0/3] SoCFPGA: L3 NIC driver Steffen Trumtrar @ 2014-11-29 20:14 ` Steffen Trumtrar 2014-12-02 16:44 ` Dinh Nguyen 2014-11-29 20:14 ` [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect Steffen Trumtrar ` (4 subsequent siblings) 5 siblings, 1 reply; 20+ messages in thread From: Steffen Trumtrar @ 2014-11-29 20:14 UTC (permalink / raw) To: linux-arm-kernel Documentation for the Altera L3 networked interconnect found on the SoCFPGA architecture. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> --- .../devicetree/bindings/soc/socfpga/altr,l3-nic.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt diff --git a/Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt b/Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt new file mode 100644 index 000000000000..d9491f14eed3 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt @@ -0,0 +1,15 @@ +Altera SOCFPGA L3 Network Interconnect +-------------------------------------- + +The L3 NIC provides access to Global Programmer View (GPV) registers for all +AXI slaves and masters on the SoC. + +Required properties: +- compatible : "altr,l3-nic" +- reg : Should contain 1 register range (address and length) + +Example: + gpv at ff800000 { + compatible = "altr,l3-nic"; + reg = <0xff800000 0x100000>; + }; -- 2.1.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 1/3] Documentation: dt: add Altera L3 NIC bindings 2014-11-29 20:14 ` [PATCH v3 1/3] Documentation: dt: add Altera L3 NIC bindings Steffen Trumtrar @ 2014-12-02 16:44 ` Dinh Nguyen 0 siblings, 0 replies; 20+ messages in thread From: Dinh Nguyen @ 2014-12-02 16:44 UTC (permalink / raw) To: linux-arm-kernel +CC: Alan Tull On 11/29/2014 02:14 PM, Steffen Trumtrar wrote: > Documentation for the Altera L3 networked interconnect found on the > SoCFPGA architecture. > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > --- > .../devicetree/bindings/soc/socfpga/altr,l3-nic.txt | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt > > diff --git a/Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt b/Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt > new file mode 100644 > index 000000000000..d9491f14eed3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt > @@ -0,0 +1,15 @@ > +Altera SOCFPGA L3 Network Interconnect > +-------------------------------------- > + > +The L3 NIC provides access to Global Programmer View (GPV) registers for all > +AXI slaves and masters on the SoC. > + > +Required properties: > +- compatible : "altr,l3-nic" > +- reg : Should contain 1 register range (address and length) > + > +Example: > + gpv at ff800000 { > + compatible = "altr,l3-nic"; > + reg = <0xff800000 0x100000>; > + }; > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect 2014-11-29 20:14 [PATCH v3 0/3] SoCFPGA: L3 NIC driver Steffen Trumtrar 2014-11-29 20:14 ` [PATCH v3 1/3] Documentation: dt: add Altera L3 NIC bindings Steffen Trumtrar @ 2014-11-29 20:14 ` Steffen Trumtrar 2014-12-02 16:45 ` Dinh Nguyen 2014-12-15 22:34 ` Pavel Machek 2014-11-29 20:14 ` [PATCH v3 3/3] ARM: dts: socfpga: Add l3nic node Steffen Trumtrar ` (3 subsequent siblings) 5 siblings, 2 replies; 20+ messages in thread From: Steffen Trumtrar @ 2014-11-29 20:14 UTC (permalink / raw) To: linux-arm-kernel The L3 interconnect provides Global Programmer View (GPV) registers for every AXI master and slave on the SoC. Although this is just a bunch of bits, syscon is not the right approach for this IP core. The L3 interconnect is configured with a lot of reserved "holes" in its memory space. Just mapping this with regmap, what syscon would do, would lead to the system completely hanging, if one of those areas would be touched. One example for when this might happen is the regmap registers dump in the debugfs. This driver specifies also the valid readable and writable ranges of the L3 interconnect. Other drivers that want to access their GPV registers can do so with this driver via socfpga_l3nic_regmap_by_phandle. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/socfpga/Kconfig | 10 ++ drivers/soc/socfpga/Makefile | 1 + drivers/soc/socfpga/l3nic.c | 221 +++++++++++++++++++++++++++++++++++++++++++ include/soc/socfpga/gpv.h | 63 ++++++++++++ include/soc/socfpga/l3regs.h | 192 +++++++++++++++++++++++++++++++++++++ 7 files changed, 489 insertions(+) create mode 100644 drivers/soc/socfpga/Kconfig create mode 100644 drivers/soc/socfpga/Makefile create mode 100644 drivers/soc/socfpga/l3nic.c create mode 100644 include/soc/socfpga/gpv.h create mode 100644 include/soc/socfpga/l3regs.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 76d6bd4da138..11db07da894f 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -1,6 +1,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/qcom/Kconfig" +source "drivers/soc/socfpga/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/versatile/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 063113d0bd38..0f89173e328a 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_ARCH_QCOM) += qcom/ +obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_PLAT_VERSATILE) += versatile/ diff --git a/drivers/soc/socfpga/Kconfig b/drivers/soc/socfpga/Kconfig new file mode 100644 index 000000000000..533c59449fb8 --- /dev/null +++ b/drivers/soc/socfpga/Kconfig @@ -0,0 +1,10 @@ +# +# SoCFPGA Soc drivers +# + +config SOCFPGA_L3NIC + tristate "SoCFPGA L3 NIC-301 driver" + depends on ARCH_SOCFPGA + select REGMAP_MMIO + help + Enable configuration support for the SoCFPGA L3 AMBA Network Interconnect. diff --git a/drivers/soc/socfpga/Makefile b/drivers/soc/socfpga/Makefile new file mode 100644 index 000000000000..e6616d079226 --- /dev/null +++ b/drivers/soc/socfpga/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SOCFPGA_L3NIC) += l3nic.o diff --git a/drivers/soc/socfpga/l3nic.c b/drivers/soc/socfpga/l3nic.c new file mode 100644 index 000000000000..c1f36e2ec9cb --- /dev/null +++ b/drivers/soc/socfpga/l3nic.c @@ -0,0 +1,221 @@ +/* + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/types.h> +#include <soc/socfpga/gpv.h> +#include <soc/socfpga/l3regs.h> + +static const struct regmap_range l3nic_write_regs_range[] = { + regmap_reg_range(L3NIC_REMAP, L3NIC_REMAP), + regmap_reg_range(L3NIC_L4MAIN, L3NIC_LWHPS2FPGAREGS), + regmap_reg_range(L3NIC_USB1, L3NIC_NANDDATA), + regmap_reg_range(L3NIC_USB0, L3NIC_SDRDATA), + regmap_reg_range(L3NIC_L4_MAIN_FN_MOD_BM_ISS, L3NIC_L4_MAIN_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_L4_SP_FN_MOD_BM_ISS, L3NIC_L4_SP_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_L4_MP_FN_MOD_BM_ISS, L3NIC_L4_MP_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_L4_OSC1_FN_MOD_BM_ISS, L3NIC_L4_OSC1_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_L4_SPIM_FN_MOD_BM_ISS, L3NIC_L4_SPIM_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_STM_FN_MOD_BM_ISS, L3NIC_STM_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_STM_FN_MOD, L3NIC_STM_FN_MOD), + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS, L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD, L3NIC_LWHPS2FPGA_FN_MOD), + regmap_reg_range(L3NIC_USB1_FN_MOD_BM_ISS, L3NIC_USB1_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_USB1_AHB_CNTL, L3NIC_USB1_AHB_CNTL), + regmap_reg_range(L3NIC_NANDDATA_FN_MOD_BM_ISS, L3NIC_NANDDATA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_NANDDATA_FN_MOD, L3NIC_NANDDATA_FN_MOD), + regmap_reg_range(L3NIC_USB0_FN_MOD_BM_ISS, L3NIC_USB0_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_USB0_AHB_CNTL, L3NIC_USB0_AHB_CNTL), + regmap_reg_range(L3NIC_QSPIDATA_FN_MOD_BM_ISS, L3NIC_QSPIDATA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_QSPIDATA_AHB_CNTL, L3NIC_QSPIDATA_AHB_CNTL), + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS, L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_FPGAMGRDATA_WR_TIDEMARK, L3NIC_FPGAMGRDATA_WR_TIDEMARK), + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD, L3NIC_FPGAMGRDATA_FN_MOD), + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD_BM_ISS, L3NIC_HPS2FPGA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_HPS2FPGA_WR_TIDEMARK, L3NIC_HPS2FPGA_WR_TIDEMARK), + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD, L3NIC_HPS2FPGA_FN_MOD), + regmap_reg_range(L3NIC_ACP_FN_MOD_BM_ISS, L3NIC_ACP_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_ACP_FN_MOD, L3NIC_ACP_FN_MOD), + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD_BM_ISS, L3NIC_BOOT_ROM_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD, L3NIC_BOOT_ROM_FN_MOD), + regmap_reg_range(L3NIC_OCRAM_FN_MOD_BM_ISS, L3NIC_OCRAM_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_OCRAM_WR_TIDEMARK, L3NIC_OCRAM_WR_TIDEMARK), + regmap_reg_range(L3NIC_OCRAM_FN_MOD, L3NIC_OCRAM_FN_MOD), + regmap_reg_range(L3NIC_DAP_FN_MOD2, L3NIC_DAP_FN_MOD_AHB), + regmap_reg_range(L3NIC_DAP_READ_QOS, L3NIC_DAP_FN_MOD), + regmap_reg_range(L3NIC_MPU_READ_QOS, L3NIC_MPU_FN_MOD), + regmap_reg_range(L3NIC_SDMMC_FN_MOD_AHB, L3NIC_SDMMC_FN_MOD_AHB), + regmap_reg_range(L3NIC_SDMMC_READ_QOS, L3NIC_SDMMC_FN_MOD), + regmap_reg_range(L3NIC_DMA_READ_QOS, L3NIC_DMA_FN_MOD), + regmap_reg_range(L3NIC_FPGA2HPS_WR_TIDEMARK, L3NIC_FPGA2HPS_WR_TIDEMARK), + regmap_reg_range(L3NIC_FPGA2HPS_READ_QOS, L3NIC_FPGA2HPS_FN_MOD), + regmap_reg_range(L3NIC_ETR_READ_QOS, L3NIC_ETR_FN_MOD), + regmap_reg_range(L3NIC_EMAC0_READ_QOS, L3NIC_EMAC0_FN_MOD), + regmap_reg_range(L3NIC_EMAC1_READ_QOS, L3NIC_EMAC1_FN_MOD), + regmap_reg_range(L3NIC_USB0_FN_MOD_AHB, L3NIC_USB0_FN_MOD_AHB), + regmap_reg_range(L3NIC_USB0_READ_QOS, L3NIC_USB0_FN_MOD), + regmap_reg_range(L3NIC_NAND_READ_QOS, L3NIC_NAND_FN_MOD), + regmap_reg_range(L3NIC_USB1_FN_MOD_AHB, L3NIC_USB1_FN_MOD_AHB), + regmap_reg_range(L3NIC_USB1_READ_QOS, L3NIC_USB1_FN_MOD), +}; + +static const struct regmap_range l3nic_read_regs_range[] = { + regmap_reg_range(L3NIC_REMAP, L3NIC_REMAP), + + regmap_reg_range(L3NIC_PERIPH_ID_4, L3NIC_PERIPH_ID_4), + regmap_reg_range(L3NIC_PERIPH_ID_0, L3NIC_COMP_ID_3), + + regmap_reg_range(L3NIC_L4_MAIN_FN_MOD_BM_ISS, L3NIC_L4_MAIN_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_L4_SP_FN_MOD_BM_ISS, L3NIC_L4_SP_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_L4_MP_FN_MOD_BM_ISS, L3NIC_L4_MP_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_L4_OSC1_FN_MOD_BM_ISS, L3NIC_L4_OSC1_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_L4_SPIM_FN_MOD_BM_ISS, L3NIC_L4_SPIM_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_STM_FN_MOD_BM_ISS, L3NIC_STM_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_STM_FN_MOD, L3NIC_STM_FN_MOD), + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS, L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD, L3NIC_LWHPS2FPGA_FN_MOD), + regmap_reg_range(L3NIC_USB1_FN_MOD_BM_ISS, L3NIC_USB1_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_USB1_AHB_CNTL, L3NIC_USB1_AHB_CNTL), + regmap_reg_range(L3NIC_NANDDATA_FN_MOD_BM_ISS, L3NIC_NANDDATA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_NANDDATA_FN_MOD, L3NIC_NANDDATA_FN_MOD), + regmap_reg_range(L3NIC_USB0_FN_MOD_BM_ISS, L3NIC_USB0_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_USB0_AHB_CNTL, L3NIC_USB0_AHB_CNTL), + regmap_reg_range(L3NIC_QSPIDATA_FN_MOD_BM_ISS, L3NIC_QSPIDATA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_QSPIDATA_AHB_CNTL, L3NIC_QSPIDATA_AHB_CNTL), + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS, L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_FPGAMGRDATA_WR_TIDEMARK, L3NIC_FPGAMGRDATA_WR_TIDEMARK), + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD, L3NIC_FPGAMGRDATA_FN_MOD), + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD_BM_ISS, L3NIC_HPS2FPGA_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_HPS2FPGA_WR_TIDEMARK, L3NIC_HPS2FPGA_WR_TIDEMARK), + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD, L3NIC_HPS2FPGA_FN_MOD), + regmap_reg_range(L3NIC_ACP_FN_MOD_BM_ISS, L3NIC_ACP_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_ACP_FN_MOD, L3NIC_ACP_FN_MOD), + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD_BM_ISS, L3NIC_BOOT_ROM_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD, L3NIC_BOOT_ROM_FN_MOD), + regmap_reg_range(L3NIC_OCRAM_FN_MOD_BM_ISS, L3NIC_OCRAM_FN_MOD_BM_ISS), + regmap_reg_range(L3NIC_OCRAM_WR_TIDEMARK, L3NIC_OCRAM_WR_TIDEMARK), + regmap_reg_range(L3NIC_OCRAM_FN_MOD, L3NIC_OCRAM_FN_MOD), + regmap_reg_range(L3NIC_DAP_FN_MOD2, L3NIC_DAP_FN_MOD_AHB), + regmap_reg_range(L3NIC_DAP_READ_QOS, L3NIC_DAP_FN_MOD), + regmap_reg_range(L3NIC_MPU_READ_QOS, L3NIC_MPU_FN_MOD), + regmap_reg_range(L3NIC_SDMMC_FN_MOD_AHB, L3NIC_SDMMC_FN_MOD_AHB), + regmap_reg_range(L3NIC_SDMMC_READ_QOS, L3NIC_SDMMC_FN_MOD), + regmap_reg_range(L3NIC_DMA_READ_QOS, L3NIC_DMA_FN_MOD), + regmap_reg_range(L3NIC_FPGA2HPS_WR_TIDEMARK, L3NIC_FPGA2HPS_WR_TIDEMARK), + regmap_reg_range(L3NIC_FPGA2HPS_READ_QOS, L3NIC_FPGA2HPS_FN_MOD), + regmap_reg_range(L3NIC_ETR_READ_QOS, L3NIC_ETR_FN_MOD), + regmap_reg_range(L3NIC_EMAC0_READ_QOS, L3NIC_EMAC0_FN_MOD), + regmap_reg_range(L3NIC_EMAC1_READ_QOS, L3NIC_EMAC1_FN_MOD), + regmap_reg_range(L3NIC_USB0_FN_MOD_AHB, L3NIC_USB0_FN_MOD_AHB), + regmap_reg_range(L3NIC_USB0_READ_QOS, L3NIC_USB0_FN_MOD), + regmap_reg_range(L3NIC_NAND_READ_QOS, L3NIC_NAND_FN_MOD), + regmap_reg_range(L3NIC_USB1_FN_MOD_AHB, L3NIC_USB1_FN_MOD_AHB), + regmap_reg_range(L3NIC_USB1_READ_QOS, L3NIC_USB1_FN_MOD), +}; + +static const struct regmap_access_table l3nic_write_regs = { + .yes_ranges = l3nic_write_regs_range, + .n_yes_ranges = ARRAY_SIZE(l3nic_write_regs_range), +}; + +static const struct regmap_access_table l3nic_read_regs = { + .yes_ranges = l3nic_read_regs_range, + .n_yes_ranges = ARRAY_SIZE(l3nic_read_regs_range), +}; + +static struct regmap_config l3nic_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .rd_table = &l3nic_read_regs, + .wr_table = &l3nic_write_regs, + .cache_type = REGCACHE_RBTREE, +}; + +struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, + const char *name) +{ + struct socfpga_l3nic *l3nic; + struct platform_device *pdev; + + pdev = socfpga_gpv_device_by_phandle(np, name); + if (IS_ERR(pdev)) + return ERR_CAST(pdev); + + l3nic = dev_get_drvdata(&pdev->dev); + if (!l3nic) + return ERR_PTR(-EINVAL); + + if (l3nic->regmap) + return l3nic->regmap; + else + return ERR_PTR(-ENODEV); +} +EXPORT_SYMBOL_GPL(socfpga_l3nic_regmap_by_phandle); + +static int socfpga_l3nic_probe(struct platform_device *pdev) +{ + struct socfpga_l3nic *priv; + struct resource *res; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + l3nic_regmap_config.max_register = res->end - res->start - 3; + priv->regmap = devm_regmap_init_mmio(&pdev->dev, priv->base, + &l3nic_regmap_config); + if (IS_ERR(priv->regmap)) { + dev_err(&pdev->dev, "regmap init failed\n"); + return PTR_ERR(priv->regmap); + } + + platform_set_drvdata(pdev, priv); + + dev_info(&pdev->dev, "L3 NIC-301 registered\n"); + + return 0; +} + +static int socfpga_l3nic_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id socfpga_l3nic_dt_ids[] = { + { .compatible = "altr,l3-nic", }, + { /* sentinel */ }, +}; + +static struct platform_driver socfpga_l3nic_driver = { + .probe = socfpga_l3nic_probe, + .remove = socfpga_l3nic_remove, + .driver = { + .name = "socfpga-l3-nic", + .owner = THIS_MODULE, + .of_match_table = socfpga_l3nic_dt_ids, + }, +}; +module_platform_driver(socfpga_l3nic_driver); + +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar at pengutronix.de"); +MODULE_DESCRIPTION("Socfpga L3 NIC-301 Interconnect Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/soc/socfpga/gpv.h b/include/soc/socfpga/gpv.h new file mode 100644 index 000000000000..31bb555ea2c3 --- /dev/null +++ b/include/soc/socfpga/gpv.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __SOC_SOCFPGA_GPV_H__ +#define __SOC_SOCFPGA_GPV_H__ + +#ifdef CONFIG_ARCH_SOCFPGA + +#include <linux/device.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#define GPV_FN_MOD_BM_ISS_WR BIT(1) +#define GPV_FN_MOD_BM_ISS_RD BIT(0) +#define GPV_AHB_CNTL_FORCE_INCR BIT(1) +#define GPV_AHB_CNTL_DECERR_EN BIT(0) +#define GPV_WR_TIDEMARK_MASK 0xf +#define GPV_FN_MOD_AHB_WR_INCR_OVERRIDE BIT(1) +#define GPV_FN_MOD_AHB_RD_INCR_OVERRIDE BIT(0) +#define GPV_FN_MOD_WR BIT(1) +#define GPV_FN_MOD_RD BIT(0) +#define GPV_FN_MOD_BYPASS_MERGE BIT(0) +#define GPV_READ_QOS_MASK 0xf +#define GPV_WRITE_QOS_MASK 0xf + +static inline struct platform_device *socfpga_gpv_device_by_phandle( + struct device_node *np, + const char *name) +{ + struct device_node *gpv_np; + struct platform_device *pdev; + + gpv_np = of_parse_phandle(np, name, 0); + if (!gpv_np) + return ERR_PTR(-EINVAL); + + pdev = of_find_device_by_node(gpv_np); + + of_node_put(gpv_np); + + if (!pdev) + return ERR_PTR(-EPROBE_DEFER); + + return pdev; +} + +#else + +static struct platform_device *socfpga_gpv_device_by_phandle( + struct device_node *np, + const char *name) +{ + return ERR_PTR(-ENOSYS); +} + +#endif +#endif diff --git a/include/soc/socfpga/l3regs.h b/include/soc/socfpga/l3regs.h new file mode 100644 index 000000000000..bcdecd74bf17 --- /dev/null +++ b/include/soc/socfpga/l3regs.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __SOC_SOCFPGA_L3NIC_H__ +#define __SOC_SOCFPGA_L3NIC_H__ + +#ifdef CONFIG_ARCH_SOCFPGA + +#define L3NIC_REMAP 0x0 + +/* Security Registers */ + +#define L3NIC_L4MAIN 0x8 +#define L3NIC_L4SP 0xc +#define L3NIC_L4MP 0x10 +#define L3NIC_L4OSC1 0x14 +#define L3NIC_L4SPIM 0x18 +#define L3NIC_STM 0x1c +#define L3NIC_LWHPS2FPGAREGS 0x20 + +#define L3NIC_USB1 0x28 +#define L3NIC_NANDDATA 0x2c + +#define L3NIC_USB0 0x80 +#define L3NIC_NANDREGS 0x84 +#define L3NIC_QSPIDATA 0x88 +#define L3NIC_FPGAMGRDATA 0x8c +#define L3NIC_HPS2FPGAREGS 0x90 +#define L3NIC_ACP 0x94 +#define L3NIC_ROM 0x98 +#define L3NIC_OCRAM 0x9c +#define L3NIC_SDRDATA 0xa0 + +/* ID registers */ + +#define L3NIC_PERIPH_ID_4 0x1fd0 + +#define L3NIC_PERIPH_ID_0 0x1fe0 +#define L3NIC_PERIPH_ID_1 0x1fe4 +#define L3NIC_PERIPH_ID_2 0x1fe8 +#define L3NIC_PERIPH_ID_3 0x1fec +#define L3NIC_COMP_ID_0 0x1ff0 +#define L3NIC_COMP_ID_1 0x1ff4 +#define L3NIC_COMP_ID_2 0x1ff8 +#define L3NIC_COMP_ID_3 0x1ffc + +/* Master Registers */ + +#define L3NIC_L4_MAIN_FN_MOD_BM_ISS 0x2008 + +#define L3NIC_L4_SP_FN_MOD_BM_ISS 0x3008 + +#define L3NIC_L4_MP_FN_MOD_BM_ISS 0x4008 + +#define L3NIC_L4_OSC1_FN_MOD_BM_ISS 0x5008 + +#define L3NIC_L4_SPIM_FN_MOD_BM_ISS 0x6008 + +#define L3NIC_STM_FN_MOD_BM_ISS 0x7008 + +#define L3NIC_STM_FN_MOD 0x7108 + +#define L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS 0x8008 + +#define L3NIC_LWHPS2FPGA_FN_MOD 0x8108 + +#define L3NIC_USB1_FN_MOD_BM_ISS 0xa008 + +#define L3NIC_USB1_AHB_CNTL 0xa044 + +#define L3NIC_NANDDATA_FN_MOD_BM_ISS 0xb008 + +#define L3NIC_NANDDATA_FN_MOD 0xb108 + +#define L3NIC_USB0_FN_MOD_BM_ISS 0x20008 + +#define L3NIC_USB0_AHB_CNTL 0x20044 + +#define L3NIC_QSPIDATA_FN_MOD_BM_ISS 0x22008 + +#define L3NIC_QSPIDATA_AHB_CNTL 0x22044 + +#define L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS 0x23008 + +#define L3NIC_FPGAMGRDATA_WR_TIDEMARK 0x23040 + +#define L3NIC_FPGAMGRDATA_FN_MOD 0x23108 + +#define L3NIC_HPS2FPGA_FN_MOD_BM_ISS 0x24008 + +#define L3NIC_HPS2FPGA_WR_TIDEMARK 0x24040 + +#define L3NIC_HPS2FPGA_FN_MOD 0x24108 + +#define L3NIC_ACP_FN_MOD_BM_ISS 0x25008 + +#define L3NIC_ACP_FN_MOD 0x25108 + +#define L3NIC_BOOT_ROM_FN_MOD_BM_ISS 0x26008 + +#define L3NIC_BOOT_ROM_FN_MOD 0x26108 + +#define L3NIC_OCRAM_FN_MOD_BM_ISS 0x27008 + +#define L3NIC_OCRAM_WR_TIDEMARK 0x27040 + +#define L3NIC_OCRAM_FN_MOD 0x27108 + +/* Slave Registers */ + +#define L3NIC_DAP_FN_MOD2 0x42024 +#define L3NIC_DAP_FN_MOD_AHB 0x42028 + +#define L3NIC_DAP_READ_QOS 0x42100 +#define L3NIC_DAP_WRITE_QOS 0x42104 +#define L3NIC_DAP_FN_MOD 0x42108 + +#define L3NIC_MPU_READ_QOS 0x43100 +#define L3NIC_MPU_WRITE_QOS 0x43104 +#define L3NIC_MPU_FN_MOD 0x43108 + +#define L3NIC_SDMMC_FN_MOD_AHB 0x44028 + +#define L3NIC_SDMMC_READ_QOS 0x44100 +#define L3NIC_SDMMC_WRITE_QOS 0x44104 +#define L3NIC_SDMMC_FN_MOD 0x44108 + +#define L3NIC_DMA_READ_QOS 0x45100 +#define L3NIC_DMA_WRITE_QOS 0x45104 +#define L3NIC_DMA_FN_MOD 0x45108 + +#define L3NIC_FPGA2HPS_WR_TIDEMARK 0x46040 + +#define L3NIC_FPGA2HPS_READ_QOS 0x46100 +#define L3NIC_FPGA2HPS_WRITE_QOS 0x46104 +#define L3NIC_FPGA2HPS_FN_MOD 0x46108 + +#define L3NIC_ETR_READ_QOS 0x47100 +#define L3NIC_ETR_WRITE_QOS 0x47104 +#define L3NIC_ETR_FN_MOD 0x47108 + +#define L3NIC_EMAC0_READ_QOS 0x48100 +#define L3NIC_EMAC0_WRITE_QOS 0x48104 +#define L3NIC_EMAC0_FN_MOD 0x48108 + +#define L3NIC_EMAC1_READ_QOS 0x49100 +#define L3NIC_EMAC1_WRITE_QOS 0x49104 +#define L3NIC_EMAC1_FN_MOD 0x49108 + +#define L3NIC_USB0_FN_MOD_AHB 0x4a028 + +#define L3NIC_USB0_READ_QOS 0x4a100 +#define L3NIC_USB0_WRITE_QOS 0x4a104 +#define L3NIC_USB0_FN_MOD 0x4a108 + +#define L3NIC_NAND_READ_QOS 0x4b100 +#define L3NIC_NAND_WRITE_QOS 0x4b104 +#define L3NIC_NAND_FN_MOD 0x4b108 + +#define L3NIC_USB1_FN_MOD_AHB 0x4c028 + +#define L3NIC_USB1_READ_QOS 0x4c100 +#define L3NIC_USB1_WRITE_QOS 0x4c104 +#define L3NIC_USB1_FN_MOD 0x4c108 + +#define L3NIC_LWHPS2FPGA_VISIBILITY BIT(4) +#define L3NIC_HPS2FPGA_VISIBILITY BIT(3) + +struct socfpga_l3nic { + void __iomem *base; + struct regmap *regmap; +}; + +extern struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, + const char *name); + +#else + +struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, + const char *name) +{ + return ERR_PTR(-ENOSYS); +} + +#endif +#endif -- 2.1.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect 2014-11-29 20:14 ` [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect Steffen Trumtrar @ 2014-12-02 16:45 ` Dinh Nguyen 2014-12-05 19:51 ` atull 2014-12-15 22:34 ` Pavel Machek 1 sibling, 1 reply; 20+ messages in thread From: Dinh Nguyen @ 2014-12-02 16:45 UTC (permalink / raw) To: linux-arm-kernel +CC: Alan Tull On 11/29/2014 02:14 PM, Steffen Trumtrar wrote: > The L3 interconnect provides Global Programmer View (GPV) registers for every > AXI master and slave on the SoC. > Although this is just a bunch of bits, syscon is not the right approach for > this IP core. > The L3 interconnect is configured with a lot of reserved "holes" in its memory > space. Just mapping this with regmap, what syscon would do, would lead to the > system completely hanging, if one of those areas would be touched. > One example for when this might happen is the regmap registers dump in the > debugfs. > > This driver specifies also the valid readable and writable ranges of the L3 > interconnect. Other drivers that want to access their GPV registers can do > so with this driver via socfpga_l3nic_regmap_by_phandle. > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > --- > drivers/soc/Kconfig | 1 + > drivers/soc/Makefile | 1 + > drivers/soc/socfpga/Kconfig | 10 ++ > drivers/soc/socfpga/Makefile | 1 + > drivers/soc/socfpga/l3nic.c | 221 +++++++++++++++++++++++++++++++++++++++++++ > include/soc/socfpga/gpv.h | 63 ++++++++++++ > include/soc/socfpga/l3regs.h | 192 +++++++++++++++++++++++++++++++++++++ > 7 files changed, 489 insertions(+) > create mode 100644 drivers/soc/socfpga/Kconfig > create mode 100644 drivers/soc/socfpga/Makefile > create mode 100644 drivers/soc/socfpga/l3nic.c > create mode 100644 include/soc/socfpga/gpv.h > create mode 100644 include/soc/socfpga/l3regs.h > > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig > index 76d6bd4da138..11db07da894f 100644 > --- a/drivers/soc/Kconfig > +++ b/drivers/soc/Kconfig > @@ -1,6 +1,7 @@ > menu "SOC (System On Chip) specific Drivers" > > source "drivers/soc/qcom/Kconfig" > +source "drivers/soc/socfpga/Kconfig" > source "drivers/soc/ti/Kconfig" > source "drivers/soc/versatile/Kconfig" > > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > index 063113d0bd38..0f89173e328a 100644 > --- a/drivers/soc/Makefile > +++ b/drivers/soc/Makefile > @@ -3,6 +3,7 @@ > # > > obj-$(CONFIG_ARCH_QCOM) += qcom/ > +obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ > obj-$(CONFIG_ARCH_TEGRA) += tegra/ > obj-$(CONFIG_SOC_TI) += ti/ > obj-$(CONFIG_PLAT_VERSATILE) += versatile/ > diff --git a/drivers/soc/socfpga/Kconfig b/drivers/soc/socfpga/Kconfig > new file mode 100644 > index 000000000000..533c59449fb8 > --- /dev/null > +++ b/drivers/soc/socfpga/Kconfig > @@ -0,0 +1,10 @@ > +# > +# SoCFPGA Soc drivers > +# > + > +config SOCFPGA_L3NIC > + tristate "SoCFPGA L3 NIC-301 driver" > + depends on ARCH_SOCFPGA > + select REGMAP_MMIO > + help > + Enable configuration support for the SoCFPGA L3 AMBA Network Interconnect. > diff --git a/drivers/soc/socfpga/Makefile b/drivers/soc/socfpga/Makefile > new file mode 100644 > index 000000000000..e6616d079226 > --- /dev/null > +++ b/drivers/soc/socfpga/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_SOCFPGA_L3NIC) += l3nic.o > diff --git a/drivers/soc/socfpga/l3nic.c b/drivers/soc/socfpga/l3nic.c > new file mode 100644 > index 000000000000..c1f36e2ec9cb > --- /dev/null > +++ b/drivers/soc/socfpga/l3nic.c > @@ -0,0 +1,221 @@ > +/* > + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/types.h> > +#include <soc/socfpga/gpv.h> > +#include <soc/socfpga/l3regs.h> > + > +static const struct regmap_range l3nic_write_regs_range[] = { > + regmap_reg_range(L3NIC_REMAP, L3NIC_REMAP), > + regmap_reg_range(L3NIC_L4MAIN, L3NIC_LWHPS2FPGAREGS), > + regmap_reg_range(L3NIC_USB1, L3NIC_NANDDATA), > + regmap_reg_range(L3NIC_USB0, L3NIC_SDRDATA), > + regmap_reg_range(L3NIC_L4_MAIN_FN_MOD_BM_ISS, L3NIC_L4_MAIN_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_L4_SP_FN_MOD_BM_ISS, L3NIC_L4_SP_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_L4_MP_FN_MOD_BM_ISS, L3NIC_L4_MP_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_L4_OSC1_FN_MOD_BM_ISS, L3NIC_L4_OSC1_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_L4_SPIM_FN_MOD_BM_ISS, L3NIC_L4_SPIM_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_STM_FN_MOD_BM_ISS, L3NIC_STM_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_STM_FN_MOD, L3NIC_STM_FN_MOD), > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS, L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD, L3NIC_LWHPS2FPGA_FN_MOD), > + regmap_reg_range(L3NIC_USB1_FN_MOD_BM_ISS, L3NIC_USB1_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_USB1_AHB_CNTL, L3NIC_USB1_AHB_CNTL), > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD_BM_ISS, L3NIC_NANDDATA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD, L3NIC_NANDDATA_FN_MOD), > + regmap_reg_range(L3NIC_USB0_FN_MOD_BM_ISS, L3NIC_USB0_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_USB0_AHB_CNTL, L3NIC_USB0_AHB_CNTL), > + regmap_reg_range(L3NIC_QSPIDATA_FN_MOD_BM_ISS, L3NIC_QSPIDATA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_QSPIDATA_AHB_CNTL, L3NIC_QSPIDATA_AHB_CNTL), > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS, L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_FPGAMGRDATA_WR_TIDEMARK, L3NIC_FPGAMGRDATA_WR_TIDEMARK), > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD, L3NIC_FPGAMGRDATA_FN_MOD), > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD_BM_ISS, L3NIC_HPS2FPGA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_HPS2FPGA_WR_TIDEMARK, L3NIC_HPS2FPGA_WR_TIDEMARK), > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD, L3NIC_HPS2FPGA_FN_MOD), > + regmap_reg_range(L3NIC_ACP_FN_MOD_BM_ISS, L3NIC_ACP_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_ACP_FN_MOD, L3NIC_ACP_FN_MOD), > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD_BM_ISS, L3NIC_BOOT_ROM_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD, L3NIC_BOOT_ROM_FN_MOD), > + regmap_reg_range(L3NIC_OCRAM_FN_MOD_BM_ISS, L3NIC_OCRAM_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_OCRAM_WR_TIDEMARK, L3NIC_OCRAM_WR_TIDEMARK), > + regmap_reg_range(L3NIC_OCRAM_FN_MOD, L3NIC_OCRAM_FN_MOD), > + regmap_reg_range(L3NIC_DAP_FN_MOD2, L3NIC_DAP_FN_MOD_AHB), > + regmap_reg_range(L3NIC_DAP_READ_QOS, L3NIC_DAP_FN_MOD), > + regmap_reg_range(L3NIC_MPU_READ_QOS, L3NIC_MPU_FN_MOD), > + regmap_reg_range(L3NIC_SDMMC_FN_MOD_AHB, L3NIC_SDMMC_FN_MOD_AHB), > + regmap_reg_range(L3NIC_SDMMC_READ_QOS, L3NIC_SDMMC_FN_MOD), > + regmap_reg_range(L3NIC_DMA_READ_QOS, L3NIC_DMA_FN_MOD), > + regmap_reg_range(L3NIC_FPGA2HPS_WR_TIDEMARK, L3NIC_FPGA2HPS_WR_TIDEMARK), > + regmap_reg_range(L3NIC_FPGA2HPS_READ_QOS, L3NIC_FPGA2HPS_FN_MOD), > + regmap_reg_range(L3NIC_ETR_READ_QOS, L3NIC_ETR_FN_MOD), > + regmap_reg_range(L3NIC_EMAC0_READ_QOS, L3NIC_EMAC0_FN_MOD), > + regmap_reg_range(L3NIC_EMAC1_READ_QOS, L3NIC_EMAC1_FN_MOD), > + regmap_reg_range(L3NIC_USB0_FN_MOD_AHB, L3NIC_USB0_FN_MOD_AHB), > + regmap_reg_range(L3NIC_USB0_READ_QOS, L3NIC_USB0_FN_MOD), > + regmap_reg_range(L3NIC_NAND_READ_QOS, L3NIC_NAND_FN_MOD), > + regmap_reg_range(L3NIC_USB1_FN_MOD_AHB, L3NIC_USB1_FN_MOD_AHB), > + regmap_reg_range(L3NIC_USB1_READ_QOS, L3NIC_USB1_FN_MOD), > +}; > + > +static const struct regmap_range l3nic_read_regs_range[] = { > + regmap_reg_range(L3NIC_REMAP, L3NIC_REMAP), > + > + regmap_reg_range(L3NIC_PERIPH_ID_4, L3NIC_PERIPH_ID_4), > + regmap_reg_range(L3NIC_PERIPH_ID_0, L3NIC_COMP_ID_3), > + > + regmap_reg_range(L3NIC_L4_MAIN_FN_MOD_BM_ISS, L3NIC_L4_MAIN_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_L4_SP_FN_MOD_BM_ISS, L3NIC_L4_SP_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_L4_MP_FN_MOD_BM_ISS, L3NIC_L4_MP_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_L4_OSC1_FN_MOD_BM_ISS, L3NIC_L4_OSC1_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_L4_SPIM_FN_MOD_BM_ISS, L3NIC_L4_SPIM_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_STM_FN_MOD_BM_ISS, L3NIC_STM_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_STM_FN_MOD, L3NIC_STM_FN_MOD), > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS, L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD, L3NIC_LWHPS2FPGA_FN_MOD), > + regmap_reg_range(L3NIC_USB1_FN_MOD_BM_ISS, L3NIC_USB1_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_USB1_AHB_CNTL, L3NIC_USB1_AHB_CNTL), > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD_BM_ISS, L3NIC_NANDDATA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD, L3NIC_NANDDATA_FN_MOD), > + regmap_reg_range(L3NIC_USB0_FN_MOD_BM_ISS, L3NIC_USB0_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_USB0_AHB_CNTL, L3NIC_USB0_AHB_CNTL), > + regmap_reg_range(L3NIC_QSPIDATA_FN_MOD_BM_ISS, L3NIC_QSPIDATA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_QSPIDATA_AHB_CNTL, L3NIC_QSPIDATA_AHB_CNTL), > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS, L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_FPGAMGRDATA_WR_TIDEMARK, L3NIC_FPGAMGRDATA_WR_TIDEMARK), > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD, L3NIC_FPGAMGRDATA_FN_MOD), > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD_BM_ISS, L3NIC_HPS2FPGA_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_HPS2FPGA_WR_TIDEMARK, L3NIC_HPS2FPGA_WR_TIDEMARK), > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD, L3NIC_HPS2FPGA_FN_MOD), > + regmap_reg_range(L3NIC_ACP_FN_MOD_BM_ISS, L3NIC_ACP_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_ACP_FN_MOD, L3NIC_ACP_FN_MOD), > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD_BM_ISS, L3NIC_BOOT_ROM_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD, L3NIC_BOOT_ROM_FN_MOD), > + regmap_reg_range(L3NIC_OCRAM_FN_MOD_BM_ISS, L3NIC_OCRAM_FN_MOD_BM_ISS), > + regmap_reg_range(L3NIC_OCRAM_WR_TIDEMARK, L3NIC_OCRAM_WR_TIDEMARK), > + regmap_reg_range(L3NIC_OCRAM_FN_MOD, L3NIC_OCRAM_FN_MOD), > + regmap_reg_range(L3NIC_DAP_FN_MOD2, L3NIC_DAP_FN_MOD_AHB), > + regmap_reg_range(L3NIC_DAP_READ_QOS, L3NIC_DAP_FN_MOD), > + regmap_reg_range(L3NIC_MPU_READ_QOS, L3NIC_MPU_FN_MOD), > + regmap_reg_range(L3NIC_SDMMC_FN_MOD_AHB, L3NIC_SDMMC_FN_MOD_AHB), > + regmap_reg_range(L3NIC_SDMMC_READ_QOS, L3NIC_SDMMC_FN_MOD), > + regmap_reg_range(L3NIC_DMA_READ_QOS, L3NIC_DMA_FN_MOD), > + regmap_reg_range(L3NIC_FPGA2HPS_WR_TIDEMARK, L3NIC_FPGA2HPS_WR_TIDEMARK), > + regmap_reg_range(L3NIC_FPGA2HPS_READ_QOS, L3NIC_FPGA2HPS_FN_MOD), > + regmap_reg_range(L3NIC_ETR_READ_QOS, L3NIC_ETR_FN_MOD), > + regmap_reg_range(L3NIC_EMAC0_READ_QOS, L3NIC_EMAC0_FN_MOD), > + regmap_reg_range(L3NIC_EMAC1_READ_QOS, L3NIC_EMAC1_FN_MOD), > + regmap_reg_range(L3NIC_USB0_FN_MOD_AHB, L3NIC_USB0_FN_MOD_AHB), > + regmap_reg_range(L3NIC_USB0_READ_QOS, L3NIC_USB0_FN_MOD), > + regmap_reg_range(L3NIC_NAND_READ_QOS, L3NIC_NAND_FN_MOD), > + regmap_reg_range(L3NIC_USB1_FN_MOD_AHB, L3NIC_USB1_FN_MOD_AHB), > + regmap_reg_range(L3NIC_USB1_READ_QOS, L3NIC_USB1_FN_MOD), > +}; > + > +static const struct regmap_access_table l3nic_write_regs = { > + .yes_ranges = l3nic_write_regs_range, > + .n_yes_ranges = ARRAY_SIZE(l3nic_write_regs_range), > +}; > + > +static const struct regmap_access_table l3nic_read_regs = { > + .yes_ranges = l3nic_read_regs_range, > + .n_yes_ranges = ARRAY_SIZE(l3nic_read_regs_range), > +}; > + > +static struct regmap_config l3nic_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > + .rd_table = &l3nic_read_regs, > + .wr_table = &l3nic_write_regs, > + .cache_type = REGCACHE_RBTREE, > +}; > + > +struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, > + const char *name) > +{ > + struct socfpga_l3nic *l3nic; > + struct platform_device *pdev; > + > + pdev = socfpga_gpv_device_by_phandle(np, name); > + if (IS_ERR(pdev)) > + return ERR_CAST(pdev); > + > + l3nic = dev_get_drvdata(&pdev->dev); > + if (!l3nic) > + return ERR_PTR(-EINVAL); > + > + if (l3nic->regmap) > + return l3nic->regmap; > + else > + return ERR_PTR(-ENODEV); > +} > +EXPORT_SYMBOL_GPL(socfpga_l3nic_regmap_by_phandle); > + > +static int socfpga_l3nic_probe(struct platform_device *pdev) > +{ > + struct socfpga_l3nic *priv; > + struct resource *res; > + > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(priv->base)) > + return PTR_ERR(priv->base); > + > + l3nic_regmap_config.max_register = res->end - res->start - 3; > + priv->regmap = devm_regmap_init_mmio(&pdev->dev, priv->base, > + &l3nic_regmap_config); > + if (IS_ERR(priv->regmap)) { > + dev_err(&pdev->dev, "regmap init failed\n"); > + return PTR_ERR(priv->regmap); > + } > + > + platform_set_drvdata(pdev, priv); > + > + dev_info(&pdev->dev, "L3 NIC-301 registered\n"); > + > + return 0; > +} > + > +static int socfpga_l3nic_remove(struct platform_device *pdev) > +{ > + return 0; > +} > + > +static const struct of_device_id socfpga_l3nic_dt_ids[] = { > + { .compatible = "altr,l3-nic", }, > + { /* sentinel */ }, > +}; > + > +static struct platform_driver socfpga_l3nic_driver = { > + .probe = socfpga_l3nic_probe, > + .remove = socfpga_l3nic_remove, > + .driver = { > + .name = "socfpga-l3-nic", > + .owner = THIS_MODULE, > + .of_match_table = socfpga_l3nic_dt_ids, > + }, > +}; > +module_platform_driver(socfpga_l3nic_driver); > + > +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de"); > +MODULE_DESCRIPTION("Socfpga L3 NIC-301 Interconnect Driver"); > +MODULE_LICENSE("GPL v2"); > diff --git a/include/soc/socfpga/gpv.h b/include/soc/socfpga/gpv.h > new file mode 100644 > index 000000000000..31bb555ea2c3 > --- /dev/null > +++ b/include/soc/socfpga/gpv.h > @@ -0,0 +1,63 @@ > +/* > + * Copyright (c) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#ifndef __SOC_SOCFPGA_GPV_H__ > +#define __SOC_SOCFPGA_GPV_H__ > + > +#ifdef CONFIG_ARCH_SOCFPGA > + > +#include <linux/device.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > + > +#define GPV_FN_MOD_BM_ISS_WR BIT(1) > +#define GPV_FN_MOD_BM_ISS_RD BIT(0) > +#define GPV_AHB_CNTL_FORCE_INCR BIT(1) > +#define GPV_AHB_CNTL_DECERR_EN BIT(0) > +#define GPV_WR_TIDEMARK_MASK 0xf > +#define GPV_FN_MOD_AHB_WR_INCR_OVERRIDE BIT(1) > +#define GPV_FN_MOD_AHB_RD_INCR_OVERRIDE BIT(0) > +#define GPV_FN_MOD_WR BIT(1) > +#define GPV_FN_MOD_RD BIT(0) > +#define GPV_FN_MOD_BYPASS_MERGE BIT(0) > +#define GPV_READ_QOS_MASK 0xf > +#define GPV_WRITE_QOS_MASK 0xf > + > +static inline struct platform_device *socfpga_gpv_device_by_phandle( > + struct device_node *np, > + const char *name) > +{ > + struct device_node *gpv_np; > + struct platform_device *pdev; > + > + gpv_np = of_parse_phandle(np, name, 0); > + if (!gpv_np) > + return ERR_PTR(-EINVAL); > + > + pdev = of_find_device_by_node(gpv_np); > + > + of_node_put(gpv_np); > + > + if (!pdev) > + return ERR_PTR(-EPROBE_DEFER); > + > + return pdev; > +} > + > +#else > + > +static struct platform_device *socfpga_gpv_device_by_phandle( > + struct device_node *np, > + const char *name) > +{ > + return ERR_PTR(-ENOSYS); > +} > + > +#endif > +#endif > diff --git a/include/soc/socfpga/l3regs.h b/include/soc/socfpga/l3regs.h > new file mode 100644 > index 000000000000..bcdecd74bf17 > --- /dev/null > +++ b/include/soc/socfpga/l3regs.h > @@ -0,0 +1,192 @@ > +/* > + * Copyright (c) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#ifndef __SOC_SOCFPGA_L3NIC_H__ > +#define __SOC_SOCFPGA_L3NIC_H__ > + > +#ifdef CONFIG_ARCH_SOCFPGA > + > +#define L3NIC_REMAP 0x0 > + > +/* Security Registers */ > + > +#define L3NIC_L4MAIN 0x8 > +#define L3NIC_L4SP 0xc > +#define L3NIC_L4MP 0x10 > +#define L3NIC_L4OSC1 0x14 > +#define L3NIC_L4SPIM 0x18 > +#define L3NIC_STM 0x1c > +#define L3NIC_LWHPS2FPGAREGS 0x20 > + > +#define L3NIC_USB1 0x28 > +#define L3NIC_NANDDATA 0x2c > + > +#define L3NIC_USB0 0x80 > +#define L3NIC_NANDREGS 0x84 > +#define L3NIC_QSPIDATA 0x88 > +#define L3NIC_FPGAMGRDATA 0x8c > +#define L3NIC_HPS2FPGAREGS 0x90 > +#define L3NIC_ACP 0x94 > +#define L3NIC_ROM 0x98 > +#define L3NIC_OCRAM 0x9c > +#define L3NIC_SDRDATA 0xa0 > + > +/* ID registers */ > + > +#define L3NIC_PERIPH_ID_4 0x1fd0 > + > +#define L3NIC_PERIPH_ID_0 0x1fe0 > +#define L3NIC_PERIPH_ID_1 0x1fe4 > +#define L3NIC_PERIPH_ID_2 0x1fe8 > +#define L3NIC_PERIPH_ID_3 0x1fec > +#define L3NIC_COMP_ID_0 0x1ff0 > +#define L3NIC_COMP_ID_1 0x1ff4 > +#define L3NIC_COMP_ID_2 0x1ff8 > +#define L3NIC_COMP_ID_3 0x1ffc > + > +/* Master Registers */ > + > +#define L3NIC_L4_MAIN_FN_MOD_BM_ISS 0x2008 > + > +#define L3NIC_L4_SP_FN_MOD_BM_ISS 0x3008 > + > +#define L3NIC_L4_MP_FN_MOD_BM_ISS 0x4008 > + > +#define L3NIC_L4_OSC1_FN_MOD_BM_ISS 0x5008 > + > +#define L3NIC_L4_SPIM_FN_MOD_BM_ISS 0x6008 > + > +#define L3NIC_STM_FN_MOD_BM_ISS 0x7008 > + > +#define L3NIC_STM_FN_MOD 0x7108 > + > +#define L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS 0x8008 > + > +#define L3NIC_LWHPS2FPGA_FN_MOD 0x8108 > + > +#define L3NIC_USB1_FN_MOD_BM_ISS 0xa008 > + > +#define L3NIC_USB1_AHB_CNTL 0xa044 > + > +#define L3NIC_NANDDATA_FN_MOD_BM_ISS 0xb008 > + > +#define L3NIC_NANDDATA_FN_MOD 0xb108 > + > +#define L3NIC_USB0_FN_MOD_BM_ISS 0x20008 > + > +#define L3NIC_USB0_AHB_CNTL 0x20044 > + > +#define L3NIC_QSPIDATA_FN_MOD_BM_ISS 0x22008 > + > +#define L3NIC_QSPIDATA_AHB_CNTL 0x22044 > + > +#define L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS 0x23008 > + > +#define L3NIC_FPGAMGRDATA_WR_TIDEMARK 0x23040 > + > +#define L3NIC_FPGAMGRDATA_FN_MOD 0x23108 > + > +#define L3NIC_HPS2FPGA_FN_MOD_BM_ISS 0x24008 > + > +#define L3NIC_HPS2FPGA_WR_TIDEMARK 0x24040 > + > +#define L3NIC_HPS2FPGA_FN_MOD 0x24108 > + > +#define L3NIC_ACP_FN_MOD_BM_ISS 0x25008 > + > +#define L3NIC_ACP_FN_MOD 0x25108 > + > +#define L3NIC_BOOT_ROM_FN_MOD_BM_ISS 0x26008 > + > +#define L3NIC_BOOT_ROM_FN_MOD 0x26108 > + > +#define L3NIC_OCRAM_FN_MOD_BM_ISS 0x27008 > + > +#define L3NIC_OCRAM_WR_TIDEMARK 0x27040 > + > +#define L3NIC_OCRAM_FN_MOD 0x27108 > + > +/* Slave Registers */ > + > +#define L3NIC_DAP_FN_MOD2 0x42024 > +#define L3NIC_DAP_FN_MOD_AHB 0x42028 > + > +#define L3NIC_DAP_READ_QOS 0x42100 > +#define L3NIC_DAP_WRITE_QOS 0x42104 > +#define L3NIC_DAP_FN_MOD 0x42108 > + > +#define L3NIC_MPU_READ_QOS 0x43100 > +#define L3NIC_MPU_WRITE_QOS 0x43104 > +#define L3NIC_MPU_FN_MOD 0x43108 > + > +#define L3NIC_SDMMC_FN_MOD_AHB 0x44028 > + > +#define L3NIC_SDMMC_READ_QOS 0x44100 > +#define L3NIC_SDMMC_WRITE_QOS 0x44104 > +#define L3NIC_SDMMC_FN_MOD 0x44108 > + > +#define L3NIC_DMA_READ_QOS 0x45100 > +#define L3NIC_DMA_WRITE_QOS 0x45104 > +#define L3NIC_DMA_FN_MOD 0x45108 > + > +#define L3NIC_FPGA2HPS_WR_TIDEMARK 0x46040 > + > +#define L3NIC_FPGA2HPS_READ_QOS 0x46100 > +#define L3NIC_FPGA2HPS_WRITE_QOS 0x46104 > +#define L3NIC_FPGA2HPS_FN_MOD 0x46108 > + > +#define L3NIC_ETR_READ_QOS 0x47100 > +#define L3NIC_ETR_WRITE_QOS 0x47104 > +#define L3NIC_ETR_FN_MOD 0x47108 > + > +#define L3NIC_EMAC0_READ_QOS 0x48100 > +#define L3NIC_EMAC0_WRITE_QOS 0x48104 > +#define L3NIC_EMAC0_FN_MOD 0x48108 > + > +#define L3NIC_EMAC1_READ_QOS 0x49100 > +#define L3NIC_EMAC1_WRITE_QOS 0x49104 > +#define L3NIC_EMAC1_FN_MOD 0x49108 > + > +#define L3NIC_USB0_FN_MOD_AHB 0x4a028 > + > +#define L3NIC_USB0_READ_QOS 0x4a100 > +#define L3NIC_USB0_WRITE_QOS 0x4a104 > +#define L3NIC_USB0_FN_MOD 0x4a108 > + > +#define L3NIC_NAND_READ_QOS 0x4b100 > +#define L3NIC_NAND_WRITE_QOS 0x4b104 > +#define L3NIC_NAND_FN_MOD 0x4b108 > + > +#define L3NIC_USB1_FN_MOD_AHB 0x4c028 > + > +#define L3NIC_USB1_READ_QOS 0x4c100 > +#define L3NIC_USB1_WRITE_QOS 0x4c104 > +#define L3NIC_USB1_FN_MOD 0x4c108 > + > +#define L3NIC_LWHPS2FPGA_VISIBILITY BIT(4) > +#define L3NIC_HPS2FPGA_VISIBILITY BIT(3) > + > +struct socfpga_l3nic { > + void __iomem *base; > + struct regmap *regmap; > +}; > + > +extern struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, > + const char *name); > + > +#else > + > +struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, > + const char *name) > +{ > + return ERR_PTR(-ENOSYS); > +} > + > +#endif > +#endif > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect 2014-12-02 16:45 ` Dinh Nguyen @ 2014-12-05 19:51 ` atull 2014-12-05 20:19 ` Steffen Trumtrar 0 siblings, 1 reply; 20+ messages in thread From: atull @ 2014-12-05 19:51 UTC (permalink / raw) To: linux-arm-kernel On Tue, 2 Dec 2014, Dinh Nguyen wrote: > +CC: Alan Tull > > On 11/29/2014 02:14 PM, Steffen Trumtrar wrote: > > The L3 interconnect provides Global Programmer View (GPV) registers for every > > AXI master and slave on the SoC. > > Although this is just a bunch of bits, syscon is not the right approach for > > this IP core. > > The L3 interconnect is configured with a lot of reserved "holes" in its memory > > space. Just mapping this with regmap, what syscon would do, would lead to the > > system completely hanging, if one of those areas would be touched. > > One example for when this might happen is the regmap registers dump in the > > debugfs. > > > > This driver specifies also the valid readable and writable ranges of the L3 > > interconnect. Other drivers that want to access their GPV registers can do > > so with this driver via socfpga_l3nic_regmap_by_phandle. > > > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > > --- > > drivers/soc/Kconfig | 1 + > > drivers/soc/Makefile | 1 + > > drivers/soc/socfpga/Kconfig | 10 ++ > > drivers/soc/socfpga/Makefile | 1 + > > drivers/soc/socfpga/l3nic.c | 221 +++++++++++++++++++++++++++++++++++++++++++ > > include/soc/socfpga/gpv.h | 63 ++++++++++++ > > include/soc/socfpga/l3regs.h | 192 +++++++++++++++++++++++++++++++++++++ > > 7 files changed, 489 insertions(+) > > create mode 100644 drivers/soc/socfpga/Kconfig > > create mode 100644 drivers/soc/socfpga/Makefile > > create mode 100644 drivers/soc/socfpga/l3nic.c > > create mode 100644 include/soc/socfpga/gpv.h > > create mode 100644 include/soc/socfpga/l3regs.h > > > > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig > > index 76d6bd4da138..11db07da894f 100644 > > --- a/drivers/soc/Kconfig > > +++ b/drivers/soc/Kconfig > > @@ -1,6 +1,7 @@ > > menu "SOC (System On Chip) specific Drivers" > > > > source "drivers/soc/qcom/Kconfig" > > +source "drivers/soc/socfpga/Kconfig" > > source "drivers/soc/ti/Kconfig" > > source "drivers/soc/versatile/Kconfig" > > > > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > > index 063113d0bd38..0f89173e328a 100644 > > --- a/drivers/soc/Makefile > > +++ b/drivers/soc/Makefile > > @@ -3,6 +3,7 @@ > > # > > > > obj-$(CONFIG_ARCH_QCOM) += qcom/ > > +obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ > > obj-$(CONFIG_ARCH_TEGRA) += tegra/ > > obj-$(CONFIG_SOC_TI) += ti/ > > obj-$(CONFIG_PLAT_VERSATILE) += versatile/ > > diff --git a/drivers/soc/socfpga/Kconfig b/drivers/soc/socfpga/Kconfig > > new file mode 100644 > > index 000000000000..533c59449fb8 > > --- /dev/null > > +++ b/drivers/soc/socfpga/Kconfig > > @@ -0,0 +1,10 @@ > > +# > > +# SoCFPGA Soc drivers > > +# > > + > > +config SOCFPGA_L3NIC > > + tristate "SoCFPGA L3 NIC-301 driver" > > + depends on ARCH_SOCFPGA > > + select REGMAP_MMIO > > + help > > + Enable configuration support for the SoCFPGA L3 AMBA Network Interconnect. > > diff --git a/drivers/soc/socfpga/Makefile b/drivers/soc/socfpga/Makefile > > new file mode 100644 > > index 000000000000..e6616d079226 > > --- /dev/null > > +++ b/drivers/soc/socfpga/Makefile > > @@ -0,0 +1 @@ > > +obj-$(CONFIG_SOCFPGA_L3NIC) += l3nic.o > > diff --git a/drivers/soc/socfpga/l3nic.c b/drivers/soc/socfpga/l3nic.c > > new file mode 100644 > > index 000000000000..c1f36e2ec9cb > > --- /dev/null > > +++ b/drivers/soc/socfpga/l3nic.c > > @@ -0,0 +1,221 @@ > > +/* > > + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as published by > > + * the Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + */ > > + > > +#include <linux/clk.h> > > +#include <linux/err.h> > > +#include <linux/io.h> > > +#include <linux/module.h> > > +#include <linux/of.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/regmap.h> > > +#include <linux/types.h> > > +#include <soc/socfpga/gpv.h> > > +#include <soc/socfpga/l3regs.h> > > + > > +static const struct regmap_range l3nic_write_regs_range[] = { > > + regmap_reg_range(L3NIC_REMAP, L3NIC_REMAP), > > + regmap_reg_range(L3NIC_L4MAIN, L3NIC_LWHPS2FPGAREGS), > > + regmap_reg_range(L3NIC_USB1, L3NIC_NANDDATA), > > + regmap_reg_range(L3NIC_USB0, L3NIC_SDRDATA), > > + regmap_reg_range(L3NIC_L4_MAIN_FN_MOD_BM_ISS, L3NIC_L4_MAIN_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_L4_SP_FN_MOD_BM_ISS, L3NIC_L4_SP_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_L4_MP_FN_MOD_BM_ISS, L3NIC_L4_MP_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_L4_OSC1_FN_MOD_BM_ISS, L3NIC_L4_OSC1_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_L4_SPIM_FN_MOD_BM_ISS, L3NIC_L4_SPIM_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_STM_FN_MOD_BM_ISS, L3NIC_STM_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_STM_FN_MOD, L3NIC_STM_FN_MOD), > > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS, L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD, L3NIC_LWHPS2FPGA_FN_MOD), > > + regmap_reg_range(L3NIC_USB1_FN_MOD_BM_ISS, L3NIC_USB1_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_USB1_AHB_CNTL, L3NIC_USB1_AHB_CNTL), > > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD_BM_ISS, L3NIC_NANDDATA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD, L3NIC_NANDDATA_FN_MOD), > > + regmap_reg_range(L3NIC_USB0_FN_MOD_BM_ISS, L3NIC_USB0_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_USB0_AHB_CNTL, L3NIC_USB0_AHB_CNTL), > > + regmap_reg_range(L3NIC_QSPIDATA_FN_MOD_BM_ISS, L3NIC_QSPIDATA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_QSPIDATA_AHB_CNTL, L3NIC_QSPIDATA_AHB_CNTL), > > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS, L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_FPGAMGRDATA_WR_TIDEMARK, L3NIC_FPGAMGRDATA_WR_TIDEMARK), > > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD, L3NIC_FPGAMGRDATA_FN_MOD), > > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD_BM_ISS, L3NIC_HPS2FPGA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_HPS2FPGA_WR_TIDEMARK, L3NIC_HPS2FPGA_WR_TIDEMARK), > > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD, L3NIC_HPS2FPGA_FN_MOD), > > + regmap_reg_range(L3NIC_ACP_FN_MOD_BM_ISS, L3NIC_ACP_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_ACP_FN_MOD, L3NIC_ACP_FN_MOD), > > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD_BM_ISS, L3NIC_BOOT_ROM_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD, L3NIC_BOOT_ROM_FN_MOD), > > + regmap_reg_range(L3NIC_OCRAM_FN_MOD_BM_ISS, L3NIC_OCRAM_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_OCRAM_WR_TIDEMARK, L3NIC_OCRAM_WR_TIDEMARK), > > + regmap_reg_range(L3NIC_OCRAM_FN_MOD, L3NIC_OCRAM_FN_MOD), > > + regmap_reg_range(L3NIC_DAP_FN_MOD2, L3NIC_DAP_FN_MOD_AHB), > > + regmap_reg_range(L3NIC_DAP_READ_QOS, L3NIC_DAP_FN_MOD), > > + regmap_reg_range(L3NIC_MPU_READ_QOS, L3NIC_MPU_FN_MOD), > > + regmap_reg_range(L3NIC_SDMMC_FN_MOD_AHB, L3NIC_SDMMC_FN_MOD_AHB), > > + regmap_reg_range(L3NIC_SDMMC_READ_QOS, L3NIC_SDMMC_FN_MOD), > > + regmap_reg_range(L3NIC_DMA_READ_QOS, L3NIC_DMA_FN_MOD), > > + regmap_reg_range(L3NIC_FPGA2HPS_WR_TIDEMARK, L3NIC_FPGA2HPS_WR_TIDEMARK), > > + regmap_reg_range(L3NIC_FPGA2HPS_READ_QOS, L3NIC_FPGA2HPS_FN_MOD), > > + regmap_reg_range(L3NIC_ETR_READ_QOS, L3NIC_ETR_FN_MOD), > > + regmap_reg_range(L3NIC_EMAC0_READ_QOS, L3NIC_EMAC0_FN_MOD), > > + regmap_reg_range(L3NIC_EMAC1_READ_QOS, L3NIC_EMAC1_FN_MOD), > > + regmap_reg_range(L3NIC_USB0_FN_MOD_AHB, L3NIC_USB0_FN_MOD_AHB), > > + regmap_reg_range(L3NIC_USB0_READ_QOS, L3NIC_USB0_FN_MOD), > > + regmap_reg_range(L3NIC_NAND_READ_QOS, L3NIC_NAND_FN_MOD), > > + regmap_reg_range(L3NIC_USB1_FN_MOD_AHB, L3NIC_USB1_FN_MOD_AHB), > > + regmap_reg_range(L3NIC_USB1_READ_QOS, L3NIC_USB1_FN_MOD), > > +}; > > + > > +static const struct regmap_range l3nic_read_regs_range[] = { > > + regmap_reg_range(L3NIC_REMAP, L3NIC_REMAP), Hi Steffen, We may have discussed this a bit, but I want to make sure that this is made obvious here: some of these registers are not readable. L3NIC_REMAP is one of these for example. So please mark the appropriate registers as not being readable. Then anyone who does a regmap_update_bits() will get an error, which is what we want. It would probably be good to add a note to the patch header warning people that some of these regs are write-only. I also would request that you post future versions, please keep me and all the other people who originally had replied to v1, v2, etc in the cc. Alan > > + > > + regmap_reg_range(L3NIC_PERIPH_ID_4, L3NIC_PERIPH_ID_4), > > + regmap_reg_range(L3NIC_PERIPH_ID_0, L3NIC_COMP_ID_3), > > + > > + regmap_reg_range(L3NIC_L4_MAIN_FN_MOD_BM_ISS, L3NIC_L4_MAIN_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_L4_SP_FN_MOD_BM_ISS, L3NIC_L4_SP_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_L4_MP_FN_MOD_BM_ISS, L3NIC_L4_MP_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_L4_OSC1_FN_MOD_BM_ISS, L3NIC_L4_OSC1_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_L4_SPIM_FN_MOD_BM_ISS, L3NIC_L4_SPIM_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_STM_FN_MOD_BM_ISS, L3NIC_STM_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_STM_FN_MOD, L3NIC_STM_FN_MOD), > > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS, L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD, L3NIC_LWHPS2FPGA_FN_MOD), > > + regmap_reg_range(L3NIC_USB1_FN_MOD_BM_ISS, L3NIC_USB1_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_USB1_AHB_CNTL, L3NIC_USB1_AHB_CNTL), > > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD_BM_ISS, L3NIC_NANDDATA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD, L3NIC_NANDDATA_FN_MOD), > > + regmap_reg_range(L3NIC_USB0_FN_MOD_BM_ISS, L3NIC_USB0_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_USB0_AHB_CNTL, L3NIC_USB0_AHB_CNTL), > > + regmap_reg_range(L3NIC_QSPIDATA_FN_MOD_BM_ISS, L3NIC_QSPIDATA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_QSPIDATA_AHB_CNTL, L3NIC_QSPIDATA_AHB_CNTL), > > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS, L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_FPGAMGRDATA_WR_TIDEMARK, L3NIC_FPGAMGRDATA_WR_TIDEMARK), > > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD, L3NIC_FPGAMGRDATA_FN_MOD), > > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD_BM_ISS, L3NIC_HPS2FPGA_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_HPS2FPGA_WR_TIDEMARK, L3NIC_HPS2FPGA_WR_TIDEMARK), > > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD, L3NIC_HPS2FPGA_FN_MOD), > > + regmap_reg_range(L3NIC_ACP_FN_MOD_BM_ISS, L3NIC_ACP_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_ACP_FN_MOD, L3NIC_ACP_FN_MOD), > > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD_BM_ISS, L3NIC_BOOT_ROM_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD, L3NIC_BOOT_ROM_FN_MOD), > > + regmap_reg_range(L3NIC_OCRAM_FN_MOD_BM_ISS, L3NIC_OCRAM_FN_MOD_BM_ISS), > > + regmap_reg_range(L3NIC_OCRAM_WR_TIDEMARK, L3NIC_OCRAM_WR_TIDEMARK), > > + regmap_reg_range(L3NIC_OCRAM_FN_MOD, L3NIC_OCRAM_FN_MOD), > > + regmap_reg_range(L3NIC_DAP_FN_MOD2, L3NIC_DAP_FN_MOD_AHB), > > + regmap_reg_range(L3NIC_DAP_READ_QOS, L3NIC_DAP_FN_MOD), > > + regmap_reg_range(L3NIC_MPU_READ_QOS, L3NIC_MPU_FN_MOD), > > + regmap_reg_range(L3NIC_SDMMC_FN_MOD_AHB, L3NIC_SDMMC_FN_MOD_AHB), > > + regmap_reg_range(L3NIC_SDMMC_READ_QOS, L3NIC_SDMMC_FN_MOD), > > + regmap_reg_range(L3NIC_DMA_READ_QOS, L3NIC_DMA_FN_MOD), > > + regmap_reg_range(L3NIC_FPGA2HPS_WR_TIDEMARK, L3NIC_FPGA2HPS_WR_TIDEMARK), > > + regmap_reg_range(L3NIC_FPGA2HPS_READ_QOS, L3NIC_FPGA2HPS_FN_MOD), > > + regmap_reg_range(L3NIC_ETR_READ_QOS, L3NIC_ETR_FN_MOD), > > + regmap_reg_range(L3NIC_EMAC0_READ_QOS, L3NIC_EMAC0_FN_MOD), > > + regmap_reg_range(L3NIC_EMAC1_READ_QOS, L3NIC_EMAC1_FN_MOD), > > + regmap_reg_range(L3NIC_USB0_FN_MOD_AHB, L3NIC_USB0_FN_MOD_AHB), > > + regmap_reg_range(L3NIC_USB0_READ_QOS, L3NIC_USB0_FN_MOD), > > + regmap_reg_range(L3NIC_NAND_READ_QOS, L3NIC_NAND_FN_MOD), > > + regmap_reg_range(L3NIC_USB1_FN_MOD_AHB, L3NIC_USB1_FN_MOD_AHB), > > + regmap_reg_range(L3NIC_USB1_READ_QOS, L3NIC_USB1_FN_MOD), > > +}; > > + > > +static const struct regmap_access_table l3nic_write_regs = { > > + .yes_ranges = l3nic_write_regs_range, > > + .n_yes_ranges = ARRAY_SIZE(l3nic_write_regs_range), > > +}; > > + > > +static const struct regmap_access_table l3nic_read_regs = { > > + .yes_ranges = l3nic_read_regs_range, > > + .n_yes_ranges = ARRAY_SIZE(l3nic_read_regs_range), > > +}; > > + > > +static struct regmap_config l3nic_regmap_config = { > > + .reg_bits = 32, > > + .val_bits = 32, > > + .reg_stride = 4, > > + .rd_table = &l3nic_read_regs, > > + .wr_table = &l3nic_write_regs, > > + .cache_type = REGCACHE_RBTREE, > > +}; > > + > > +struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, > > + const char *name) > > +{ > > + struct socfpga_l3nic *l3nic; > > + struct platform_device *pdev; > > + > > + pdev = socfpga_gpv_device_by_phandle(np, name); > > + if (IS_ERR(pdev)) > > + return ERR_CAST(pdev); > > + > > + l3nic = dev_get_drvdata(&pdev->dev); > > + if (!l3nic) > > + return ERR_PTR(-EINVAL); > > + > > + if (l3nic->regmap) > > + return l3nic->regmap; > > + else > > + return ERR_PTR(-ENODEV); > > +} > > +EXPORT_SYMBOL_GPL(socfpga_l3nic_regmap_by_phandle); > > + > > +static int socfpga_l3nic_probe(struct platform_device *pdev) > > +{ > > + struct socfpga_l3nic *priv; > > + struct resource *res; > > + > > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); > > + if (!priv) > > + return -ENOMEM; > > + > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + priv->base = devm_ioremap_resource(&pdev->dev, res); > > + if (IS_ERR(priv->base)) > > + return PTR_ERR(priv->base); > > + > > + l3nic_regmap_config.max_register = res->end - res->start - 3; > > + priv->regmap = devm_regmap_init_mmio(&pdev->dev, priv->base, > > + &l3nic_regmap_config); > > + if (IS_ERR(priv->regmap)) { > > + dev_err(&pdev->dev, "regmap init failed\n"); > > + return PTR_ERR(priv->regmap); > > + } > > + > > + platform_set_drvdata(pdev, priv); > > + > > + dev_info(&pdev->dev, "L3 NIC-301 registered\n"); > > + > > + return 0; > > +} > > + > > +static int socfpga_l3nic_remove(struct platform_device *pdev) > > +{ > > + return 0; > > +} > > + > > +static const struct of_device_id socfpga_l3nic_dt_ids[] = { > > + { .compatible = "altr,l3-nic", }, > > + { /* sentinel */ }, > > +}; > > + > > +static struct platform_driver socfpga_l3nic_driver = { > > + .probe = socfpga_l3nic_probe, > > + .remove = socfpga_l3nic_remove, > > + .driver = { > > + .name = "socfpga-l3-nic", > > + .owner = THIS_MODULE, > > + .of_match_table = socfpga_l3nic_dt_ids, > > + }, > > +}; > > +module_platform_driver(socfpga_l3nic_driver); > > + > > +MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de"); > > +MODULE_DESCRIPTION("Socfpga L3 NIC-301 Interconnect Driver"); > > +MODULE_LICENSE("GPL v2"); > > diff --git a/include/soc/socfpga/gpv.h b/include/soc/socfpga/gpv.h > > new file mode 100644 > > index 000000000000..31bb555ea2c3 > > --- /dev/null > > +++ b/include/soc/socfpga/gpv.h > > @@ -0,0 +1,63 @@ > > +/* > > + * Copyright (c) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as published by > > + * the Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + */ > > + > > +#ifndef __SOC_SOCFPGA_GPV_H__ > > +#define __SOC_SOCFPGA_GPV_H__ > > + > > +#ifdef CONFIG_ARCH_SOCFPGA > > + > > +#include <linux/device.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > + > > +#define GPV_FN_MOD_BM_ISS_WR BIT(1) > > +#define GPV_FN_MOD_BM_ISS_RD BIT(0) > > +#define GPV_AHB_CNTL_FORCE_INCR BIT(1) > > +#define GPV_AHB_CNTL_DECERR_EN BIT(0) > > +#define GPV_WR_TIDEMARK_MASK 0xf > > +#define GPV_FN_MOD_AHB_WR_INCR_OVERRIDE BIT(1) > > +#define GPV_FN_MOD_AHB_RD_INCR_OVERRIDE BIT(0) > > +#define GPV_FN_MOD_WR BIT(1) > > +#define GPV_FN_MOD_RD BIT(0) > > +#define GPV_FN_MOD_BYPASS_MERGE BIT(0) > > +#define GPV_READ_QOS_MASK 0xf > > +#define GPV_WRITE_QOS_MASK 0xf > > + > > +static inline struct platform_device *socfpga_gpv_device_by_phandle( > > + struct device_node *np, > > + const char *name) > > +{ > > + struct device_node *gpv_np; > > + struct platform_device *pdev; > > + > > + gpv_np = of_parse_phandle(np, name, 0); > > + if (!gpv_np) > > + return ERR_PTR(-EINVAL); > > + > > + pdev = of_find_device_by_node(gpv_np); > > + > > + of_node_put(gpv_np); > > + > > + if (!pdev) > > + return ERR_PTR(-EPROBE_DEFER); > > + > > + return pdev; > > +} > > + > > +#else > > + > > +static struct platform_device *socfpga_gpv_device_by_phandle( > > + struct device_node *np, > > + const char *name) > > +{ > > + return ERR_PTR(-ENOSYS); > > +} > > + > > +#endif > > +#endif > > diff --git a/include/soc/socfpga/l3regs.h b/include/soc/socfpga/l3regs.h > > new file mode 100644 > > index 000000000000..bcdecd74bf17 > > --- /dev/null > > +++ b/include/soc/socfpga/l3regs.h > > @@ -0,0 +1,192 @@ > > +/* > > + * Copyright (c) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as published by > > + * the Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + */ > > + > > +#ifndef __SOC_SOCFPGA_L3NIC_H__ > > +#define __SOC_SOCFPGA_L3NIC_H__ > > + > > +#ifdef CONFIG_ARCH_SOCFPGA > > + > > +#define L3NIC_REMAP 0x0 > > + > > +/* Security Registers */ > > + > > +#define L3NIC_L4MAIN 0x8 > > +#define L3NIC_L4SP 0xc > > +#define L3NIC_L4MP 0x10 > > +#define L3NIC_L4OSC1 0x14 > > +#define L3NIC_L4SPIM 0x18 > > +#define L3NIC_STM 0x1c > > +#define L3NIC_LWHPS2FPGAREGS 0x20 > > + > > +#define L3NIC_USB1 0x28 > > +#define L3NIC_NANDDATA 0x2c > > + > > +#define L3NIC_USB0 0x80 > > +#define L3NIC_NANDREGS 0x84 > > +#define L3NIC_QSPIDATA 0x88 > > +#define L3NIC_FPGAMGRDATA 0x8c > > +#define L3NIC_HPS2FPGAREGS 0x90 > > +#define L3NIC_ACP 0x94 > > +#define L3NIC_ROM 0x98 > > +#define L3NIC_OCRAM 0x9c > > +#define L3NIC_SDRDATA 0xa0 > > + > > +/* ID registers */ > > + > > +#define L3NIC_PERIPH_ID_4 0x1fd0 > > + > > +#define L3NIC_PERIPH_ID_0 0x1fe0 > > +#define L3NIC_PERIPH_ID_1 0x1fe4 > > +#define L3NIC_PERIPH_ID_2 0x1fe8 > > +#define L3NIC_PERIPH_ID_3 0x1fec > > +#define L3NIC_COMP_ID_0 0x1ff0 > > +#define L3NIC_COMP_ID_1 0x1ff4 > > +#define L3NIC_COMP_ID_2 0x1ff8 > > +#define L3NIC_COMP_ID_3 0x1ffc > > + > > +/* Master Registers */ > > + > > +#define L3NIC_L4_MAIN_FN_MOD_BM_ISS 0x2008 > > + > > +#define L3NIC_L4_SP_FN_MOD_BM_ISS 0x3008 > > + > > +#define L3NIC_L4_MP_FN_MOD_BM_ISS 0x4008 > > + > > +#define L3NIC_L4_OSC1_FN_MOD_BM_ISS 0x5008 > > + > > +#define L3NIC_L4_SPIM_FN_MOD_BM_ISS 0x6008 > > + > > +#define L3NIC_STM_FN_MOD_BM_ISS 0x7008 > > + > > +#define L3NIC_STM_FN_MOD 0x7108 > > + > > +#define L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS 0x8008 > > + > > +#define L3NIC_LWHPS2FPGA_FN_MOD 0x8108 > > + > > +#define L3NIC_USB1_FN_MOD_BM_ISS 0xa008 > > + > > +#define L3NIC_USB1_AHB_CNTL 0xa044 > > + > > +#define L3NIC_NANDDATA_FN_MOD_BM_ISS 0xb008 > > + > > +#define L3NIC_NANDDATA_FN_MOD 0xb108 > > + > > +#define L3NIC_USB0_FN_MOD_BM_ISS 0x20008 > > + > > +#define L3NIC_USB0_AHB_CNTL 0x20044 > > + > > +#define L3NIC_QSPIDATA_FN_MOD_BM_ISS 0x22008 > > + > > +#define L3NIC_QSPIDATA_AHB_CNTL 0x22044 > > + > > +#define L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS 0x23008 > > + > > +#define L3NIC_FPGAMGRDATA_WR_TIDEMARK 0x23040 > > + > > +#define L3NIC_FPGAMGRDATA_FN_MOD 0x23108 > > + > > +#define L3NIC_HPS2FPGA_FN_MOD_BM_ISS 0x24008 > > + > > +#define L3NIC_HPS2FPGA_WR_TIDEMARK 0x24040 > > + > > +#define L3NIC_HPS2FPGA_FN_MOD 0x24108 > > + > > +#define L3NIC_ACP_FN_MOD_BM_ISS 0x25008 > > + > > +#define L3NIC_ACP_FN_MOD 0x25108 > > + > > +#define L3NIC_BOOT_ROM_FN_MOD_BM_ISS 0x26008 > > + > > +#define L3NIC_BOOT_ROM_FN_MOD 0x26108 > > + > > +#define L3NIC_OCRAM_FN_MOD_BM_ISS 0x27008 > > + > > +#define L3NIC_OCRAM_WR_TIDEMARK 0x27040 > > + > > +#define L3NIC_OCRAM_FN_MOD 0x27108 > > + > > +/* Slave Registers */ > > + > > +#define L3NIC_DAP_FN_MOD2 0x42024 > > +#define L3NIC_DAP_FN_MOD_AHB 0x42028 > > + > > +#define L3NIC_DAP_READ_QOS 0x42100 > > +#define L3NIC_DAP_WRITE_QOS 0x42104 > > +#define L3NIC_DAP_FN_MOD 0x42108 > > + > > +#define L3NIC_MPU_READ_QOS 0x43100 > > +#define L3NIC_MPU_WRITE_QOS 0x43104 > > +#define L3NIC_MPU_FN_MOD 0x43108 > > + > > +#define L3NIC_SDMMC_FN_MOD_AHB 0x44028 > > + > > +#define L3NIC_SDMMC_READ_QOS 0x44100 > > +#define L3NIC_SDMMC_WRITE_QOS 0x44104 > > +#define L3NIC_SDMMC_FN_MOD 0x44108 > > + > > +#define L3NIC_DMA_READ_QOS 0x45100 > > +#define L3NIC_DMA_WRITE_QOS 0x45104 > > +#define L3NIC_DMA_FN_MOD 0x45108 > > + > > +#define L3NIC_FPGA2HPS_WR_TIDEMARK 0x46040 > > + > > +#define L3NIC_FPGA2HPS_READ_QOS 0x46100 > > +#define L3NIC_FPGA2HPS_WRITE_QOS 0x46104 > > +#define L3NIC_FPGA2HPS_FN_MOD 0x46108 > > + > > +#define L3NIC_ETR_READ_QOS 0x47100 > > +#define L3NIC_ETR_WRITE_QOS 0x47104 > > +#define L3NIC_ETR_FN_MOD 0x47108 > > + > > +#define L3NIC_EMAC0_READ_QOS 0x48100 > > +#define L3NIC_EMAC0_WRITE_QOS 0x48104 > > +#define L3NIC_EMAC0_FN_MOD 0x48108 > > + > > +#define L3NIC_EMAC1_READ_QOS 0x49100 > > +#define L3NIC_EMAC1_WRITE_QOS 0x49104 > > +#define L3NIC_EMAC1_FN_MOD 0x49108 > > + > > +#define L3NIC_USB0_FN_MOD_AHB 0x4a028 > > + > > +#define L3NIC_USB0_READ_QOS 0x4a100 > > +#define L3NIC_USB0_WRITE_QOS 0x4a104 > > +#define L3NIC_USB0_FN_MOD 0x4a108 > > + > > +#define L3NIC_NAND_READ_QOS 0x4b100 > > +#define L3NIC_NAND_WRITE_QOS 0x4b104 > > +#define L3NIC_NAND_FN_MOD 0x4b108 > > + > > +#define L3NIC_USB1_FN_MOD_AHB 0x4c028 > > + > > +#define L3NIC_USB1_READ_QOS 0x4c100 > > +#define L3NIC_USB1_WRITE_QOS 0x4c104 > > +#define L3NIC_USB1_FN_MOD 0x4c108 > > + > > +#define L3NIC_LWHPS2FPGA_VISIBILITY BIT(4) > > +#define L3NIC_HPS2FPGA_VISIBILITY BIT(3) > > + > > +struct socfpga_l3nic { > > + void __iomem *base; > > + struct regmap *regmap; > > +}; > > + > > +extern struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, > > + const char *name); > > + > > +#else > > + > > +struct regmap *socfpga_l3nic_regmap_by_phandle(struct device_node *np, > > + const char *name) > > +{ > > + return ERR_PTR(-ENOSYS); > > +} > > + > > +#endif > > +#endif > > > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect 2014-12-05 19:51 ` atull @ 2014-12-05 20:19 ` Steffen Trumtrar 0 siblings, 0 replies; 20+ messages in thread From: Steffen Trumtrar @ 2014-12-05 20:19 UTC (permalink / raw) To: linux-arm-kernel Hi! On Fri, Dec 05, 2014 at 01:51:48PM -0600, atull wrote: > On Tue, 2 Dec 2014, Dinh Nguyen wrote: > > > +CC: Alan Tull > > > > On 11/29/2014 02:14 PM, Steffen Trumtrar wrote: > > > The L3 interconnect provides Global Programmer View (GPV) registers for every > > > AXI master and slave on the SoC. > > > Although this is just a bunch of bits, syscon is not the right approach for > > > this IP core. > > > The L3 interconnect is configured with a lot of reserved "holes" in its memory > > > space. Just mapping this with regmap, what syscon would do, would lead to the > > > system completely hanging, if one of those areas would be touched. > > > One example for when this might happen is the regmap registers dump in the > > > debugfs. > > > > > > This driver specifies also the valid readable and writable ranges of the L3 > > > interconnect. Other drivers that want to access their GPV registers can do > > > so with this driver via socfpga_l3nic_regmap_by_phandle. > > > > > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > > > --- > > > drivers/soc/Kconfig | 1 + > > > drivers/soc/Makefile | 1 + > > > drivers/soc/socfpga/Kconfig | 10 ++ > > > drivers/soc/socfpga/Makefile | 1 + > > > drivers/soc/socfpga/l3nic.c | 221 +++++++++++++++++++++++++++++++++++++++++++ > > > include/soc/socfpga/gpv.h | 63 ++++++++++++ > > > include/soc/socfpga/l3regs.h | 192 +++++++++++++++++++++++++++++++++++++ > > > 7 files changed, 489 insertions(+) > > > create mode 100644 drivers/soc/socfpga/Kconfig > > > create mode 100644 drivers/soc/socfpga/Makefile > > > create mode 100644 drivers/soc/socfpga/l3nic.c > > > create mode 100644 include/soc/socfpga/gpv.h > > > create mode 100644 include/soc/socfpga/l3regs.h > > > > > > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig > > > index 76d6bd4da138..11db07da894f 100644 > > > --- a/drivers/soc/Kconfig > > > +++ b/drivers/soc/Kconfig > > > @@ -1,6 +1,7 @@ > > > menu "SOC (System On Chip) specific Drivers" > > > > > > source "drivers/soc/qcom/Kconfig" > > > +source "drivers/soc/socfpga/Kconfig" > > > source "drivers/soc/ti/Kconfig" > > > source "drivers/soc/versatile/Kconfig" > > > > > > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > > > index 063113d0bd38..0f89173e328a 100644 > > > --- a/drivers/soc/Makefile > > > +++ b/drivers/soc/Makefile > > > @@ -3,6 +3,7 @@ > > > # > > > > > > obj-$(CONFIG_ARCH_QCOM) += qcom/ > > > +obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ > > > obj-$(CONFIG_ARCH_TEGRA) += tegra/ > > > obj-$(CONFIG_SOC_TI) += ti/ > > > obj-$(CONFIG_PLAT_VERSATILE) += versatile/ > > > diff --git a/drivers/soc/socfpga/Kconfig b/drivers/soc/socfpga/Kconfig > > > new file mode 100644 > > > index 000000000000..533c59449fb8 > > > --- /dev/null > > > +++ b/drivers/soc/socfpga/Kconfig > > > @@ -0,0 +1,10 @@ > > > +# > > > +# SoCFPGA Soc drivers > > > +# > > > + > > > +config SOCFPGA_L3NIC > > > + tristate "SoCFPGA L3 NIC-301 driver" > > > + depends on ARCH_SOCFPGA > > > + select REGMAP_MMIO > > > + help > > > + Enable configuration support for the SoCFPGA L3 AMBA Network Interconnect. > > > diff --git a/drivers/soc/socfpga/Makefile b/drivers/soc/socfpga/Makefile > > > new file mode 100644 > > > index 000000000000..e6616d079226 > > > --- /dev/null > > > +++ b/drivers/soc/socfpga/Makefile > > > @@ -0,0 +1 @@ > > > +obj-$(CONFIG_SOCFPGA_L3NIC) += l3nic.o > > > diff --git a/drivers/soc/socfpga/l3nic.c b/drivers/soc/socfpga/l3nic.c > > > new file mode 100644 > > > index 000000000000..c1f36e2ec9cb > > > --- /dev/null > > > +++ b/drivers/soc/socfpga/l3nic.c > > > @@ -0,0 +1,221 @@ > > > +/* > > > + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> > > > + * > > > + * This program is free software; you can redistribute it and/or modify > > > + * it under the terms of the GNU General Public License as published by > > > + * the Free Software Foundation; either version 2 of the License, or > > > + * (at your option) any later version. > > > + */ > > > + > > > +#include <linux/clk.h> > > > +#include <linux/err.h> > > > +#include <linux/io.h> > > > +#include <linux/module.h> > > > +#include <linux/of.h> > > > +#include <linux/of_device.h> > > > +#include <linux/platform_device.h> > > > +#include <linux/regmap.h> > > > +#include <linux/types.h> > > > +#include <soc/socfpga/gpv.h> > > > +#include <soc/socfpga/l3regs.h> > > > + > > > +static const struct regmap_range l3nic_write_regs_range[] = { > > > + regmap_reg_range(L3NIC_REMAP, L3NIC_REMAP), > > > + regmap_reg_range(L3NIC_L4MAIN, L3NIC_LWHPS2FPGAREGS), > > > + regmap_reg_range(L3NIC_USB1, L3NIC_NANDDATA), > > > + regmap_reg_range(L3NIC_USB0, L3NIC_SDRDATA), > > > + regmap_reg_range(L3NIC_L4_MAIN_FN_MOD_BM_ISS, L3NIC_L4_MAIN_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_L4_SP_FN_MOD_BM_ISS, L3NIC_L4_SP_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_L4_MP_FN_MOD_BM_ISS, L3NIC_L4_MP_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_L4_OSC1_FN_MOD_BM_ISS, L3NIC_L4_OSC1_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_L4_SPIM_FN_MOD_BM_ISS, L3NIC_L4_SPIM_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_STM_FN_MOD_BM_ISS, L3NIC_STM_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_STM_FN_MOD, L3NIC_STM_FN_MOD), > > > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS, L3NIC_LWHPS2FPGA_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_LWHPS2FPGA_FN_MOD, L3NIC_LWHPS2FPGA_FN_MOD), > > > + regmap_reg_range(L3NIC_USB1_FN_MOD_BM_ISS, L3NIC_USB1_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_USB1_AHB_CNTL, L3NIC_USB1_AHB_CNTL), > > > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD_BM_ISS, L3NIC_NANDDATA_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_NANDDATA_FN_MOD, L3NIC_NANDDATA_FN_MOD), > > > + regmap_reg_range(L3NIC_USB0_FN_MOD_BM_ISS, L3NIC_USB0_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_USB0_AHB_CNTL, L3NIC_USB0_AHB_CNTL), > > > + regmap_reg_range(L3NIC_QSPIDATA_FN_MOD_BM_ISS, L3NIC_QSPIDATA_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_QSPIDATA_AHB_CNTL, L3NIC_QSPIDATA_AHB_CNTL), > > > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS, L3NIC_FPGAMGRDATA_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_FPGAMGRDATA_WR_TIDEMARK, L3NIC_FPGAMGRDATA_WR_TIDEMARK), > > > + regmap_reg_range(L3NIC_FPGAMGRDATA_FN_MOD, L3NIC_FPGAMGRDATA_FN_MOD), > > > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD_BM_ISS, L3NIC_HPS2FPGA_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_HPS2FPGA_WR_TIDEMARK, L3NIC_HPS2FPGA_WR_TIDEMARK), > > > + regmap_reg_range(L3NIC_HPS2FPGA_FN_MOD, L3NIC_HPS2FPGA_FN_MOD), > > > + regmap_reg_range(L3NIC_ACP_FN_MOD_BM_ISS, L3NIC_ACP_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_ACP_FN_MOD, L3NIC_ACP_FN_MOD), > > > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD_BM_ISS, L3NIC_BOOT_ROM_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_BOOT_ROM_FN_MOD, L3NIC_BOOT_ROM_FN_MOD), > > > + regmap_reg_range(L3NIC_OCRAM_FN_MOD_BM_ISS, L3NIC_OCRAM_FN_MOD_BM_ISS), > > > + regmap_reg_range(L3NIC_OCRAM_WR_TIDEMARK, L3NIC_OCRAM_WR_TIDEMARK), > > > + regmap_reg_range(L3NIC_OCRAM_FN_MOD, L3NIC_OCRAM_FN_MOD), > > > + regmap_reg_range(L3NIC_DAP_FN_MOD2, L3NIC_DAP_FN_MOD_AHB), > > > + regmap_reg_range(L3NIC_DAP_READ_QOS, L3NIC_DAP_FN_MOD), > > > + regmap_reg_range(L3NIC_MPU_READ_QOS, L3NIC_MPU_FN_MOD), > > > + regmap_reg_range(L3NIC_SDMMC_FN_MOD_AHB, L3NIC_SDMMC_FN_MOD_AHB), > > > + regmap_reg_range(L3NIC_SDMMC_READ_QOS, L3NIC_SDMMC_FN_MOD), > > > + regmap_reg_range(L3NIC_DMA_READ_QOS, L3NIC_DMA_FN_MOD), > > > + regmap_reg_range(L3NIC_FPGA2HPS_WR_TIDEMARK, L3NIC_FPGA2HPS_WR_TIDEMARK), > > > + regmap_reg_range(L3NIC_FPGA2HPS_READ_QOS, L3NIC_FPGA2HPS_FN_MOD), > > > + regmap_reg_range(L3NIC_ETR_READ_QOS, L3NIC_ETR_FN_MOD), > > > + regmap_reg_range(L3NIC_EMAC0_READ_QOS, L3NIC_EMAC0_FN_MOD), > > > + regmap_reg_range(L3NIC_EMAC1_READ_QOS, L3NIC_EMAC1_FN_MOD), > > > + regmap_reg_range(L3NIC_USB0_FN_MOD_AHB, L3NIC_USB0_FN_MOD_AHB), > > > + regmap_reg_range(L3NIC_USB0_READ_QOS, L3NIC_USB0_FN_MOD), > > > + regmap_reg_range(L3NIC_NAND_READ_QOS, L3NIC_NAND_FN_MOD), > > > + regmap_reg_range(L3NIC_USB1_FN_MOD_AHB, L3NIC_USB1_FN_MOD_AHB), > > > + regmap_reg_range(L3NIC_USB1_READ_QOS, L3NIC_USB1_FN_MOD), > > > +}; > > > + > > > +static const struct regmap_range l3nic_read_regs_range[] = { > > > + regmap_reg_range(L3NIC_REMAP, L3NIC_REMAP), > > Hi Steffen, > > We may have discussed this a bit, but I want to make sure that this is > made obvious here: some of these registers are not readable. L3NIC_REMAP > is one of these for example. > You can read just fine from the register, but you will always get a 0 back. > So please mark the appropriate registers as not being readable. Then > anyone who does a regmap_update_bits() will get an error, which is > what we want. > > It would probably be good to add a note to the patch header warning > people that some of these regs are write-only. > Regmap has a cache for the value. When you do a read on these registers, you get the cached value, consequently you can also do a regmap_update_bits from different drivers and will always have the correct value written to the register. The registers you can NOT read from are the ones not in the specified ranges and the whole reason why I wrote this driver. > I also would request that you post future versions, please keep me and all > the other people who originally had replied to v1, v2, etc in the cc. > Yes, I forgot to add you. Sorry. Regards, Steffen -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect 2014-11-29 20:14 ` [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect Steffen Trumtrar 2014-12-02 16:45 ` Dinh Nguyen @ 2014-12-15 22:34 ` Pavel Machek 2014-12-16 8:31 ` Steffen Trumtrar 1 sibling, 1 reply; 20+ messages in thread From: Pavel Machek @ 2014-12-15 22:34 UTC (permalink / raw) To: linux-arm-kernel Hi! > The L3 interconnect provides Global Programmer View (GPV) registers for every > AXI master and slave on the SoC. > Although this is just a bunch of bits, syscon is not the right approach for > this IP core. > The L3 interconnect is configured with a lot of reserved "holes" in its memory > space. Just mapping this with regmap, what syscon would do, would lead to the > system completely hanging, if one of those areas would be touched. > One example for when this might happen is the regmap registers dump in the > debugfs. Could syscon be extended to take more than one range? Then, you could simply list all the ranges in device tree and use syscon... > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig > index 76d6bd4da138..11db07da894f 100644 > --- a/drivers/soc/Kconfig > +++ b/drivers/soc/Kconfig > @@ -1,6 +1,7 @@ > menu "SOC (System On Chip) specific Drivers" SoC is usual spelling. > @@ -0,0 +1,10 @@ > +# > +# SoCFPGA Soc drivers SoC. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect 2014-12-15 22:34 ` Pavel Machek @ 2014-12-16 8:31 ` Steffen Trumtrar 0 siblings, 0 replies; 20+ messages in thread From: Steffen Trumtrar @ 2014-12-16 8:31 UTC (permalink / raw) To: linux-arm-kernel Hi! On Mon, Dec 15, 2014 at 11:34:40PM +0100, Pavel Machek wrote: > Hi! > > > The L3 interconnect provides Global Programmer View (GPV) registers for every > > AXI master and slave on the SoC. > > Although this is just a bunch of bits, syscon is not the right approach for > > this IP core. > > The L3 interconnect is configured with a lot of reserved "holes" in its memory > > space. Just mapping this with regmap, what syscon would do, would lead to the > > system completely hanging, if one of those areas would be touched. > > One example for when this might happen is the regmap registers dump in the > > debugfs. > > Could syscon be extended to take more than one range? Then, you could > simply list all the ranges in device tree and use syscon... > Well it could. The question is, if it should. I don't think it would be a good idea to abstract away every IP core with a syscon node, just because it works. > > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig > > index 76d6bd4da138..11db07da894f 100644 > > --- a/drivers/soc/Kconfig > > +++ b/drivers/soc/Kconfig > > @@ -1,6 +1,7 @@ > > menu "SOC (System On Chip) specific Drivers" > > SoC is usual spelling. > Send patches :-) This is already mainline and not added here. > > @@ -0,0 +1,10 @@ > > +# > > +# SoCFPGA Soc drivers > > SoC. > This however I will fix. Thanks, Steffen -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 3/3] ARM: dts: socfpga: Add l3nic node 2014-11-29 20:14 [PATCH v3 0/3] SoCFPGA: L3 NIC driver Steffen Trumtrar 2014-11-29 20:14 ` [PATCH v3 1/3] Documentation: dt: add Altera L3 NIC bindings Steffen Trumtrar 2014-11-29 20:14 ` [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect Steffen Trumtrar @ 2014-11-29 20:14 ` Steffen Trumtrar 2014-12-02 16:46 ` Dinh Nguyen 2014-11-30 11:51 ` [PATCH v3 0/3] SoCFPGA: L3 NIC driver Arnd Bergmann ` (2 subsequent siblings) 5 siblings, 1 reply; 20+ messages in thread From: Steffen Trumtrar @ 2014-11-29 20:14 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> --- arch/arm/boot/dts/socfpga.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4472fd92685c..e47b69c9f6cd 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -628,6 +628,11 @@ arm,data-latency = <2 1 1>; }; + l3regs: gpv at ff800000 { + compatible = "altr,l3-nic"; + reg = <0xff800000 0x100000>; + }; + mmc: dwmmc0 at ff704000 { compatible = "altr,socfpga-dw-mshc"; reg = <0xff704000 0x1000>; -- 2.1.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 3/3] ARM: dts: socfpga: Add l3nic node 2014-11-29 20:14 ` [PATCH v3 3/3] ARM: dts: socfpga: Add l3nic node Steffen Trumtrar @ 2014-12-02 16:46 ` Dinh Nguyen 0 siblings, 0 replies; 20+ messages in thread From: Dinh Nguyen @ 2014-12-02 16:46 UTC (permalink / raw) To: linux-arm-kernel +CC: Alan Tull On 11/29/2014 02:14 PM, Steffen Trumtrar wrote: > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > --- > arch/arm/boot/dts/socfpga.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi > index 4472fd92685c..e47b69c9f6cd 100644 > --- a/arch/arm/boot/dts/socfpga.dtsi > +++ b/arch/arm/boot/dts/socfpga.dtsi > @@ -628,6 +628,11 @@ > arm,data-latency = <2 1 1>; > }; > > + l3regs: gpv at ff800000 { > + compatible = "altr,l3-nic"; > + reg = <0xff800000 0x100000>; > + }; > + > mmc: dwmmc0 at ff704000 { > compatible = "altr,socfpga-dw-mshc"; > reg = <0xff704000 0x1000>; > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-11-29 20:14 [PATCH v3 0/3] SoCFPGA: L3 NIC driver Steffen Trumtrar ` (2 preceding siblings ...) 2014-11-29 20:14 ` [PATCH v3 3/3] ARM: dts: socfpga: Add l3nic node Steffen Trumtrar @ 2014-11-30 11:51 ` Arnd Bergmann 2014-11-30 20:53 ` Robert Schwebel 2014-12-01 10:08 ` Mark Rutland 2014-12-02 16:44 ` Dinh Nguyen 5 siblings, 1 reply; 20+ messages in thread From: Arnd Bergmann @ 2014-11-30 11:51 UTC (permalink / raw) To: linux-arm-kernel On Saturday 29 November 2014 21:14:09 Steffen Trumtrar wrote: > Hi! > > This series adds support for the SoCFPGA L3 NIC. As the memory range has > a lot of holes, where you can not read from, syscon can not be used for > this IP core. Instead add a new driver, that knows about all the allowed > ranges and guards the access via regmap. What is an L3 NIC? Arnd ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-11-30 11:51 ` [PATCH v3 0/3] SoCFPGA: L3 NIC driver Arnd Bergmann @ 2014-11-30 20:53 ` Robert Schwebel 2014-12-04 16:30 ` Arnd Bergmann 0 siblings, 1 reply; 20+ messages in thread From: Robert Schwebel @ 2014-11-30 20:53 UTC (permalink / raw) To: linux-arm-kernel On Sun, Nov 30, 2014 at 12:51:58PM +0100, Arnd Bergmann wrote: > > This series adds support for the SoCFPGA L3 NIC. As the memory range has > > a lot of holes, where you can not read from, syscon can not be used for > > this IP core. Instead add a new driver, that knows about all the allowed > > ranges and guards the access via regmap. > > What is an L3 NIC? Fron the SoCFPGA manual: " The hard processor system (HPS) level 3 (L3) interconnect and level 4 (L4) peripheral buses are implemented with the ARM CoreLinkTM Network Interconnect (NIC-301). The NIC-301 provides a foundation for a high-performance HPS interconnect based on the ARM Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI), Advanced High-Performance Bus (AHBTM), and Advanced Peripheral Bus (APBTM) protocols. The L3 interconnect implements a multilayer, nonblocking architecture that supports multiple simultaneous transactions between masters and slaves, including the Cortex-A9 microprocessor unit (MPU) subsystem. The interconnect provides five independent L4 buses to access control and status registers (CSRs) of peripherals, managers, and memory controllers Related Information http://infocenter.arm.com/ Additional information is available in the AMBA Network Interconnect (NIC-301) Technical Reference Manual, revision r2p3, which you can download from the ARM info center website. " rsc -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-11-30 20:53 ` Robert Schwebel @ 2014-12-04 16:30 ` Arnd Bergmann 2014-12-04 18:37 ` Mark Rutland 0 siblings, 1 reply; 20+ messages in thread From: Arnd Bergmann @ 2014-12-04 16:30 UTC (permalink / raw) To: linux-arm-kernel On Sunday 30 November 2014 21:53:31 Robert Schwebel wrote: > On Sun, Nov 30, 2014 at 12:51:58PM +0100, Arnd Bergmann wrote: > > > This series adds support for the SoCFPGA L3 NIC. As the memory range has > > > a lot of holes, where you can not read from, syscon can not be used for > > > this IP core. Instead add a new driver, that knows about all the allowed > > > ranges and guards the access via regmap. > > > > What is an L3 NIC? > > Fron the SoCFPGA manual: > > " > The hard processor system (HPS) level 3 (L3) interconnect and level 4 > (L4) peripheral buses are implemented with the ARM CoreLinkTM Network > Interconnect (NIC-301). The NIC-301 provides a foundation for a > high-performance HPS interconnect based on the ARM Advanced > Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface > (AXI), Advanced High-Performance Bus (AHBTM), and Advanced Peripheral > Bus (APBTM) protocols. The L3 interconnect implements a multilayer, > nonblocking architecture that supports multiple simultaneous > transactions between masters and slaves, including the Cortex-A9 > microprocessor unit (MPU) subsystem. The interconnect provides five > independent L4 buses to access control and status registers (CSRs) of > peripherals, managers, and memory controllers Related Information > http://infocenter.arm.com/ Additional information is available in the > AMBA Network Interconnect (NIC-301) Technical Reference Manual, revision > r2p3, which you can download from the ARM info center website. Please put something like this in the introductory mail and later into the pull request then. If the l3-nic is an ARM nic-301, shouldn't the compatible string be "arm,nic-301"? Arnd ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-12-04 16:30 ` Arnd Bergmann @ 2014-12-04 18:37 ` Mark Rutland 2014-12-05 11:30 ` Robin Murphy 0 siblings, 1 reply; 20+ messages in thread From: Mark Rutland @ 2014-12-04 18:37 UTC (permalink / raw) To: linux-arm-kernel On Thu, Dec 04, 2014 at 04:30:58PM +0000, Arnd Bergmann wrote: > On Sunday 30 November 2014 21:53:31 Robert Schwebel wrote: > > On Sun, Nov 30, 2014 at 12:51:58PM +0100, Arnd Bergmann wrote: > > > > This series adds support for the SoCFPGA L3 NIC. As the memory range has > > > > a lot of holes, where you can not read from, syscon can not be used for > > > > this IP core. Instead add a new driver, that knows about all the allowed > > > > ranges and guards the access via regmap. > > > > > > What is an L3 NIC? > > > > Fron the SoCFPGA manual: > > > > " > > The hard processor system (HPS) level 3 (L3) interconnect and level 4 > > (L4) peripheral buses are implemented with the ARM CoreLinkTM Network > > Interconnect (NIC-301). The NIC-301 provides a foundation for a > > high-performance HPS interconnect based on the ARM Advanced > > Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface > > (AXI), Advanced High-Performance Bus (AHBTM), and Advanced Peripheral > > Bus (APBTM) protocols. The L3 interconnect implements a multilayer, > > nonblocking architecture that supports multiple simultaneous > > transactions between masters and slaves, including the Cortex-A9 > > microprocessor unit (MPU) subsystem. The interconnect provides five > > independent L4 buses to access control and status registers (CSRs) of > > peripherals, managers, and memory controllers Related Information > > http://infocenter.arm.com/ Additional information is available in the > > AMBA Network Interconnect (NIC-301) Technical Reference Manual, revision > > r2p3, which you can download from the ARM info center website. > > Please put something like this in the introductory mail and later > into the pull request then. If the l3-nic is an ARM nic-301, shouldn't > the compatible string be "arm,nic-301"? We should also treat the device as a bus, with it's child devices as nodes underneath it (rather than a block on the side referred to by phandle). Mark. ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-12-04 18:37 ` Mark Rutland @ 2014-12-05 11:30 ` Robin Murphy 2014-12-05 22:18 ` Rob Herring 0 siblings, 1 reply; 20+ messages in thread From: Robin Murphy @ 2014-12-05 11:30 UTC (permalink / raw) To: linux-arm-kernel Hi Mark, On 04/12/14 18:37, Mark Rutland wrote: > On Thu, Dec 04, 2014 at 04:30:58PM +0000, Arnd Bergmann wrote: >> On Sunday 30 November 2014 21:53:31 Robert Schwebel wrote: >>> On Sun, Nov 30, 2014 at 12:51:58PM +0100, Arnd Bergmann wrote: >>>>> This series adds support for the SoCFPGA L3 NIC. As the memory range has >>>>> a lot of holes, where you can not read from, syscon can not be used for >>>>> this IP core. Instead add a new driver, that knows about all the allowed >>>>> ranges and guards the access via regmap. >>>> >>>> What is an L3 NIC? >>> >>> Fron the SoCFPGA manual: >>> >>> " >>> The hard processor system (HPS) level 3 (L3) interconnect and level 4 >>> (L4) peripheral buses are implemented with the ARM CoreLinkTM Network >>> Interconnect (NIC-301). The NIC-301 provides a foundation for a >>> high-performance HPS interconnect based on the ARM Advanced >>> Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface >>> (AXI), Advanced High-Performance Bus (AHBTM), and Advanced Peripheral >>> Bus (APBTM) protocols. The L3 interconnect implements a multilayer, >>> nonblocking architecture that supports multiple simultaneous >>> transactions between masters and slaves, including the Cortex-A9 >>> microprocessor unit (MPU) subsystem. The interconnect provides five >>> independent L4 buses to access control and status registers (CSRs) of >>> peripherals, managers, and memory controllers Related Information >>> http://infocenter.arm.com/ Additional information is available in the >>> AMBA Network Interconnect (NIC-301) Technical Reference Manual, revision >>> r2p3, which you can download from the ARM info center website. >> >> Please put something like this in the introductory mail and later >> into the pull request then. If the l3-nic is an ARM nic-301, shouldn't >> the compatible string be "arm,nic-301"? A common binding like that might work for earlier NIC301 revisions which were a fairly straightforward N-masters-to-M-slaves IP block. NIC301r2 (and NIC400 after it) is a rather different beast which is massively configurable and allows manually wiring together various master and slave ports with switches, register blocks, etc. willy-nilly like some kind of RTL Lego set. Given that, bindings for individual implementations make a lot more sense than first appears. > > We should also treat the device as a bus, with it's child devices as > nodes underneath it (rather than a block on the side referred to by > phandle). At the risk of reigniting the big hairy topology discussion, a "single" NIC of this flavour can have multiple unconnected paths through it (as sounds like may be the case here), with the master ports having entirely unrelated address maps, so from Linux's point of view it could look like several different buses which just happen to share a power domain. Add to that the fun possibility of things like having GPV registers only visible on one "bus" but controlling remapping of another "bus", and I think implementation-specific bindings are probably the only way for us to stay remotely sane. [Disclaimer: this comes from working on the end-user configuration tool, so I know more about that than the hardware itself] Robin. ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-12-05 11:30 ` Robin Murphy @ 2014-12-05 22:18 ` Rob Herring 0 siblings, 0 replies; 20+ messages in thread From: Rob Herring @ 2014-12-05 22:18 UTC (permalink / raw) To: linux-arm-kernel On Fri, Dec 5, 2014 at 5:30 AM, Robin Murphy <robin.murphy@arm.com> wrote: > Hi Mark, > > > On 04/12/14 18:37, Mark Rutland wrote: >> >> On Thu, Dec 04, 2014 at 04:30:58PM +0000, Arnd Bergmann wrote: >>> >>> On Sunday 30 November 2014 21:53:31 Robert Schwebel wrote: >>>> >>>> On Sun, Nov 30, 2014 at 12:51:58PM +0100, Arnd Bergmann wrote: >>>>>> >>>>>> This series adds support for the SoCFPGA L3 NIC. As the memory range >>>>>> has >>>>>> a lot of holes, where you can not read from, syscon can not be used >>>>>> for >>>>>> this IP core. Instead add a new driver, that knows about all the >>>>>> allowed >>>>>> ranges and guards the access via regmap. >>>>> >>>>> >>>>> What is an L3 NIC? >>>> >>>> >>>> Fron the SoCFPGA manual: >>>> >>>> " >>>> The hard processor system (HPS) level 3 (L3) interconnect and level 4 >>>> (L4) peripheral buses are implemented with the ARM CoreLinkTM Network >>>> Interconnect (NIC-301). The NIC-301 provides a foundation for a >>>> high-performance HPS interconnect based on the ARM Advanced >>>> Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface >>>> (AXI), Advanced High-Performance Bus (AHBTM), and Advanced Peripheral >>>> Bus (APBTM) protocols. The L3 interconnect implements a multilayer, >>>> nonblocking architecture that supports multiple simultaneous >>>> transactions between masters and slaves, including the Cortex-A9 >>>> microprocessor unit (MPU) subsystem. The interconnect provides five >>>> independent L4 buses to access control and status registers (CSRs) of >>>> peripherals, managers, and memory controllers Related Information >>>> http://infocenter.arm.com/ Additional information is available in the >>>> AMBA Network Interconnect (NIC-301) Technical Reference Manual, revision >>>> r2p3, which you can download from the ARM info center website. >>> >>> >>> Please put something like this in the introductory mail and later >>> into the pull request then. If the l3-nic is an ARM nic-301, shouldn't >>> the compatible string be "arm,nic-301"? > > > A common binding like that might work for earlier NIC301 revisions which > were a fairly straightforward N-masters-to-M-slaves IP block. NIC301r2 (and > NIC400 after it) is a rather different beast which is massively configurable > and allows manually wiring together various master and slave ports with > switches, register blocks, etc. willy-nilly like some kind of RTL Lego set. > Given that, bindings for individual implementations make a lot more sense > than first appears. > >> >> We should also treat the device as a bus, with it's child devices as >> nodes underneath it (rather than a block on the side referred to by >> phandle). > > > At the risk of reigniting the big hairy topology discussion, a "single" NIC > of this flavour can have multiple unconnected paths through it (as sounds > like may be the case here), with the master ports having entirely unrelated > address maps, so from Linux's point of view it could look like several > different buses which just happen to share a power domain. Add to that the > fun possibility of things like having GPV registers only visible on one > "bus" but controlling remapping of another "bus", and I think > implementation-specific bindings are probably the only way for us to stay > remotely sane. At least on the instance I worked on, most of the configuration is secure/non-secure related and hence configurable secure mode only (hopefully). We've already taken the stance that secure-only setup (e.g. errata work-arounds) should not be in the kernel. Does the same apply here? What configuration needs to be done at run-time? > [Disclaimer: this comes from working on the end-user configuration tool, so > I know more about that than the hardware itself] Generated RTL is fun for software. Especially, one vendor who's register layout shifts depending on the IP configuration. Rob ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-11-29 20:14 [PATCH v3 0/3] SoCFPGA: L3 NIC driver Steffen Trumtrar ` (3 preceding siblings ...) 2014-11-30 11:51 ` [PATCH v3 0/3] SoCFPGA: L3 NIC driver Arnd Bergmann @ 2014-12-01 10:08 ` Mark Rutland 2014-12-01 10:36 ` Steffen Trumtrar 2014-12-02 16:44 ` Dinh Nguyen 5 siblings, 1 reply; 20+ messages in thread From: Mark Rutland @ 2014-12-01 10:08 UTC (permalink / raw) To: linux-arm-kernel On Sat, Nov 29, 2014 at 08:14:09PM +0000, Steffen Trumtrar wrote: > Hi! Hi Steffen, > This series adds support for the SoCFPGA L3 NIC. As the memory range has > a lot of holes, where you can not read from, syscon can not be used for > this IP core. Instead add a new driver, that knows about all the allowed > ranges and guards the access via regmap. I note that while this series plumbs in a set of accessors (via regmap), there are no users as part of this series. What exactly do you intend to use these for? What is going to (re)program the bus, and how? I also note that you mention this L3/L4 bus hierarchy is composed of a number of NIC-301s, rather than being a single custom IP block. If that's the case, it would seem like there should be a binding for the NIC-301, and the hierarchy should be described. Thanks, Mark. > > Changes in v3: > > - Split out the devicetree binding in its own patch > > Regards, > Steffen > > Steffen Trumtrar (3): > Documentation: dt: add Altera L3 NIC bindings > ARM: socfpga: Add driver for the L3 interconnect > ARM: dts: socfpga: Add l3nic node > > .../bindings/soc/socfpga/altr,l3-nic.txt | 15 ++ > arch/arm/boot/dts/socfpga.dtsi | 5 + > drivers/soc/Kconfig | 1 + > drivers/soc/Makefile | 1 + > drivers/soc/socfpga/Kconfig | 10 + > drivers/soc/socfpga/Makefile | 1 + > drivers/soc/socfpga/l3nic.c | 221 +++++++++++++++++++++ > include/soc/socfpga/gpv.h | 63 ++++++ > include/soc/socfpga/l3regs.h | 192 ++++++++++++++++++ > 9 files changed, 509 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt > create mode 100644 drivers/soc/socfpga/Kconfig > create mode 100644 drivers/soc/socfpga/Makefile > create mode 100644 drivers/soc/socfpga/l3nic.c > create mode 100644 include/soc/socfpga/gpv.h > create mode 100644 include/soc/socfpga/l3regs.h > > -- > 2.1.3 > > ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-12-01 10:08 ` Mark Rutland @ 2014-12-01 10:36 ` Steffen Trumtrar 0 siblings, 0 replies; 20+ messages in thread From: Steffen Trumtrar @ 2014-12-01 10:36 UTC (permalink / raw) To: linux-arm-kernel Hi Mark! On Mon, Dec 01, 2014 at 10:08:58AM +0000, Mark Rutland wrote: > On Sat, Nov 29, 2014 at 08:14:09PM +0000, Steffen Trumtrar wrote: > > Hi! > > Hi Steffen, > > > This series adds support for the SoCFPGA L3 NIC. As the memory range has > > a lot of holes, where you can not read from, syscon can not be used for > > this IP core. Instead add a new driver, that knows about all the allowed > > ranges and guards the access via regmap. > > I note that while this series plumbs in a set of accessors (via regmap), > there are no users as part of this series. What exactly do you intend to > use these for? What is going to (re)program the bus, and how? > The first thing I want to use this for are the AXI bridges on the SoCFPGA. These bridges connect the FPGA to the SoC. I need to setup the visibility of the bridges on the L3, so that all L3 masters can access them. Other things that can be configured are e.g. "(...) issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions." for the USB0 host. So, this would belong into the USB driver AFAIK. Meaning: every L3 AXI slave or master can flip some bits in this register space. > I also note that you mention this L3/L4 bus hierarchy is composed of a > number of NIC-301s, rather than being a single custom IP block. If > that's the case, it would seem like there should be a binding for the > NIC-301, and the hierarchy should be described. > I didn't mean to say that. The NIC-301 is one single IP core AFAICT. See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0397f/index.html Regards, Steffen -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] SoCFPGA: L3 NIC driver 2014-11-29 20:14 [PATCH v3 0/3] SoCFPGA: L3 NIC driver Steffen Trumtrar ` (4 preceding siblings ...) 2014-12-01 10:08 ` Mark Rutland @ 2014-12-02 16:44 ` Dinh Nguyen 5 siblings, 0 replies; 20+ messages in thread From: Dinh Nguyen @ 2014-12-02 16:44 UTC (permalink / raw) To: linux-arm-kernel +CC: Alan Tull On 11/29/2014 02:14 PM, Steffen Trumtrar wrote: > Hi! > > This series adds support for the SoCFPGA L3 NIC. As the memory range has > a lot of holes, where you can not read from, syscon can not be used for > this IP core. Instead add a new driver, that knows about all the allowed > ranges and guards the access via regmap. > > Changes in v3: > > - Split out the devicetree binding in its own patch > > Regards, > Steffen > > Steffen Trumtrar (3): > Documentation: dt: add Altera L3 NIC bindings > ARM: socfpga: Add driver for the L3 interconnect > ARM: dts: socfpga: Add l3nic node > > .../bindings/soc/socfpga/altr,l3-nic.txt | 15 ++ > arch/arm/boot/dts/socfpga.dtsi | 5 + > drivers/soc/Kconfig | 1 + > drivers/soc/Makefile | 1 + > drivers/soc/socfpga/Kconfig | 10 + > drivers/soc/socfpga/Makefile | 1 + > drivers/soc/socfpga/l3nic.c | 221 +++++++++++++++++++++ > include/soc/socfpga/gpv.h | 63 ++++++ > include/soc/socfpga/l3regs.h | 192 ++++++++++++++++++ > 9 files changed, 509 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,l3-nic.txt > create mode 100644 drivers/soc/socfpga/Kconfig > create mode 100644 drivers/soc/socfpga/Makefile > create mode 100644 drivers/soc/socfpga/l3nic.c > create mode 100644 include/soc/socfpga/gpv.h > create mode 100644 include/soc/socfpga/l3regs.h > ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2014-12-16 8:31 UTC | newest] Thread overview: 20+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-11-29 20:14 [PATCH v3 0/3] SoCFPGA: L3 NIC driver Steffen Trumtrar 2014-11-29 20:14 ` [PATCH v3 1/3] Documentation: dt: add Altera L3 NIC bindings Steffen Trumtrar 2014-12-02 16:44 ` Dinh Nguyen 2014-11-29 20:14 ` [PATCH v3 2/3] ARM: socfpga: Add driver for the L3 interconnect Steffen Trumtrar 2014-12-02 16:45 ` Dinh Nguyen 2014-12-05 19:51 ` atull 2014-12-05 20:19 ` Steffen Trumtrar 2014-12-15 22:34 ` Pavel Machek 2014-12-16 8:31 ` Steffen Trumtrar 2014-11-29 20:14 ` [PATCH v3 3/3] ARM: dts: socfpga: Add l3nic node Steffen Trumtrar 2014-12-02 16:46 ` Dinh Nguyen 2014-11-30 11:51 ` [PATCH v3 0/3] SoCFPGA: L3 NIC driver Arnd Bergmann 2014-11-30 20:53 ` Robert Schwebel 2014-12-04 16:30 ` Arnd Bergmann 2014-12-04 18:37 ` Mark Rutland 2014-12-05 11:30 ` Robin Murphy 2014-12-05 22:18 ` Rob Herring 2014-12-01 10:08 ` Mark Rutland 2014-12-01 10:36 ` Steffen Trumtrar 2014-12-02 16:44 ` Dinh Nguyen
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