[PATCH v2 0/8] Add Armada 385 General Purpose Development Board support

[PATCH v2 0/8] Add Armada 385 General Purpose Development Board support

[Gregory CLEMENT]

Hi,

this patch set adds the support for the Armada 385 GP board, this
board is pretty close to the Armada 385 RD one. It comes with a new
revision of the Armada 38x SoC (A0). Actually the SoC used here is the
Armada 388 one, which differed from the Armada 385 by allowing to use
two more SATA ports.

In this second version, I took into account the various comments from
the 1st version but also some comments addressed to the Armada 385 AP
series. The bigest changes are the removal of the regulator for the
SATA which will be part of another series, the add of a dtsi file for
the Armada 388 variant, and the add of pinctrl configuration. See the
changelog for the details.

The first 3 patches came from Maxime's series to support the AP
board. I have done this in order to have a complete series and also
because I don't expect big change in these patches.

Changelog:

v1 -> v2:
- removed the earlyprintk in the command line
- added the stdout-path for the bootloader
- added the pinctrl configuration for all the node that need it
- renamed pca9555_ into expander
- added comment about the connector
- switched the PHY address to match the hardware
- removed the nr-ports property which is specific to the mv-sata and
  not the ahci
- removed the clock-frequency property of the sdhci node
- formatted the speed-map of gpio-fan with a newline between the map
  entries
- removed the SATA regulators
- added the dtsi for the Armada 388 variant

Gregory CLEMENT (5):
  ARM: mvebu: a38x: Add more pinctrl functions
  ARM: mvebu: a38x: Add missing labels
  ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC
  ARM: mvebu: Add Device Tree description of the Armada 388 SoC
  ARM: mvebu: Add Armada 385 General Purpose Development Board support

Maxime Ripard (3):
  ARM: mvebu: a38x: Fix node names
  ARM: mvebu: A38x: Remove redundant pinctrl informations
  ARM: mvebu: Add a number of pinctrl functions

 .../devicetree/bindings/arm/armada-38x.txt         |   7 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/armada-380.dtsi                  |   3 +-
 arch/arm/boot/dts/armada-385-db.dts                |   2 +-
 arch/arm/boot/dts/armada-385-gp.dts                | 288 +++++++++++++++++++++
 arch/arm/boot/dts/armada-385-rd.dts                |   2 +-
 arch/arm/boot/dts/armada-385.dtsi                  |   3 +-
 arch/arm/boot/dts/armada-388.dtsi                  |  58 +++++
 arch/arm/boot/dts/armada-38x.dtsi                  |  93 ++++++-
 9 files changed, 447 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/boot/dts/armada-385-gp.dts
 create mode 100644 arch/arm/boot/dts/armada-388.dtsi

-- 
1.9.1

[PATCH v2 1/8] ARM: mvebu: a38x: Fix node names

[Gregory CLEMENT]

From: Maxime Ripard <maxime.ripard@free-electrons.com>

Some nodes in the DTs have a reg property but no unit name in their node name.

This contradicts the way the ePAPR defines the node names. Fix this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/armada-380.dtsi   | 2 +-
 arch/arm/boot/dts/armada-385-db.dts | 2 +-
 arch/arm/boot/dts/armada-385-rd.dts | 2 +-
 arch/arm/boot/dts/armada-385.dtsi   | 2 +-
 arch/arm/boot/dts/armada-38x.dtsi   | 4 ++--
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index 4173a8ab34e7..13400ce88c54 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -32,7 +32,7 @@
 
 	soc {
 		internal-regs {
-			pinctrl {
+			pinctrl at 18000 {
 				compatible = "marvell,mv88f6810-pinctrl";
 				reg = <0x18000 0x20>;
 			};
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
index 2aaa9d2ac284..212605ccc7b6 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -74,7 +74,7 @@
 				phy-mode = "rgmii-id";
 			};
 
-			mdio {
+			mdio at 72004 {
 				phy0: ethernet-phy at 0 {
 					reg = <0>;
 				};
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
index aaca2861dc87..74a3bfe6efd7 100644
--- a/arch/arm/boot/dts/armada-385-rd.dts
+++ b/arch/arm/boot/dts/armada-385-rd.dts
@@ -67,7 +67,7 @@
 			};
 
 
-			mdio {
+			mdio at 72004 {
 				phy0: ethernet-phy at 0 {
 					reg = <0>;
 				};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 6283d7912f71..5249a4d3c207 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -37,7 +37,7 @@
 
 	soc {
 		internal-regs {
-			pinctrl {
+			pinctrl at 18000 {
 				compatible = "marvell,mv88f6820-pinctrl";
 				reg = <0x18000 0x20>;
 			};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 74391dace9e7..ada1f206028b 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -193,7 +193,7 @@
 				status = "disabled";
 			};
 
-			pinctrl {
+			pinctrl at 18000 {
 				compatible = "marvell,mv88f6820-pinctrl";
 				reg = <0x18000 0x20>;
 			};
@@ -373,7 +373,7 @@
 				status = "disabled";
 			};
 
-			mdio {
+			mdio at 72004 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "marvell,orion-mdio";
-- 
1.9.1

[PATCH v2 2/8] ARM: mvebu: A38x: Remove redundant pinctrl informations

[Gregory CLEMENT]

From: Maxime Ripard <maxime.ripard@free-electrons.com>

The compatible set in the armada-38x DTSI is always overridden, and the reg
defined in there is duplicated in the armada-380 and armada-385 DTSIs.

Remove these useless items.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/armada-380.dtsi | 1 -
 arch/arm/boot/dts/armada-385.dtsi | 1 -
 arch/arm/boot/dts/armada-38x.dtsi | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index 13400ce88c54..7e509d2d74d0 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -34,7 +34,6 @@
 		internal-regs {
 			pinctrl at 18000 {
 				compatible = "marvell,mv88f6810-pinctrl";
-				reg = <0x18000 0x20>;
 			};
 		};
 
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 5249a4d3c207..a54a252ddb4c 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -39,7 +39,6 @@
 		internal-regs {
 			pinctrl at 18000 {
 				compatible = "marvell,mv88f6820-pinctrl";
-				reg = <0x18000 0x20>;
 			};
 		};
 
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index ada1f206028b..40200084c6c8 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -194,7 +194,6 @@
 			};
 
 			pinctrl at 18000 {
-				compatible = "marvell,mv88f6820-pinctrl";
 				reg = <0x18000 0x20>;
 			};
 
-- 
1.9.1

[PATCH v2 3/8] ARM: mvebu: Add a number of pinctrl functions

[Gregory CLEMENT]

From: Maxime Ripard <maxime.ripard@free-electrons.com>

Some pinctrl functions can be shared with all DTS out there, since they are
generic, SoC-wide muxing options. Add a number of these to the DTSI to avoid
duplication.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 40200084c6c8..98885c58be29 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -195,6 +195,45 @@
 
 			pinctrl at 18000 {
 				reg = <0x18000 0x20>;
+
+				ge0_rgmii_pins: ge-rgmii-pins-0 {
+					marvell,pins = "mpp6", "mpp7", "mpp8",
+						       "mpp9", "mpp10", "mpp11",
+						       "mpp12", "mpp13", "mpp14",
+						       "mpp15", "mpp16", "mpp17";
+					marvell,function = "ge0";
+				};
+
+				i2c0_pins: i2c-pins-0 {
+					marvell,pins = "mpp2", "mpp3";
+					marvell,function = "i2c0";
+				};
+
+				mdio_pins: mdio-pins {
+					marvell,pins = "mpp4", "mpp5";
+					marvell,function = "ge";
+				};
+
+				ref_clk0_pins: ref-clk-pins-0 {
+					marvell,pins = "mpp45";
+					marvell,function = "ref";
+				};
+
+				spi1_pins: spi-pins-1 {
+					marvell,pins = "mpp56", "mpp57", "mpp58",
+						       "mpp59";
+					marvell,function = "spi1";
+				};
+
+				uart0_pins: uart-pins-0 {
+					marvell,pins = "mpp0", "mpp1";
+					marvell,function = "ua0";
+				};
+
+				uart1_pins: uart-pins-1 {
+					marvell,pins = "mpp19", "mpp20";
+					marvell,function = "ua1";
+				};
 			};
 
 			gpio0: gpio at 18100 {
-- 
1.9.1

[PATCH v2 4/8] ARM: mvebu: a38x: Add more pinctrl functions

[Gregory CLEMENT]

With the Armada 385 GP board more pinctrl functions depending of the
SoC are needed. Add them to the DTSI to avoid duplication.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 47 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 98885c58be29..63fe15174fee 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -204,6 +204,14 @@
 					marvell,function = "ge0";
 				};
 
+				ge1_rgmii_pins: ge-rgmii-pins-1 {
+					marvell,pins = "mpp21", "mpp27", "mpp28",
+						       "mpp29", "mpp30", "mpp31",
+						       "mpp32", "mpp37", "mpp38",
+						       "mpp39", "mpp40", "mpp41";
+					marvell,function = "ge1";
+				};
+
 				i2c0_pins: i2c-pins-0 {
 					marvell,pins = "mpp2", "mpp3";
 					marvell,function = "i2c0";
@@ -219,6 +227,17 @@
 					marvell,function = "ref";
 				};
 
+				ref_clk1_pins: ref-clk-pins-1 {
+					marvell,pins = "mpp46";
+					marvell,function = "ref";
+				};
+
+				spi0_pins: spi-pins-0 {
+					marvell,pins = "mpp22", "mpp23", "mpp24",
+						       "mpp25";
+					marvell,function = "spi0";
+				};
+
 				spi1_pins: spi-pins-1 {
 					marvell,pins = "mpp56", "mpp57", "mpp58",
 						       "mpp59";
@@ -234,6 +253,34 @@
 					marvell,pins = "mpp19", "mpp20";
 					marvell,function = "ua1";
 				};
+
+				sdhci_pins: sdhci-pins {
+					marvell,pins = "mpp48", "mpp49", "mpp50",
+						       "mpp52", "mpp53", "mpp54",
+						       "mpp55", "mpp57", "mpp58",
+						       "mpp59";
+					marvell,function = "sd0";
+				};
+
+				sata0_pins: sata-pins-0 {
+					marvell,pins = "mpp20";
+					marvell,function = "sata0";
+				};
+
+				sata1_pins: sata-pins-1 {
+					marvell,pins = "mpp19";
+					marvell,function = "sata1";
+				};
+
+				sata2_pins: sata-pins-2 {
+					marvell,pins = "mpp47";
+					marvell,function = "sata2";
+				};
+
+				sata3_pins: sata-pins-3 {
+					marvell,pins = "mpp44";
+					marvell,function = "sata3";
+				};
 			};
 
 			gpio0: gpio at 18100 {
-- 
1.9.1

[PATCH v2 5/8] ARM: mvebu: a38x: Add missing labels

[Gregory CLEMENT]

The pintcrl label was missing. Adding it allowed referring it from the
root of the device tree. Also add the uart0 label used by the
bootloader.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 63fe15174fee..04fe80d101f8 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -173,7 +173,7 @@
 				status = "disabled";
 			};
 
-			serial at 12000 {
+			uart0: serial at 12000 {
 				compatible = "snps,dw-apb-uart";
 				reg = <0x12000 0x100>;
 				reg-shift = <2>;
@@ -193,7 +193,7 @@
 				status = "disabled";
 			};
 
-			pinctrl at 18000 {
+			pinctrl: pinctrl at 18000 {
 				reg = <0x18000 0x20>;
 
 				ge0_rgmii_pins: ge-rgmii-pins-0 {
-- 
1.9.1

[PATCH v2 6/8] ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC

[Gregory CLEMENT]

Update the binding documentation of the Armada 38x Soc family with
the Armada 388.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 Documentation/devicetree/bindings/arm/armada-38x.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt
index ad9f8ed4d9bd..202953f1887e 100644
--- a/Documentation/devicetree/bindings/arm/armada-38x.txt
+++ b/Documentation/devicetree/bindings/arm/armada-38x.txt
@@ -15,6 +15,13 @@ Required root node property:
 
 compatible: must contain "marvell,armada385"
 
+In addition, boards using the Marvell Armada 388 SoC shall have the
+following property before the previous one:
+
+Required root node property:
+
+compatible: must contain "marvell,armada388"
+
 Example:
 
 compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
-- 
1.9.1

[PATCH v2 7/8] ARM: mvebu: Add Device Tree description of the Armada 388 SoC

[Gregory CLEMENT]

This SoC belongs to the Armada 38x family. The main difference with
the Armada 385 is that the 388 can handle two more SATA
ports. Currently the only consequence is the use of a different
compatible string for the pinctrl node, in order to be able to use the
pins associated to this 2 new SATA ports.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/armada-388.dtsi | 58 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-388.dtsi

diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi
new file mode 100644
index 000000000000..c762ff7ed1d1
--- /dev/null
+++ b/arch/arm/boot/dts/armada-388.dtsi
@@ -0,0 +1,58 @@
+/*
+ * Device Tree Include file for Marvell Armada 388 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ * The main difference with the Armada 385 is that the 388 can handle two more
+ * SATA ports. So we can reuse the dtsi of the Armada 385 and just override
+ * the pinctrl property and the name of the SoC.
+ */
+
+#include "armada-385.dtsi"
+
+/ {
+	model = "Marvell Armada 388 family SoC";
+	compatible = "marvell,armada388", "marvell,armada380";
+	soc {
+		internal-regs {
+			pinctrl at 18000 {
+				compatible = "marvell,mv88f6828-pinctrl";
+			};
+		};
+	};
+};
-- 
1.9.1

[PATCH v2 8/8] ARM: mvebu: Add Armada 385 General Purpose Development Board support

[Gregory CLEMENT]

The A385-GP is a board produced by Marvell that holds

- 1 PCIe slot
- 2 mini PCIe slot (one of them is multiplexed with the PCIe slot,
  muxing is selected through the GPIO expander)
- 1 16MB SPI-NOR
- 2 Gigabit Ethernet ports
- 4 SATA ports (2 of them are multiplexed with the mini PCIe slots,
  muxing is selected through the GPIO expander)
- 1 SDIO slot
- 1 USB3 port
- 2 USB2 port
- 2 GPIO/interrupts expander on I2C

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/Makefile          |   1 +
 arch/arm/boot/dts/armada-385-gp.dts | 288 ++++++++++++++++++++++++++++++++++++
 2 files changed, 289 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-385-gp.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 91bd5bd62857..d6d7bafac127 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -535,6 +535,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \
 	armada-375-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_38X) += \
 	armada-385-db.dtb \
+	armada-385-gp.dtb \
 	armada-385-rd.dtb
 dtb-$(CONFIG_MACH_ARMADA_XP) += \
 	armada-xp-axpwifiap.dtb \
diff --git a/arch/arm/boot/dts/armada-385-gp.dts b/arch/arm/boot/dts/armada-385-gp.dts
new file mode 100644
index 000000000000..66cd006e8478
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-gp.dts
@@ -0,0 +1,288 @@
+/*
+ * Device Tree file for Marvell Armada 385 development board
+ * (RD-88F6820-GP)
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-388.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Marvell Armada 385 GP";
+	compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = &uart0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2 GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi at 10600 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi0_pins>;
+				status = "okay";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "st,m25p128";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <50000000>;
+					m25p,fast-read;
+				};
+			};
+
+			i2c at 11000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins>;
+				status = "okay";
+				clock-frequency = <100000>;
+				/*
+				 * The EEPROM located at adresse 54 is needed
+				 * for the boot - DO NOT ERASE IT -
+				 */
+
+				expander0: pca9555 at 20 {
+					compatible = "nxp,pca9555";
+					pinctrl-names = "default";
+					pinctrl-0 = <&pca0_pins>;
+					interrupt-parent = <&gpio0>;
+					interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					reg = <0x20>;
+				};
+
+				expander1: pca9555 at 21 {
+					compatible = "nxp,pca9555";
+					pinctrl-names = "default";
+					interrupt-parent = <&gpio0>;
+					interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					reg = <0x21>;
+				};
+
+			};
+
+			serial at 12000 {
+				/*
+				 * Exported on the micro USB connector CON16
+				 * through an FTDI
+				 */
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart0_pins>;
+				status = "okay";
+			};
+
+			/* GE1 CON15 */
+			ethernet at 30000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&ge1_rgmii_pins>;
+				status = "okay";
+				phy = <&phy1>;
+				phy-mode = "rgmii-id";
+			};
+
+			/* CON4 */
+			usb at 50000 {
+				vcc-supply = <&reg_usb2_0_vbus>;
+				status = "okay";
+			};
+
+			/* GE0 CON1 */
+			ethernet at 70000 {
+				pinctrl-names = "default";
+				/*
+				 * The Reference Clock 0 is used to provide a
+				 * clock to the PHY
+				 */
+				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+				status = "okay";
+				phy = <&phy0>;
+				phy-mode = "rgmii-id";
+			};
+
+
+			mdio at 72004 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&mdio_pins>;
+
+				phy0: ethernet-phy at 1 {
+					reg = <1>;
+				};
+
+				phy1: ethernet-phy at 0 {
+					reg = <0>;
+				};
+			};
+
+			sata at a8000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
+				status = "okay";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			sata at e0000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
+				status = "okay";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			sdhci at d8000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdhci_pins>;
+				cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
+				no-1-8-v;
+				wp-inverted;
+				bus-width = <8>;
+				status = "okay";
+			};
+
+			/* CON5 */
+			usb3 at f0000 {
+				vcc-supply = <&reg_usb2_1_vbus>;
+				status = "okay";
+			};
+
+			/* CON7 */
+			usb3 at f8000 {
+				vcc-supply = <&reg_usb3_vbus>;
+				status = "okay";
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+			/*
+			 * One PCIe units is accessible through
+			 * standard PCIe slot on the board.
+			 */
+			pcie at 1,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+
+			/*
+			 * The two other PCIe units are accessible
+			 * through mini PCIe slot on the board.
+			 */
+			pcie at 2,0 {
+				/* Port 1, Lane 0 */
+				status = "okay";
+			};
+			pcie at 3,0 {
+				/* Port 2, Lane 0 */
+				status = "okay";
+			};
+		};
+
+		gpio-fan {
+			compatible = "gpio-fan";
+			gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
+			gpio-fan,speed-map = <	 0 0
+								  3000 1>;
+		};
+	};
+
+	reg_usb3_vbus: usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb3-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_usb2_0_vbus: v5-vbus0 {
+		compatible = "regulator-fixed";
+		regulator-name = "v5.0-vbus0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_usb2_1_vbus: v5-vbus1 {
+		compatible = "regulator-fixed";
+		regulator-name = "v5.0-vbus1";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_usb2_1_vbus: v5-vbus1 {
+		compatible = "regulator-fixed";
+		regulator-name = "v5.0-vbus1";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&pinctrl {
+	pca0_pins: pca0_pins {
+		marvell,pins = "mpp18";
+		marvell,function = "gpio";
+	};
+};
-- 
1.9.1

[PATCH v2 8/8] ARM: mvebu: Add Armada 385 General Purpose Development Board support

[Andrew Lunn]

On Thu, Jan 08, 2015 at 11:51:45AM +0100, Gregory CLEMENT wrote:

> +		gpio-fan {
> +			compatible = "gpio-fan";
> +			gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
> +			gpio-fan,speed-map = <	 0 0
> +								  3000 1>;
> +		};
> +	};

Hi Gregory

The indentation is a bit off here. If there are no other comments, i
can fix it as i add it to mvebu/dt.

    Andrew

[PATCH v2 7/8] ARM: mvebu: Add Device Tree description of the Armada 388 SoC

[Thomas Petazzoni]

Dear Gregory CLEMENT,

On Thu,  8 Jan 2015 11:51:44 +0100, Gregory CLEMENT wrote:
> This SoC belongs to the Armada 38x family. The main difference with
> the Armada 385 is that the 388 can handle two more SATA
> ports. Currently the only consequence is the use of a different
> compatible string for the pinctrl node, in order to be able to use the
> pins associated to this 2 new SATA ports.

I am not sure the pinmux is the only difference. Read on below.

> +#include "armada-385.dtsi"
> +
> +/ {
> +	model = "Marvell Armada 388 family SoC";
> +	compatible = "marvell,armada388", "marvell,armada380";
> +	soc {

Please, one empty new line between the last property (compatible) and
the "soc" node.

> +		internal-regs {
> +			pinctrl at 18000 {
> +				compatible = "marvell,mv88f6828-pinctrl";
> +			};
> +		};
> +	};
> +};

So, the 380 and 385 have two SATA ports, presumably ports 0 and 1.
According to the Functional Specifications, section 3.1 (Internal
Address map), those two ports are located at 0xA8000. Ports 2 and 3,
which are only available on Armada 388, are located at 0xE0100 and
0xE0180 according to the same datasheet. So I believe that the node:

			sata at a8000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xa8000 0x2000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 15>;
				status = "disabled";
			};

should stay where it is in armada-38x.dtsi.

However, the node:

			sata at e0000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xe0000 0x2000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 30>;
				status = "disabled";
			};

should probably move into armada-388.dtsi, since it covers ports 2 and
3.

In addition, I believe that the existing armada-385-db.dts and
armada-385-rd.dts should be renamed to armada-388-db.dts and
armada-388-rd.dts, and they should include armada-388.dtsi instead. At
least it's sure for the DB (which has both SATA controllers enabled).
For the RD, it remains to be confirmed, but in general most Marvell
development platforms use the superset SoC, which has all the
functionalities.

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v2 6/8] ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC

[Thomas Petazzoni]

Dear Gregory CLEMENT,

On Thu,  8 Jan 2015 11:51:43 +0100, Gregory CLEMENT wrote:
> Update the binding documentation of the Armada 38x Soc family with
> the Armada 388.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/arm/armada-38x.txt | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt
> index ad9f8ed4d9bd..202953f1887e 100644
> --- a/Documentation/devicetree/bindings/arm/armada-38x.txt
> +++ b/Documentation/devicetree/bindings/arm/armada-38x.txt
> @@ -15,6 +15,13 @@ Required root node property:
>  
>  compatible: must contain "marvell,armada385"
>  
> +In addition, boards using the Marvell Armada 388 SoC shall have the
> +following property before the previous one:

So before "marvell,armada385" ? So we want to have:

 compatible = "<board>", "marvell,armada388", "marvell,armada385", "marvell,armada380";

 ?

That's not what you do in the new armada-385-gp.dts. The 388 is a
superset of the 385, which itself is a superset of the 380. Should this
be reflected in this list of compatible strings?

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v2 7/8] ARM: mvebu: Add Device Tree description of the Armada 388 SoC

[Gregory CLEMENT]

Hi Thomas,

On 08/01/2015 15:54, Thomas Petazzoni wrote:
> Dear Gregory CLEMENT,
> 
> On Thu,  8 Jan 2015 11:51:44 +0100, Gregory CLEMENT wrote:
>> This SoC belongs to the Armada 38x family. The main difference with
>> the Armada 385 is that the 388 can handle two more SATA
>> ports. Currently the only consequence is the use of a different
>> compatible string for the pinctrl node, in order to be able to use the
>> pins associated to this 2 new SATA ports.
> 
> I am not sure the pinmux is the only difference. Read on below.
> 
>> +#include "armada-385.dtsi"
>> +
>> +/ {
>> +	model = "Marvell Armada 388 family SoC";
>> +	compatible = "marvell,armada388", "marvell,armada380";
>> +	soc {
> 
> Please, one empty new line between the last property (compatible) and
> the "soc" node.
> 
>> +		internal-regs {
>> +			pinctrl at 18000 {
>> +				compatible = "marvell,mv88f6828-pinctrl";
>> +			};
>> +		};
>> +	};
>> +};
> 
> So, the 380 and 385 have two SATA ports, presumably ports 0 and 1.
> According to the Functional Specifications, section 3.1 (Internal
> Address map), those two ports are located at 0xA8000. Ports 2 and 3,
> which are only available on Armada 388, are located at 0xE0100 and
> 0xE0180 according to the same datasheet. So I believe that the node:
> 
> 			sata at a8000 {
> 				compatible = "marvell,armada-380-ahci";
> 				reg = <0xa8000 0x2000>;
> 				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> 				clocks = <&gateclk 15>;
> 				status = "disabled";
> 			};
> 
> should stay where it is in armada-38x.dtsi.
> 
> However, the node:
> 
> 			sata at e0000 {
> 				compatible = "marvell,armada-380-ahci";
> 				reg = <0xe0000 0x2000>;
> 				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> 				clocks = <&gateclk 30>;
> 				status = "disabled";
> 			};
> 
> should probably move into armada-388.dtsi, since it covers ports 2 and
> 3.

I will do this.

> 
> In addition, I believe that the existing armada-385-db.dts and
> armada-385-rd.dts should be renamed to armada-388-db.dts and
> armada-388-rd.dts, and they should include armada-388.dtsi instead. At
> least it's sure for the DB (which has both SATA controllers enabled).
> For the RD, it remains to be confirmed, but in general most Marvell
> development platforms use the superset SoC, which has all the
> functionalities.

The RD also uses 4 SATA ports and also the pin which are only associated
to the Armada 388, so it seems also be this Soc. I will convert them.


Thanks,

Gregory


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com