[PATCH v4 0/9] ARM: sun9i: Enable MMC support on Allwinner A80

[PATCH v4 0/9] ARM: sun9i: Enable MMC support on Allwinner A80

[Chen-Yu Tsai]

Hi Maxime,

This is v4 of the sun9i mmc series. The following patches from v3
were merged and are dropped:

    ARM: dts: sun9i: Add pinmux setting for mmc0
    ARM: dts: sunxi: Use label to reference pio in sunxi-common-regulators
    ARM: dts: sun9i: Add mmc module clock nodes for A80
    clk: sunxi: Add a common setup function for mmc module clocks

Hopefully this is the last version, and we can get everything in for
3.20. If you've finished your clock-indices work, feel free to skip:

    ARM: dts: sun9i: Add clock-indices property for bus gate clocks

Changes since v3:

  - Rearranged device nodes in a80 optimus board dts according
    to alphabetical order.
  - Fixed check on of_io_request_and_map() call in mod0 clock

Cheers
ChenYu Tsai


Original cover letter from v3:

This series enables MMC support on the A80 using existing drivers
we have. The A80 has 4 MMC controllers. These controllers share
a common clock gate and reset control, which are then sub-divided
to each controller.

The phase clocks are the same as the older SoCs, so it should be
straight forward to add them with the rest of the sunxi family.
I did find that Allwinner's kernel uses different delay values
for the A80, but so far I've not run into any issues using the
mainline kernel.

Patch 1 adds a generic setup function for the mmc module/phase
clocks, which is re-used in patch 2.

Patch 2 adds module 0 type clock support for the A80. These are
essentially the same as mod0 clocks on other Allwinner SoCs, except
for the wider mux bits.

Patch 3 adds mmc mod clocks to the DTSI.

Patch 4 adds support for the mmc config (term from user manual) clocks.
This is the part that breaks out the clock gates and reset controls
for each controller. This is implemented as a platform driver, as
the shared reset control must be de-asserted for any of either this
or the mmc blocks to work.

Patch 5 adds clock-indices properties to the AHB/APB gate clocks.
This is needed for of_clk_get_parent_name to work properly, as we
use bit indices instead of counting the entries.

Patch 6 adds the mmc config clock nodes to the DTSI.

Patch 7 changes sunxi-common-regulators.dtsi to use labels to
reference the pio node.

Patch 8 adds the mmc controller nodes to the DTSI.

Patch 9 and 12 add the pinmux settings for mmc0 and mmc2.

Patch 10 converts the a80 optimus board dts to using label references,
which is the preferred way, before enabling any new devices.

Patch 11 and 13 enable mmc0 and mmc2 on the A80 Optimus Board.

Kudos to Andreas for figuring out all the DT bits. His SoB
is on the relevant patches.

Changes since v2:

  - Rebased onto current sunxi-next and sunxi mmc phase clock
    series v3
  - Added patch "clk: sunxi: Add a common setup function for
    mmc module clocks"
  - Use new common setup function for a80 mmc module clocks
  - Added patch "ARM: dts: sun9i: Convert a80 optimus board
    dts to label referencing"
  - Use label referencing in a80 optimus board dts

Changes since v1:

  - Use sunxi-common-regulators.dtsi for vmmc regulator
  - Rebased onto sunxi mmc phase clock series v2
  - Use new multi-output mmc module clock style
  - Rename sun9i mmc config clock name and compatible
  - Make mmc2_pins include all pins needed, and change
    name to mmc2_8bit_pins
  - Add spaces between pin names in mmc pins
  - Add clk_prepare_enable()/clk_disable_unprepare() calls to
    reset control ops for the mmc config clock
  - Use DIV_ROUND_UP when calculating number of clocks in sun9i
    mmc config clock probe function
  - Add required properties and outputs section for sun9i mmc
    config clock in bindings doc; also add an example


Chen-Yu Tsai (9):
  clk: sunxi: Add mod0 and mmc module clock support for A80
  clk: sunxi: Add driver for A80 MMC config clocks/resets
  ARM: dts: sun9i: Add clock-indices property for bus gate clocks
  ARM: dts: sun9i: Add mmc config clock nodes
  ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsi
  ARM: dts: sun9i: Convert a80 optimus board dts to label referencing
  ARM: dts: sun9i: Enable mmc0 on A80 Optimus Board
  ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2
  ARM: dts: sun9i: Enable mmc2 on A80 Optimus Board

 Documentation/devicetree/bindings/clock/sunxi.txt |  30 ++-
 arch/arm/boot/dts/sun9i-a80-optimus.dts           | 103 ++++++----
 arch/arm/boot/dts/sun9i-a80.dtsi                  |  80 ++++++++
 drivers/clk/sunxi/Makefile                        |   1 +
 drivers/clk/sunxi/clk-mod0.c                      |  32 ++++
 drivers/clk/sunxi/clk-sun9i-mmc.c                 | 222 ++++++++++++++++++++++
 6 files changed, 427 insertions(+), 41 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-sun9i-mmc.c

-- 
2.1.4

[PATCH v4 1/9] clk: sunxi: Add mod0 and mmc module clock support for A80

[Chen-Yu Tsai]

The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.

As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.

This patch adds support for both.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  7 +++--
 drivers/clk/sunxi/clk-mod0.c                      | 32 +++++++++++++++++++++++
 2 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index e4c42276c577..0dfd018ba47b 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -56,7 +56,9 @@ Required properties:
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
 	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
+	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
 	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
+	"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
 	"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
 	"allwinner,sun7i-a20-out-clk" - for the external output clocks
 	"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
@@ -72,7 +74,8 @@ Required properties for all clocks:
 - #clock-cells : from common clock binding; shall be set to 0 except for
 	the following compatibles where it shall be set to 1:
 	"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
-	"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
+	"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
+	"allwinner,*-usb-clk", "allwinner,*-mmc-clk"
 - clock-output-names : shall be the corresponding names of the outputs.
 	If the clock module only has one output, the name shall be the
 	module name.
@@ -94,7 +97,7 @@ For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
 is the normal PLL6 output, or "pll6". The second output is rate doubled
 PLL6, or "pll6x2".
 
-The "allwinner,sun4i-a10-mmc-clk" has three different outputs: the
+The "allwinner,*-mmc-clk" clocks have three different outputs: the
 main clock, with the ID 0, and the output and sample clocks, with the
 IDs 1 and 2, respectively.
 
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 4430d1398ce6..ec8f5a1fca09 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -130,6 +130,30 @@ static struct platform_driver sun4i_a10_mod0_clk_driver = {
 };
 module_platform_driver(sun4i_a10_mod0_clk_driver);
 
+static const struct factors_data sun9i_a80_mod0_data __initconst = {
+	.enable = 31,
+	.mux = 24,
+	.muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
+	.table = &sun4i_a10_mod0_config,
+	.getter = sun4i_a10_get_mod0_factors,
+};
+
+static void __init sun9i_a80_mod0_setup(struct device_node *node)
+{
+	void __iomem *reg;
+
+	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+	if (IS_ERR(reg)) {
+		pr_err("Could not get registers for mod0-clk: %s\n",
+		       node->name);
+		return;
+	}
+
+	sunxi_factors_register(node, &sun9i_a80_mod0_data,
+			       &sun4i_a10_mod0_lock, reg);
+}
+CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);
+
 static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
 
 static void __init sun5i_a13_mbus_setup(struct device_node *node)
@@ -358,3 +382,11 @@ static void __init sun4i_a10_mmc_setup(struct device_node *node)
 	sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock);
 }
 CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);
+
+static DEFINE_SPINLOCK(sun9i_a80_mmc_lock);
+
+static void __init sun9i_a80_mmc_setup(struct device_node *node)
+{
+	sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock);
+}
+CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);
-- 
2.1.4

[PATCH v4 2/9] clk: sunxi: Add driver for A80 MMC config clocks/resets

[Chen-Yu Tsai]

On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  25 ++-
 drivers/clk/sunxi/Makefile                        |   1 +
 drivers/clk/sunxi/clk-sun9i-mmc.c                 | 222 ++++++++++++++++++++++
 3 files changed, 247 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi/clk-sun9i-mmc.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0dfd018ba47b..60b44285250d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -57,6 +57,7 @@ Required properties:
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
 	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
 	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
+	"allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
 	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
 	"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
 	"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
@@ -75,7 +76,8 @@ Required properties for all clocks:
 	the following compatibles where it shall be set to 1:
 	"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
 	"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
-	"allwinner,*-usb-clk", "allwinner,*-mmc-clk"
+	"allwinner,*-usb-clk", "allwinner,*-mmc-clk",
+	"allwinner,*-mmc-config-clk"
 - clock-output-names : shall be the corresponding names of the outputs.
 	If the clock module only has one output, the name shall be the
 	module name.
@@ -83,6 +85,10 @@ Required properties for all clocks:
 And "allwinner,*-usb-clk" clocks also require:
 - reset-cells : shall be set to 1
 
+The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
+- #reset-cells : shall be set to 1
+- resets : shall be the reset control phandle for the mmc block.
+
 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
 
@@ -101,6 +107,10 @@ The "allwinner,*-mmc-clk" clocks have three different outputs: the
 main clock, with the ID 0, and the output and sample clocks, with the
 IDs 1 and 2, respectively.
 
+The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
+per mmc controller. The number of outputs is determined by the size of
+the address block, which is related to the overall mmc block.
+
 For example:
 
 osc24M: clk at 01c20050 {
@@ -176,3 +186,16 @@ gmac_clk: clk at 01c20164 {
 	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 	clock-output-names = "gmac";
 };
+
+mmc_config_clk: clk at 01c13000 {
+	compatible = "allwinner,sun9i-a80-mmc-config-clk";
+	reg = <0x01c13000 0x10>;
+	clocks = <&ahb0_gates 8>;
+	clock-names = "ahb";
+	resets = <&ahb0_resets 8>;
+	reset-names = "ahb";
+	#clock-cells = <1>;
+	#reset-cells = <1>;
+	clock-output-names = "mmc0_config", "mmc1_config",
+			     "mmc2_config", "mmc3_config";
+};
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index a66953c0f430..3a5292e3fcf8 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -8,6 +8,7 @@ obj-y += clk-a20-gmac.o
 obj-y += clk-mod0.o
 obj-y += clk-sun8i-mbus.o
 obj-y += clk-sun9i-core.o
+obj-y += clk-sun9i-mmc.o
 
 obj-$(CONFIG_MFD_SUN6I_PRCM) += \
 	clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
diff --git a/drivers/clk/sunxi/clk-sun9i-mmc.c b/drivers/clk/sunxi/clk-sun9i-mmc.c
new file mode 100644
index 000000000000..aeb3a52e0a9f
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun9i-mmc.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2013 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai	<wens@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/reset.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+
+#define SUN9I_MMC_WIDTH		4
+
+#define SUN9I_MMC_GATE_BIT	16
+#define SUN9I_MMC_RESET_BIT	18
+
+struct sun9i_mmc_clk_data {
+	spinlock_t			lock;
+	void __iomem			*membase;
+	struct clk			*clk;
+	struct reset_control		*reset;
+	struct clk_onecell_data		clk_data;
+	struct reset_controller_dev	rcdev;
+};
+
+static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct sun9i_mmc_clk_data *data = container_of(rcdev,
+						       struct sun9i_mmc_clk_data,
+						       rcdev);
+	unsigned long flags;
+	void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
+	u32 val;
+
+	clk_prepare_enable(data->clk);
+	spin_lock_irqsave(&data->lock, flags);
+
+	val = readl(reg);
+	writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
+
+	spin_unlock_irqrestore(&data->lock, flags);
+	clk_disable_unprepare(data->clk);
+
+	return 0;
+}
+
+static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct sun9i_mmc_clk_data *data = container_of(rcdev,
+						       struct sun9i_mmc_clk_data,
+						       rcdev);
+	unsigned long flags;
+	void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
+	u32 val;
+
+	clk_prepare_enable(data->clk);
+	spin_lock_irqsave(&data->lock, flags);
+
+	val = readl(reg);
+	writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);
+
+	spin_unlock_irqrestore(&data->lock, flags);
+	clk_disable_unprepare(data->clk);
+
+	return 0;
+}
+
+static struct reset_control_ops sun9i_mmc_reset_ops = {
+	.assert		= sun9i_mmc_reset_assert,
+	.deassert	= sun9i_mmc_reset_deassert,
+};
+
+static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct sun9i_mmc_clk_data *data;
+	struct clk_onecell_data *clk_data;
+	const char *clk_name = np->name;
+	const char *clk_parent;
+	struct resource *r;
+	int count, i, ret;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	spin_lock_init(&data->lock);
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	/* one clock/reset pair per word */
+	count = DIV_ROUND_UP((r->end - r->start + 1), SUN9I_MMC_WIDTH);
+	data->membase = devm_ioremap_resource(&pdev->dev, r);
+	if (IS_ERR(data->membase))
+		return PTR_ERR(data->membase);
+
+	clk_data = &data->clk_data;
+	clk_data->clk_num = count;
+	clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
+				      GFP_KERNEL);
+	if (!clk_data->clks)
+		return -ENOMEM;
+
+	clk_parent = of_clk_get_parent_name(np, 0);
+	if (!clk_parent)
+		return -EINVAL;
+
+	data->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(data->clk)) {
+		dev_err(&pdev->dev, "Could not get clock\n");
+		return PTR_ERR(data->clk);
+	}
+
+	data->reset = devm_reset_control_get(&pdev->dev, NULL);
+	if (IS_ERR(data->reset)) {
+		dev_err(&pdev->dev, "Could not get reset control\n");
+		return PTR_ERR(data->reset);
+	}
+
+	ret = reset_control_deassert(data->reset);
+	if (ret) {
+		dev_err(&pdev->dev, "Reset deassert err %d\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < count; i++) {
+		of_property_read_string_index(np, "clock-output-names",
+					      i, &clk_name);
+
+		clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
+						      clk_parent, 0,
+						      data->membase + SUN9I_MMC_WIDTH * i,
+						      SUN9I_MMC_GATE_BIT, 0,
+						      &data->lock);
+
+		if (IS_ERR(clk_data->clks[i])) {
+			ret = PTR_ERR(clk_data->clks[i]);
+			goto err_clk_register;
+		}
+	}
+
+	ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+	if (ret)
+		goto err_clk_provider;
+
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.nr_resets = count;
+	data->rcdev.ops = &sun9i_mmc_reset_ops;
+	data->rcdev.of_node = pdev->dev.of_node;
+
+	ret = reset_controller_register(&data->rcdev);
+	if (ret)
+		goto err_rc_reg;
+
+	platform_set_drvdata(pdev, data);
+
+	return 0;
+
+err_rc_reg:
+	of_clk_del_provider(np);
+
+err_clk_provider:
+	for (i = 0; i < count; i++)
+		clk_unregister(clk_data->clks[i]);
+
+err_clk_register:
+	reset_control_assert(data->reset);
+
+	return ret;
+}
+
+static int sun9i_a80_mmc_config_clk_remove(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct sun9i_mmc_clk_data *data = platform_get_drvdata(pdev);
+	struct clk_onecell_data *clk_data = &data->clk_data;
+	int i;
+
+	reset_controller_unregister(&data->rcdev);
+	of_clk_del_provider(np);
+	for (i = 0; i < clk_data->clk_num; i++)
+		clk_unregister(clk_data->clks[i]);
+
+	reset_control_assert(data->reset);
+
+	return 0;
+}
+
+static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = {
+	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver sun9i_a80_mmc_config_clk_driver = {
+	.driver = {
+		.name = "sun9i-a80-mmc-config-clk",
+		.of_match_table = sun9i_a80_mmc_config_clk_dt_ids,
+	},
+	.probe = sun9i_a80_mmc_config_clk_probe,
+	.remove = sun9i_a80_mmc_config_clk_remove,
+};
+module_platform_driver(sun9i_a80_mmc_config_clk_driver);
+
+MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
+MODULE_DESCRIPTION("Allwinner A80 MMC clock/reset Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.4

[PATCH v4 3/9] ARM: dts: sun9i: Add clock-indices property for bus gate clocks

[Chen-Yu Tsai]

of_clk_get_parent_name() uses the clock-indices property to resolve
clock phandle arguments in case that the argument index does not
match the clock-output-names sequence.

This is the case on sunxi, where we use the actual bit index as the
argument to the phandle. Add the clock-indices property so that
of_clk_get_parent_name() resolves the names correctly.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 267ed149a5fa..820b4c5995f3 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -260,6 +260,9 @@
 			compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
 			reg = <0x06000580 0x4>;
 			clocks = <&ahb0>;
+			clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
+					<14>, <15>, <16>, <18>, <20>, <21>,
+					<22>, <23>;
 			clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
 					"ahb0_ss", "ahb0_sd", "ahb0_nand1",
 					"ahb0_nand0", "ahb0_sdram",
@@ -273,6 +276,7 @@
 			compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
 			reg = <0x06000584 0x4>;
 			clocks = <&ahb1>;
+			clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
 			clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
 					"ahb1_gmac", "ahb1_msgbox",
 					"ahb1_spinlock", "ahb1_hstimer",
@@ -284,6 +288,8 @@
 			compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
 			reg = <0x06000588 0x4>;
 			clocks = <&ahb2>;
+			clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
+					<11>;
 			clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
 					"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
 					"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
@@ -294,6 +300,8 @@
 			compatible = "allwinner,sun9i-a80-apb0-gates-clk";
 			reg = <0x06000590 0x4>;
 			clocks = <&apb0>;
+			clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
+					<17>, <18>, <19>;
 			clock-output-names = "apb0_spdif", "apb0_pio",
 					"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 					"apb0_lradc", "apb0_gpadc", "apb0_twd",
@@ -305,6 +313,8 @@
 			compatible = "allwinner,sun9i-a80-apb1-gates-clk";
 			reg = <0x06000594 0x4>;
 			clocks = <&apb1>;
+			clock-indices = <0>, <1>, <2>, <3>, <4>,
+					<16>, <17>, <18>, <19>, <20>, <21>;
 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
 					"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
 					"apb1_uart0", "apb1_uart1",
-- 
2.1.4

[PATCH v4 4/9] ARM: dts: sun9i: Add mmc config clock nodes

[Chen-Yu Tsai]

Add the device tree nodes for the mmc config clock nodes.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 820b4c5995f3..1925c89ee701 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -333,6 +333,19 @@
 		 */
 		ranges = <0 0 0 0x20000000>;
 
+		mmc_config_clk: clk at 01c13000 {
+			compatible = "allwinner,sun9i-a80-mmc-config-clk";
+			reg = <0x01c13000 0x10>;
+			clocks = <&ahb0_gates 8>;
+			clock-names = "ahb";
+			resets = <&ahb0_resets 8>;
+			reset-names = "ahb";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			clock-output-names = "mmc0_config", "mmc1_config",
+					     "mmc2_config", "mmc3_config";
+		};
+
 		gic: interrupt-controller at 01c41000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c41000 0x1000>,
-- 
2.1.4

[PATCH v4 5/9] ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsi

[Chen-Yu Tsai]

The A80 has 4 mmc controllers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Andreas F?rber <afaerber@suse.de>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 1925c89ee701..7387fb2a5111 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -333,6 +333,54 @@
 		 */
 		ranges = <0 0 0 0x20000000>;
 
+		mmc0: mmc at 01c0f000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
+				 <&mmc0_clk 1>, <&mmc0_clk 2>;
+			clock-names = "ahb", "mmc", "output", "sample";
+			resets = <&mmc_config_clk 0>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		mmc1: mmc at 01c10000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
+				 <&mmc1_clk 1>, <&mmc1_clk 2>;
+			clock-names = "ahb", "mmc", "output", "sample";
+			resets = <&mmc_config_clk 1>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		mmc2: mmc at 01c11000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
+				 <&mmc2_clk 1>, <&mmc2_clk 2>;
+			clock-names = "ahb", "mmc", "output", "sample";
+			resets = <&mmc_config_clk 2>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		mmc3: mmc at 01c12000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c12000 0x1000>;
+			clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
+				 <&mmc3_clk 1>, <&mmc3_clk 2>;
+			clock-names = "ahb", "mmc", "output", "sample";
+			resets = <&mmc_config_clk 3>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
 		mmc_config_clk: clk at 01c13000 {
 			compatible = "allwinner,sun9i-a80-mmc-config-clk";
 			reg = <0x01c13000 0x10>;
-- 
2.1.4

[PATCH v4 6/9] ARM: dts: sun9i: Convert a80 optimus board dts to label referencing

[Chen-Yu Tsai]

The preferred method of referencing nodes from the dtsi is to use
labels, instead of copying the complete tree.

This patch converts sun9i-a80-optimus.dts to use label references.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 76 ++++++++++++++++-----------------
 1 file changed, 37 insertions(+), 39 deletions(-)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 58f5cb346519..d4f3866a8d0b 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -61,45 +61,6 @@
 		bootargs = "earlyprintk console=ttyS0,115200";
 	};
 
-	soc {
-		pio: pinctrl at 06000800 {
-			i2c3_pins_a: i2c3 at 0 {
-				/* Enable internal pull-up */
-				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-			};
-
-			led_pins_optimus: led-pins at 0 {
-				allwinner,pins = "PH0", "PH1";
-				allwinner,function = "gpio_out";
-				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			uart4_pins_a: uart4 at 0 {
-				/* Enable internal pull-up */
-				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-			};
-		};
-
-		uart0: serial at 07000000 {
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart0_pins_a>;
-			status = "okay";
-		};
-
-		uart4: serial at 07001000 {
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart4_pins_a>;
-			status = "okay";
-		};
-
-		i2c3: i2c at 07003400 {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c3_pins_a>;
-			status = "okay";
-		};
-	};
-
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
@@ -120,3 +81,40 @@
 		};
 	};
 };
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins_a>;
+	status = "okay";
+};
+
+&i2c3_pins_a {
+	/* Enable internal pull-up */
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&pio {
+	led_pins_optimus: led-pins at 0 {
+		allwinner,pins = "PH0", "PH1";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pins_a>;
+	status = "okay";
+};
+
+&uart4_pins_a {
+	/* Enable internal pull-up */
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
-- 
2.1.4

[PATCH v4 7/9] ARM: dts: sun9i: Enable mmc0 on A80 Optimus Board

[Chen-Yu Tsai]

Enable the micro-sd slot on the A80 Optimus Board, which is connected to
mmc0. This adds the card-detect gpio and enables mmc0.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Andreas F?rber <afaerber@suse.de>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index d4f3866a8d0b..5c9505a724d4 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -49,6 +49,7 @@
 
 /dts-v1/;
 #include "sun9i-a80.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
@@ -100,6 +101,23 @@
 		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
+
+	mmc0_cd_pin_optimus: mmc0_cd_pin at 0 {
+		allwinner,pins = "PH18";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>;
+	vmmc-supply = <&reg_vcc3v0>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
+	cd-inverted;
+	status = "okay";
 };
 
 &uart0 {
-- 
2.1.4

[PATCH v4 8/9] ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2

[Chen-Yu Tsai]

mmc2 is available on port C. Add a pinmux setting for 8 bit wide eMMC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Andreas F?rber <afaerber@suse.de>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 7387fb2a5111..9e28ffc6dd90 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -478,6 +478,15 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			mmc2_8bit_pins: mmc2_8bit {
+				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+						 "PC10", "PC11", "PC12",
+						 "PC13", "PC14", "PC15";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			uart0_pins_a: uart0 at 0 {
 				allwinner,pins = "PH12", "PH13";
 				allwinner,function = "uart0";
-- 
2.1.4

[PATCH v4 9/9] ARM: dts: sun9i: Enable mmc2 on A80 Optimus Board

[Chen-Yu Tsai]

The A80 Optimus Board has a 16GB eMMC connected to mmc2, with 8 bit
wide data bus.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Andreas F?rber <afaerber@suse.de>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 5c9505a724d4..c4de9cb9a5f6 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -120,6 +120,15 @@
 	status = "okay";
 };
 
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_vcc3v0>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
-- 
2.1.4

[PATCH v4 1/9] clk: sunxi: Add mod0 and mmc module clock support for A80

[Maxime Ripard]

On Sat, Jan 17, 2015 at 01:19:26PM +0800, Chen-Yu Tsai wrote:
> The module 0 style clocks, or storage module clocks as named in the
> official SDK, are almost the same as the module 0 clocks on earlier
> Allwinner SoCs. The only difference is wider mux register bits.
> 
> As with earlier Allwinner SoCs, mmc module clocks are a special case
> of mod0 clocks, with phase controls for 2 child clocks, output and
> sample.
> 
> This patch adds support for both.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 2/9] clk: sunxi: Add driver for A80 MMC config clocks/resets

[Maxime Ripard]

Hi,

On Sat, Jan 17, 2015 at 01:19:27PM +0800, Chen-Yu Tsai wrote:
> On the A80 SoC, the 4 mmc controllers each have a separate register
> controlling their register access clocks and reset controls. These
> registers in turn share a ahb clock gate and reset control.
> 
> This patch adds a platform device driver for these controls. It
> requires both clocks and reset controls to be available, so using
> CLK_OF_DECLARE might not be the best way.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  25 ++-
>  drivers/clk/sunxi/Makefile                        |   1 +
>  drivers/clk/sunxi/clk-sun9i-mmc.c                 | 222 ++++++++++++++++++++++
>  3 files changed, 247 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/sunxi/clk-sun9i-mmc.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 0dfd018ba47b..60b44285250d 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -57,6 +57,7 @@ Required properties:
>  	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
>  	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
>  	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
> +	"allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
>  	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
>  	"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
>  	"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
> @@ -75,7 +76,8 @@ Required properties for all clocks:
>  	the following compatibles where it shall be set to 1:
>  	"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
>  	"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
> -	"allwinner,*-usb-clk", "allwinner,*-mmc-clk"
> +	"allwinner,*-usb-clk", "allwinner,*-mmc-clk",
> +	"allwinner,*-mmc-config-clk"
>  - clock-output-names : shall be the corresponding names of the outputs.
>  	If the clock module only has one output, the name shall be the
>  	module name.
> @@ -83,6 +85,10 @@ Required properties for all clocks:
>  And "allwinner,*-usb-clk" clocks also require:
>  - reset-cells : shall be set to 1
>  
> +The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
> +- #reset-cells : shall be set to 1
> +- resets : shall be the reset control phandle for the mmc block.
> +
>  For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
>  dummy clocks at 25 MHz and 125 MHz, respectively. See example.
>  
> @@ -101,6 +107,10 @@ The "allwinner,*-mmc-clk" clocks have three different outputs: the
>  main clock, with the ID 0, and the output and sample clocks, with the
>  IDs 1 and 2, respectively.
>  
> +The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
> +per mmc controller. The number of outputs is determined by the size of
> +the address block, which is related to the overall mmc block.
> +
>  For example:
>  
>  osc24M: clk at 01c20050 {
> @@ -176,3 +186,16 @@ gmac_clk: clk at 01c20164 {
>  	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
>  	clock-output-names = "gmac";
>  };
> +
> +mmc_config_clk: clk at 01c13000 {
> +	compatible = "allwinner,sun9i-a80-mmc-config-clk";
> +	reg = <0x01c13000 0x10>;
> +	clocks = <&ahb0_gates 8>;
> +	clock-names = "ahb";
> +	resets = <&ahb0_resets 8>;
> +	reset-names = "ahb";
> +	#clock-cells = <1>;
> +	#reset-cells = <1>;
> +	clock-output-names = "mmc0_config", "mmc1_config",
> +			     "mmc2_config", "mmc3_config";
> +};
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index a66953c0f430..3a5292e3fcf8 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -8,6 +8,7 @@ obj-y += clk-a20-gmac.o
>  obj-y += clk-mod0.o
>  obj-y += clk-sun8i-mbus.o
>  obj-y += clk-sun9i-core.o
> +obj-y += clk-sun9i-mmc.o
>  
>  obj-$(CONFIG_MFD_SUN6I_PRCM) += \
>  	clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
> diff --git a/drivers/clk/sunxi/clk-sun9i-mmc.c b/drivers/clk/sunxi/clk-sun9i-mmc.c
> new file mode 100644
> index 000000000000..aeb3a52e0a9f
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun9i-mmc.c
> @@ -0,0 +1,222 @@
> +/*
> + * Copyright 2013 Chen-Yu Tsai
> + *
> + * Chen-Yu Tsai	<wens@csie.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/reset.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +
> +#define SUN9I_MMC_WIDTH		4
> +
> +#define SUN9I_MMC_GATE_BIT	16
> +#define SUN9I_MMC_RESET_BIT	18
> +
> +struct sun9i_mmc_clk_data {
> +	spinlock_t			lock;
> +	void __iomem			*membase;
> +	struct clk			*clk;
> +	struct reset_control		*reset;
> +	struct clk_onecell_data		clk_data;
> +	struct reset_controller_dev	rcdev;
> +};
> +
> +static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
> +			      unsigned long id)
> +{
> +	struct sun9i_mmc_clk_data *data = container_of(rcdev,
> +						       struct sun9i_mmc_clk_data,
> +						       rcdev);
> +	unsigned long flags;
> +	void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
> +	u32 val;
> +
> +	clk_prepare_enable(data->clk);
> +	spin_lock_irqsave(&data->lock, flags);
> +
> +	val = readl(reg);
> +	writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
> +
> +	spin_unlock_irqrestore(&data->lock, flags);
> +	clk_disable_unprepare(data->clk);
> +
> +	return 0;
> +}
> +
> +static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
> +				unsigned long id)
> +{
> +	struct sun9i_mmc_clk_data *data = container_of(rcdev,
> +						       struct sun9i_mmc_clk_data,
> +						       rcdev);
> +	unsigned long flags;
> +	void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
> +	u32 val;
> +
> +	clk_prepare_enable(data->clk);
> +	spin_lock_irqsave(&data->lock, flags);
> +
> +	val = readl(reg);
> +	writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);
> +
> +	spin_unlock_irqrestore(&data->lock, flags);
> +	clk_disable_unprepare(data->clk);
> +
> +	return 0;
> +}
> +
> +static struct reset_control_ops sun9i_mmc_reset_ops = {
> +	.assert		= sun9i_mmc_reset_assert,
> +	.deassert	= sun9i_mmc_reset_deassert,
> +};
> +
> +static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct sun9i_mmc_clk_data *data;
> +	struct clk_onecell_data *clk_data;
> +	const char *clk_name = np->name;
> +	const char *clk_parent;
> +	struct resource *r;
> +	int count, i, ret;
> +
> +	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
> +	if (!data)
> +		return -ENOMEM;
> +
> +	spin_lock_init(&data->lock);
> +
> +	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	/* one clock/reset pair per word */
> +	count = DIV_ROUND_UP((r->end - r->start + 1), SUN9I_MMC_WIDTH);
> +	data->membase = devm_ioremap_resource(&pdev->dev, r);
> +	if (IS_ERR(data->membase))
> +		return PTR_ERR(data->membase);
> +
> +	clk_data = &data->clk_data;
> +	clk_data->clk_num = count;
> +	clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
> +				      GFP_KERNEL);
> +	if (!clk_data->clks)
> +		return -ENOMEM;
> +
> +	clk_parent = of_clk_get_parent_name(np, 0);
> +	if (!clk_parent)
> +		return -EINVAL;
> +
> +	data->clk = devm_clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(data->clk)) {
> +		dev_err(&pdev->dev, "Could not get clock\n");
> +		return PTR_ERR(data->clk);
> +	}

I'm wondering, why are you using of_clk_get_parent_name here, instead
of __clk_get_name on data->clk? That would avoid parsing the DT while
we already have that info.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 3/9] ARM: dts: sun9i: Add clock-indices property for bus gate clocks

[Maxime Ripard]

On Sat, Jan 17, 2015 at 01:19:28PM +0800, Chen-Yu Tsai wrote:
> of_clk_get_parent_name() uses the clock-indices property to resolve
> clock phandle arguments in case that the argument index does not
> match the clock-output-names sequence.
> 
> This is the case on sunxi, where we use the actual bit index as the
> argument to the phandle. Add the clock-indices property so that
> of_clk_get_parent_name() resolves the names correctly.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Did you change anything in that patch?

I already applied it from v3, so let me know if I need to drop it.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 4/9] ARM: dts: sun9i: Add mmc config clock nodes

[Maxime Ripard]

On Sat, Jan 17, 2015 at 01:19:29PM +0800, Chen-Yu Tsai wrote:
> Add the device tree nodes for the mmc config clock nodes.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 5/9] ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsi

[Maxime Ripard]

On Sat, Jan 17, 2015 at 01:19:30PM +0800, Chen-Yu Tsai wrote:
> The A80 has 4 mmc controllers.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Andreas F?rber <afaerber@suse.de>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 6/9] ARM: dts: sun9i: Convert a80 optimus board dts to label referencing

[Maxime Ripard]

On Sat, Jan 17, 2015 at 01:19:31PM +0800, Chen-Yu Tsai wrote:
> The preferred method of referencing nodes from the dtsi is to use
> labels, instead of copying the complete tree.
> 
> This patch converts sun9i-a80-optimus.dts to use label references.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 7/9] ARM: dts: sun9i: Enable mmc0 on A80 Optimus Board

[Maxime Ripard]

On Sat, Jan 17, 2015 at 01:19:32PM +0800, Chen-Yu Tsai wrote:
> Enable the micro-sd slot on the A80 Optimus Board, which is connected to
> mmc0. This adds the card-detect gpio and enables mmc0.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Andreas F?rber <afaerber@suse.de>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 8/9] ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2

[Maxime Ripard]

On Sat, Jan 17, 2015 at 01:19:33PM +0800, Chen-Yu Tsai wrote:
> mmc2 is available on port C. Add a pinmux setting for 8 bit wide eMMC.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Andreas F?rber <afaerber@suse.de>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 9/9] ARM: dts: sun9i: Enable mmc2 on A80 Optimus Board

[Maxime Ripard]

On Sat, Jan 17, 2015 at 01:19:34PM +0800, Chen-Yu Tsai wrote:
> The A80 Optimus Board has a 16GB eMMC connected to mmc2, with 8 bit
> wide data bus.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Andreas F?rber <afaerber@suse.de>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v4 3/9] ARM: dts: sun9i: Add clock-indices property for bus gate clocks

[Chen-Yu Tsai]

On Tue, Jan 20, 2015 at 5:59 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Sat, Jan 17, 2015 at 01:19:28PM +0800, Chen-Yu Tsai wrote:
>> of_clk_get_parent_name() uses the clock-indices property to resolve
>> clock phandle arguments in case that the argument index does not
>> match the clock-output-names sequence.
>>
>> This is the case on sunxi, where we use the actual bit index as the
>> argument to the phandle. Add the clock-indices property so that
>> of_clk_get_parent_name() resolves the names correctly.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> Did you change anything in that patch?
>
> I already applied it from v3, so let me know if I need to drop it.

Please drop it. I just didn't realize you merged it after our
discussion.

ChenYu

[PATCH v4 2/9] clk: sunxi: Add driver for A80 MMC config clocks/resets

[Chen-Yu Tsai]

On Tue, Jan 20, 2015 at 5:57 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sat, Jan 17, 2015 at 01:19:27PM +0800, Chen-Yu Tsai wrote:
>> On the A80 SoC, the 4 mmc controllers each have a separate register
>> controlling their register access clocks and reset controls. These
>> registers in turn share a ahb clock gate and reset control.
>>
>> This patch adds a platform device driver for these controls. It
>> requires both clocks and reset controls to be available, so using
>> CLK_OF_DECLARE might not be the best way.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt |  25 ++-
>>  drivers/clk/sunxi/Makefile                        |   1 +
>>  drivers/clk/sunxi/clk-sun9i-mmc.c                 | 222 ++++++++++++++++++++++
>>  3 files changed, 247 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/clk/sunxi/clk-sun9i-mmc.c
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index 0dfd018ba47b..60b44285250d 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -57,6 +57,7 @@ Required properties:
>>       "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
>>       "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
>>       "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
>> +     "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
>>       "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
>>       "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
>>       "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
>> @@ -75,7 +76,8 @@ Required properties for all clocks:
>>       the following compatibles where it shall be set to 1:
>>       "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
>>       "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
>> -     "allwinner,*-usb-clk", "allwinner,*-mmc-clk"
>> +     "allwinner,*-usb-clk", "allwinner,*-mmc-clk",
>> +     "allwinner,*-mmc-config-clk"
>>  - clock-output-names : shall be the corresponding names of the outputs.
>>       If the clock module only has one output, the name shall be the
>>       module name.
>> @@ -83,6 +85,10 @@ Required properties for all clocks:
>>  And "allwinner,*-usb-clk" clocks also require:
>>  - reset-cells : shall be set to 1
>>
>> +The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
>> +- #reset-cells : shall be set to 1
>> +- resets : shall be the reset control phandle for the mmc block.
>> +
>>  For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
>>  dummy clocks at 25 MHz and 125 MHz, respectively. See example.
>>
>> @@ -101,6 +107,10 @@ The "allwinner,*-mmc-clk" clocks have three different outputs: the
>>  main clock, with the ID 0, and the output and sample clocks, with the
>>  IDs 1 and 2, respectively.
>>
>> +The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
>> +per mmc controller. The number of outputs is determined by the size of
>> +the address block, which is related to the overall mmc block.
>> +
>>  For example:
>>
>>  osc24M: clk at 01c20050 {
>> @@ -176,3 +186,16 @@ gmac_clk: clk at 01c20164 {
>>       clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
>>       clock-output-names = "gmac";
>>  };
>> +
>> +mmc_config_clk: clk at 01c13000 {
>> +     compatible = "allwinner,sun9i-a80-mmc-config-clk";
>> +     reg = <0x01c13000 0x10>;
>> +     clocks = <&ahb0_gates 8>;
>> +     clock-names = "ahb";
>> +     resets = <&ahb0_resets 8>;
>> +     reset-names = "ahb";
>> +     #clock-cells = <1>;
>> +     #reset-cells = <1>;
>> +     clock-output-names = "mmc0_config", "mmc1_config",
>> +                          "mmc2_config", "mmc3_config";
>> +};
>> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
>> index a66953c0f430..3a5292e3fcf8 100644
>> --- a/drivers/clk/sunxi/Makefile
>> +++ b/drivers/clk/sunxi/Makefile
>> @@ -8,6 +8,7 @@ obj-y += clk-a20-gmac.o
>>  obj-y += clk-mod0.o
>>  obj-y += clk-sun8i-mbus.o
>>  obj-y += clk-sun9i-core.o
>> +obj-y += clk-sun9i-mmc.o
>>
>>  obj-$(CONFIG_MFD_SUN6I_PRCM) += \
>>       clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
>> diff --git a/drivers/clk/sunxi/clk-sun9i-mmc.c b/drivers/clk/sunxi/clk-sun9i-mmc.c
>> new file mode 100644
>> index 000000000000..aeb3a52e0a9f
>> --- /dev/null
>> +++ b/drivers/clk/sunxi/clk-sun9i-mmc.c
>> @@ -0,0 +1,222 @@
>> +/*
>> + * Copyright 2013 Chen-Yu Tsai
>> + *
>> + * Chen-Yu Tsai      <wens@csie.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/reset.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/spinlock.h>
>> +
>> +#define SUN9I_MMC_WIDTH              4
>> +
>> +#define SUN9I_MMC_GATE_BIT   16
>> +#define SUN9I_MMC_RESET_BIT  18
>> +
>> +struct sun9i_mmc_clk_data {
>> +     spinlock_t                      lock;
>> +     void __iomem                    *membase;
>> +     struct clk                      *clk;
>> +     struct reset_control            *reset;
>> +     struct clk_onecell_data         clk_data;
>> +     struct reset_controller_dev     rcdev;
>> +};
>> +
>> +static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
>> +                           unsigned long id)
>> +{
>> +     struct sun9i_mmc_clk_data *data = container_of(rcdev,
>> +                                                    struct sun9i_mmc_clk_data,
>> +                                                    rcdev);
>> +     unsigned long flags;
>> +     void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
>> +     u32 val;
>> +
>> +     clk_prepare_enable(data->clk);
>> +     spin_lock_irqsave(&data->lock, flags);
>> +
>> +     val = readl(reg);
>> +     writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
>> +
>> +     spin_unlock_irqrestore(&data->lock, flags);
>> +     clk_disable_unprepare(data->clk);
>> +
>> +     return 0;
>> +}
>> +
>> +static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
>> +                             unsigned long id)
>> +{
>> +     struct sun9i_mmc_clk_data *data = container_of(rcdev,
>> +                                                    struct sun9i_mmc_clk_data,
>> +                                                    rcdev);
>> +     unsigned long flags;
>> +     void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
>> +     u32 val;
>> +
>> +     clk_prepare_enable(data->clk);
>> +     spin_lock_irqsave(&data->lock, flags);
>> +
>> +     val = readl(reg);
>> +     writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);
>> +
>> +     spin_unlock_irqrestore(&data->lock, flags);
>> +     clk_disable_unprepare(data->clk);
>> +
>> +     return 0;
>> +}
>> +
>> +static struct reset_control_ops sun9i_mmc_reset_ops = {
>> +     .assert         = sun9i_mmc_reset_assert,
>> +     .deassert       = sun9i_mmc_reset_deassert,
>> +};
>> +
>> +static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
>> +{
>> +     struct device_node *np = pdev->dev.of_node;
>> +     struct sun9i_mmc_clk_data *data;
>> +     struct clk_onecell_data *clk_data;
>> +     const char *clk_name = np->name;
>> +     const char *clk_parent;
>> +     struct resource *r;
>> +     int count, i, ret;
>> +
>> +     data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
>> +     if (!data)
>> +             return -ENOMEM;
>> +
>> +     spin_lock_init(&data->lock);
>> +
>> +     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +     /* one clock/reset pair per word */
>> +     count = DIV_ROUND_UP((r->end - r->start + 1), SUN9I_MMC_WIDTH);
>> +     data->membase = devm_ioremap_resource(&pdev->dev, r);
>> +     if (IS_ERR(data->membase))
>> +             return PTR_ERR(data->membase);
>> +
>> +     clk_data = &data->clk_data;
>> +     clk_data->clk_num = count;
>> +     clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
>> +                                   GFP_KERNEL);
>> +     if (!clk_data->clks)
>> +             return -ENOMEM;
>> +
>> +     clk_parent = of_clk_get_parent_name(np, 0);
>> +     if (!clk_parent)
>> +             return -EINVAL;
>> +
>> +     data->clk = devm_clk_get(&pdev->dev, NULL);
>> +     if (IS_ERR(data->clk)) {
>> +             dev_err(&pdev->dev, "Could not get clock\n");
>> +             return PTR_ERR(data->clk);
>> +     }
>
> I'm wondering, why are you using of_clk_get_parent_name here, instead
> of __clk_get_name on data->clk? That would avoid parsing the DT while
> we already have that info.

I hadn't thought of that. I was sticking to public consumer APIs.
Do you want me to respin this one?

ChenYu

[PATCH v4 2/9] clk: sunxi: Add driver for A80 MMC config clocks/resets

[Maxime Ripard]

On Tue, Jan 20, 2015 at 10:13:05AM +0800, Chen-Yu Tsai wrote:
> >> +     clk_parent = of_clk_get_parent_name(np, 0);
> >> +     if (!clk_parent)
> >> +             return -EINVAL;
> >> +
> >> +     data->clk = devm_clk_get(&pdev->dev, NULL);
> >> +     if (IS_ERR(data->clk)) {
> >> +             dev_err(&pdev->dev, "Could not get clock\n");
> >> +             return PTR_ERR(data->clk);
> >> +     }
> >
> > I'm wondering, why are you using of_clk_get_parent_name here, instead
> > of __clk_get_name on data->clk? That would avoid parsing the DT while
> > we already have that info.
> 
> I hadn't thought of that. I was sticking to public consumer APIs.
> Do you want me to respin this one?

I don't think it's really a !consumer API. All it does is returning
clk->name, which is accessible even to consumers.

But yeah, please resend it.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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