[PATCH] ARM: decompressor: remove unused cache flush code

[PATCH] ARM: decompressor: remove unused cache flush code

[Masahiro Yamada]

As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b0000 because
ARMv7 requires a hierarchical cache implementation.
The line "mcr    p15, 0, r10, c7, c14, 0" is not reachable.

Moreover, the v7_flush_dcache_all in arch/arm/mm/cache-v7.S does not
check the ID_MMFR1.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/boot/compressed/head.S | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 9dff614..32f0d79 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -1085,15 +1085,9 @@ __armv6_mmu_cache_flush:
 __armv7_mmu_cache_flush:
 		tst	r4, #1
 		bne	iflush
-		mrc	p15, 0, r10, c0, c1, 5	@ read ID_MMFR1
-		tst	r10, #0xf << 16		@ hierarchical cache (ARMv7)
+		stmfd	sp!, {r0-r7, r9-r11}
 		mov	r10, #0
-		beq	hierarchical
-		mcr	p15, 0, r10, c7, c14, 0	@ clean+invalidate D
-		b	iflush
-hierarchical:
 		mcr	p15, 0, r10, c7, c10, 5	@ DMB
-		stmfd	sp!, {r0-r7, r9-r11}
 		mrc	p15, 1, r0, c0, c0, 1	@ read clidr
 		ands	r3, r0, #0x7000000	@ extract loc from clidr
 		mov	r3, r3, lsr #23		@ left align loc bit field
-- 
1.9.1

[PATCH] ARM: decompressor: remove unused cache flush code

[Uwe Kleine-König]

Hello,

On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote:
> As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b0000 because
> ARMv7 requires a hierarchical cache implementation.
> The line "mcr    p15, 0, r10, c7, c14, 0" is not reachable.
> 
> Moreover, the v7_flush_dcache_all in arch/arm/mm/cache-v7.S does not
> check the ID_MMFR1.
> 
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
I stumbled about this some time ago, too. The thing is however that the
__armv7_mmu_cache functions are selected if
CPUID & 0x000f0000 == 0x000f0000, and that is (AFAIK at present only
theoretically) not implying that we have an ARMv7 machine. Only that it
uses the "CPUID Identification Scheme" which is required on ARMv7.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH] ARM: decompressor: remove unused cache flush code

[Russell King - ARM Linux]

On Thu, Jan 22, 2015 at 09:06:47AM +0100, Uwe Kleine-K?nig wrote:
> Hello,
> 
> On Thu, Jan 22, 2015 at 02:22:58PM +0900, Masahiro Yamada wrote:
> > As ARM ARM says, the bit 19-16 of ID_MMFR1 is always 0b0000 because
> > ARMv7 requires a hierarchical cache implementation.
> > The line "mcr    p15, 0, r10, c7, c14, 0" is not reachable.
> > 
> > Moreover, the v7_flush_dcache_all in arch/arm/mm/cache-v7.S does not
> > check the ID_MMFR1.
> > 
> > Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> I stumbled about this some time ago, too. The thing is however that the
> __armv7_mmu_cache functions are selected if
> CPUID & 0x000f0000 == 0x000f0000, and that is (AFAIK at present only
> theoretically) not implying that we have an ARMv7 machine. Only that it
> uses the "CPUID Identification Scheme" which is required on ARMv7.

Correct, and there are ARMv6 CPUs which satisfy the "CPUID identification
scheme" test - and are probably not heirarchial.

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