From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Mon, 16 Feb 2015 17:49:20 +0100 [thread overview]
Message-ID: <20150216164920.GF25269@lukather> (raw)
In-Reply-To: <54E1F236.4090706@free-electrons.com>
On Mon, Feb 16, 2015 at 10:35:50AM -0300, Ezequiel Garcia wrote:
> On 02/16/2015 09:51 AM, Maxime Ripard wrote:
> > The NDDB register holds the data that are needed by the read and write
> > commands.
> >
> > However, during a read PIO access, the datasheet specifies that after each 32
> > bits read in that register, when BCH is enabled, we have to make sure that the
> > RDDREQ bit is set in the NDSR register.
> >
>
> Typo s/32 bits/32 bytes
Good catch, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2015-02-16 16:49 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-16 12:51 [PATCH v3 0/2] ARM: mvebu: a385-db-ap: Enable the NAND controller Maxime Ripard
2015-02-16 12:51 ` [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining Maxime Ripard
2015-02-16 13:34 ` Boris Brezillon
2015-02-16 13:35 ` Ezequiel Garcia
2015-02-16 16:49 ` Maxime Ripard [this message]
2015-02-16 16:27 ` Thomas Petazzoni
2015-02-16 16:41 ` Maxime Ripard
2015-02-16 16:57 ` Ezequiel Garcia
2015-02-17 10:29 ` Maxime Ripard
2015-02-16 20:11 ` Robert Jarzmik
2015-02-16 20:58 ` Maxime Ripard
2015-02-16 21:36 ` Robert Jarzmik
2015-02-17 9:47 ` Maxime Ripard
2015-02-17 10:37 ` Maxime Ripard
2015-02-17 17:07 ` Robert Jarzmik
2015-02-17 17:16 ` Ezequiel Garcia
2015-02-24 3:45 ` Brian Norris
2015-02-24 8:17 ` Maxime Ripard
2015-02-16 12:51 ` [PATCH v3 2/2] ARM: mvebu: a385-db-ap: Enable the NAND Maxime Ripard
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