[BUG] ARM: socfpga: L2 cache init

[s.trumtrar@pengutronix.de (Steffen Trumtrar)]

On Tue, Feb 24, 2015 at 05:55:05PM -0600, Dinh Nguyen wrote:
> On Tue, Feb 17, 2015 at 4:28 PM, Russell King - ARM Linux
> <linux@arm.linux.org.uk> wrote:
> > On Tue, Feb 17, 2015 at 04:00:47PM -0600, Dinh Nguyen wrote:
> >> On Fri, Feb 13, 2015 at 2:01 AM, Steffen Trumtrar
> >> <s.trumtrar@pengutronix.de> wrote:
> >> > Yes, seems very likely that Russell is right.
> >>
> >> The bug doesn't happen if I disable the L2. Digging more...
> >
> > What ensures that the value written to socfpga_cpu1start_addr (by
> > of_property_read_u32() in socfpga_sysmgr_init(), called at .init_irq
> > time) is visible to the secondary CPU?
> 
> Yes, I was able use a JTAG debugger and can see that the
> secondary CPU is not seeing socfpga_cpu1start_addr correctly when the
> error occurs.
> 

\o/ very good. That sounds like the bug can be fixed soon.

Thanks,
Steffen

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