From mboxrd@z Thu Jan  1 00:00:00 1970
From: mark.rutland@arm.com (Mark Rutland)
Date: Fri, 27 Feb 2015 19:08:03 +0000
Subject: [RFC PATCH] ARM64: cmpxchg.h: Clear the exclusive access bit on
 fail
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On Fri, Feb 27, 2015 at 06:44:19PM +0000, Pranith Kumar wrote:
> On Fri, Feb 27, 2015 at 1:33 PM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
> > It's either badly formatted or I don't get it. Are the "stxr x1" and
> > "stxr x7" happening on the same CPU (P0)? If yes, that's badly written
> > code, not even architecturally compliant (you are not allowed other
> > memory accesses between ldxr and stxr).
> 
> OK. Is that the same case with ldaxr (acquire) and stlxr (release)?
> AFAIK, memory accesses between acquire and release exclusive
> operations are allowed.

The restriction on memory accesses in the middle of a load-exclusive
store-exclusive sequence applies to all the load/store-exclusive
variants, including ldaxr and stlxr.

Thanks,
Mark.