From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Mon, 2 Mar 2015 17:00:28 +0000 Subject: [PATCH 2/3] ARM: DT: STi: STiH407: Add sata DT nodes. In-Reply-To: <1425300519-13747-3-git-send-email-peter.griffin@linaro.org> References: <1425300519-13747-1-git-send-email-peter.griffin@linaro.org> <1425300519-13747-3-git-send-email-peter.griffin@linaro.org> Message-ID: <20150302170028.GB6976@x1> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 02 Mar 2015, Peter Griffin wrote: > Now that the miphy28lp is upstream, we can add the sata dt nodes > for stih407 family silicon. This has been tested on b2120 board > J4 (sata0 channel). These nodes are disabled by default as a > special mini pci-e to sata daughter board is required which > isn't shipped with the board. > > Signed-off-by: Peter Griffin > --- > arch/arm/boot/dts/stih407-family.dtsi | 44 +++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) Acked-by: Lee Jones > diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi > index a57c06e..d526921 100644 > --- a/arch/arm/boot/dts/stih407-family.dtsi > +++ b/arch/arm/boot/dts/stih407-family.dtsi > @@ -338,6 +338,50 @@ > }; > }; > > + sata0: sata at 9b20000 { > + compatible = "st,ahci"; > + reg = <0x9b20000 0x1000>; > + > + interrupts = ; > + interrupt-names = "hostc"; > + > + phys = <&phy_port0 PHY_TYPE_SATA>; > + phy-names = "ahci_phy"; > + > + resets = <&powerdown STIH407_SATA0_POWERDOWN>, > + <&softreset STIH407_SATA0_SOFTRESET>, > + <&softreset STIH407_SATA0_PWR_SOFTRESET>; > + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; > + > + clock-names = "ahci_clk"; > + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; > + > + status = "disabled"; > + }; > + > + sata1: sata at 9b28000 { > + compatible = "st,ahci"; > + reg = <0x9b28000 0x1000>; > + > + interrupts = ; > + interrupt-names = "hostc"; > + > + phys = <&phy_port1 PHY_TYPE_SATA>; > + phy-names = "ahci_phy"; > + > + resets = <&powerdown STIH407_SATA1_POWERDOWN>, > + <&softreset STIH407_SATA1_SOFTRESET>, > + <&softreset STIH407_SATA1_PWR_SOFTRESET>; > + reset-names = "pwr-dwn", > + "sw-rst", > + "pwr-rst"; > + > + clock-names = "ahci_clk"; > + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; > + > + status = "disabled"; > + }; > + > st_dwc3: dwc3 at 8f94000 { > compatible = "st,stih407-dwc3"; > reg = <0x08f94000 0x1000>, <0x110 0x4>; -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog