[PATCH 0/3] at91-3.19: pm fixes

[PATCH 0/3] at91-3.19: pm fixes

[Wenyou Yang]

Hi Nicolas,

The patch serial is to fix the pm issue.

It is based on the branch: at91-3.19-fixes
git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git

Peter Rosin (1):
  pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.

Sylvain Rochet (2):
  pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts
  pm: at91: pm_slowclock: remove clocks which are already stopped when
    entering slow clock mode

 arch/arm/mach-at91/pm.c            |   12 +++++
 arch/arm/mach-at91/pm_slowclock.S  |  105 ++++++++++++++----------------------
 include/soc/at91/at91sam9_ddrsdr.h |    2 +-
 3 files changed, 54 insertions(+), 65 deletions(-)

-- 
1.7.9.5

Best Regards,
Wenyou Yang

[PATCH 1/3] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts

[Wenyou Yang]

From: Sylvain Rochet <sylvain.rochet@finsecur.com>

Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if
something went wrong instead of continuing in unknown condition. There
is not much we can do if a PLL lock never ends, we are running in SRAM
and we will not be able to connect back the sdram or ddram in order to
be able to fire up a message or just panic.

As a bonus, not decounting the timeout register in slow clock mode
reduce cumulated suspend time and resume time from ~17ms to ~15ms.

Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: Wenyou.Yang <wenyou.yang@atmel.com>
---
 arch/arm/mach-at91/pm_slowclock.S |   33 ++++-----------------------------
 1 file changed, 4 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 2001877..79dfdbe 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -34,11 +34,6 @@
  */
 #undef SLOWDOWN_MASTER_CLOCK
 
-#define MCKRDY_TIMEOUT		1000
-#define MOSCRDY_TIMEOUT 	1000
-#define PLLALOCK_TIMEOUT	1000
-#define PLLBLOCK_TIMEOUT	1000
-
 pmc	.req	r0
 sdramc	.req	r1
 ramc1	.req	r2
@@ -50,56 +45,36 @@ tmp2	.req	r5
  * Wait until master clock is ready (after switching master clock source)
  */
 	.macro wait_mckrdy
-	mov	tmp2, #MCKRDY_TIMEOUT
-1:	sub	tmp2, tmp2, #1
-	cmp	tmp2, #0
-	beq	2f
-	ldr	tmp1, [pmc, #AT91_PMC_SR]
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
 	tst	tmp1, #AT91_PMC_MCKRDY
 	beq	1b
-2:
 	.endm
 
 /*
  * Wait until master oscillator has stabilized.
  */
 	.macro wait_moscrdy
-	mov	tmp2, #MOSCRDY_TIMEOUT
-1:	sub	tmp2, tmp2, #1
-	cmp	tmp2, #0
-	beq	2f
-	ldr	tmp1, [pmc, #AT91_PMC_SR]
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
 	tst	tmp1, #AT91_PMC_MOSCS
 	beq	1b
-2:
 	.endm
 
 /*
  * Wait until PLLA has locked.
  */
 	.macro wait_pllalock
-	mov	tmp2, #PLLALOCK_TIMEOUT
-1:	sub	tmp2, tmp2, #1
-	cmp	tmp2, #0
-	beq	2f
-	ldr	tmp1, [pmc, #AT91_PMC_SR]
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
 	tst	tmp1, #AT91_PMC_LOCKA
 	beq	1b
-2:
 	.endm
 
 /*
  * Wait until PLLB has locked.
  */
 	.macro wait_pllblock
-	mov	tmp2, #PLLBLOCK_TIMEOUT
-1:	sub	tmp2, tmp2, #1
-	cmp	tmp2, #0
-	beq	2f
-	ldr	tmp1, [pmc, #AT91_PMC_SR]
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
 	tst	tmp1, #AT91_PMC_LOCKB
 	beq	1b
-2:
 	.endm
 
 	.text
-- 
1.7.9.5

[PATCH 1/3] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts

[Nicolas Ferre]

Le 05/02/2015 07:00, Wenyou Yang a ?crit :
> From: Sylvain Rochet <sylvain.rochet@finsecur.com>
> 
> Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if
> something went wrong instead of continuing in unknown condition. There
> is not much we can do if a PLL lock never ends, we are running in SRAM
> and we will not be able to connect back the sdram or ddram in order to
> be able to fire up a message or just panic.
> 
> As a bonus, not decounting the timeout register in slow clock mode
> reduce cumulated suspend time and resume time from ~17ms to ~15ms.
> 
> Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
> Acked-by: Wenyou.Yang <wenyou.yang@atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

and stacked in at91-4.0-fixes.
thanks!

> ---
>  arch/arm/mach-at91/pm_slowclock.S |   33 ++++-----------------------------
>  1 file changed, 4 insertions(+), 29 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index 2001877..79dfdbe 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
> @@ -34,11 +34,6 @@
>   */
>  #undef SLOWDOWN_MASTER_CLOCK
>  
> -#define MCKRDY_TIMEOUT		1000
> -#define MOSCRDY_TIMEOUT 	1000
> -#define PLLALOCK_TIMEOUT	1000
> -#define PLLBLOCK_TIMEOUT	1000
> -
>  pmc	.req	r0
>  sdramc	.req	r1
>  ramc1	.req	r2
> @@ -50,56 +45,36 @@ tmp2	.req	r5
>   * Wait until master clock is ready (after switching master clock source)
>   */
>  	.macro wait_mckrdy
> -	mov	tmp2, #MCKRDY_TIMEOUT
> -1:	sub	tmp2, tmp2, #1
> -	cmp	tmp2, #0
> -	beq	2f
> -	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
>  	tst	tmp1, #AT91_PMC_MCKRDY
>  	beq	1b
> -2:
>  	.endm
>  
>  /*
>   * Wait until master oscillator has stabilized.
>   */
>  	.macro wait_moscrdy
> -	mov	tmp2, #MOSCRDY_TIMEOUT
> -1:	sub	tmp2, tmp2, #1
> -	cmp	tmp2, #0
> -	beq	2f
> -	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
>  	tst	tmp1, #AT91_PMC_MOSCS
>  	beq	1b
> -2:
>  	.endm
>  
>  /*
>   * Wait until PLLA has locked.
>   */
>  	.macro wait_pllalock
> -	mov	tmp2, #PLLALOCK_TIMEOUT
> -1:	sub	tmp2, tmp2, #1
> -	cmp	tmp2, #0
> -	beq	2f
> -	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
>  	tst	tmp1, #AT91_PMC_LOCKA
>  	beq	1b
> -2:
>  	.endm
>  
>  /*
>   * Wait until PLLB has locked.
>   */
>  	.macro wait_pllblock
> -	mov	tmp2, #PLLBLOCK_TIMEOUT
> -1:	sub	tmp2, tmp2, #1
> -	cmp	tmp2, #0
> -	beq	2f
> -	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
>  	tst	tmp1, #AT91_PMC_LOCKB
>  	beq	1b
> -2:
>  	.endm
>  
>  	.text
> 


-- 
Nicolas Ferre

[PATCH 2/3] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode

[Wenyou Yang]

From: Sylvain Rochet <sylvain.rochet@finsecur.com>

Assume USB PLL and PLL B are already stopped before entering sleep mode,
print a warning if this isn't the case.

Removed PLL B from slow clock code, all drivers are supposed to properly
unprepare clocks.

Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: Wenyou.Yang <wenyou.yang@atmel.com>
---
 arch/arm/mach-at91/pm.c           |   12 ++++++++++++
 arch/arm/mach-at91/pm_slowclock.S |   31 -------------------------------
 2 files changed, 12 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 9b15169..1cfd6e9 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -98,6 +98,18 @@ static int at91_pm_verify_clocks(void)
 		}
 	}
 
+	/* Drivers should have previously suspended USB PLL */
+	if (at91_pmc_read(AT91_CKGR_UCKR) & AT91_PMC_UPLLEN) {
+		pr_err("AT91: PM - Suspend-to-RAM with USB PLL running\n");
+		return 0;
+	}
+
+	/* Drivers should have previously suspended PLL B */
+	if (at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) {
+		pr_err("AT91: PM - Suspend-to-RAM with PLL B running\n");
+		return 0;
+	}
+
 	return 1;
 }
 
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 79dfdbe..75d8b19 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -68,15 +68,6 @@ tmp2	.req	r5
 	beq	1b
 	.endm
 
-/*
- * Wait until PLLB has locked.
- */
-	.macro wait_pllblock
-1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
-	tst	tmp1, #AT91_PMC_LOCKB
-	beq	1b
-	.endm
-
 	.text
 
 /* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
@@ -182,13 +173,6 @@ sdr_sr_done:
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
-	/* Save PLLB setting and disable it */
-	ldr	tmp1, [pmc, #AT91_CKGR_PLLBR]
-	str	tmp1, .saved_pllbr
-
-	mov	tmp1, #AT91_PMC_PLLCOUNT
-	str	tmp1, [pmc, #AT91_CKGR_PLLBR]
-
 	/* Turn off the main oscillator */
 	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
 	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
@@ -204,18 +188,6 @@ sdr_sr_done:
 
 	wait_moscrdy
 
-	/* Restore PLLB setting */
-	ldr	tmp1, .saved_pllbr
-	str	tmp1, [pmc, #AT91_CKGR_PLLBR]
-
-	tst	tmp1, #(AT91_PMC_MUL &  0xff0000)
-	bne	1f
-	tst	tmp1, #(AT91_PMC_MUL & ~0xff0000)
-	beq	2f
-1:
-	wait_pllblock
-2:
-
 	/* Restore PLLA setting */
 	ldr	tmp1, .saved_pllar
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
@@ -294,9 +266,6 @@ ram_restored:
 .saved_pllar:
 	.word 0
 
-.saved_pllbr:
-	.word 0
-
 .saved_sam9_lpr:
 	.word 0
 
-- 
1.7.9.5

[PATCH 2/3] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode

[Nicolas Ferre]

Le 05/02/2015 07:01, Wenyou Yang a ?crit :
> From: Sylvain Rochet <sylvain.rochet@finsecur.com>
> 
> Assume USB PLL and PLL B are already stopped before entering sleep mode,
> print a warning if this isn't the case.
> 
> Removed PLL B from slow clock code, all drivers are supposed to properly
> unprepare clocks.
> 
> Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
> Acked-by: Wenyou.Yang <wenyou.yang@atmel.com>

I keep this one for 4.1 as all the USB drivers are not converted yet.

Bye,


> ---
>  arch/arm/mach-at91/pm.c           |   12 ++++++++++++
>  arch/arm/mach-at91/pm_slowclock.S |   31 -------------------------------
>  2 files changed, 12 insertions(+), 31 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 9b15169..1cfd6e9 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -98,6 +98,18 @@ static int at91_pm_verify_clocks(void)
>  		}
>  	}
>  
> +	/* Drivers should have previously suspended USB PLL */
> +	if (at91_pmc_read(AT91_CKGR_UCKR) & AT91_PMC_UPLLEN) {
> +		pr_err("AT91: PM - Suspend-to-RAM with USB PLL running\n");
> +		return 0;
> +	}
> +
> +	/* Drivers should have previously suspended PLL B */
> +	if (at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) {
> +		pr_err("AT91: PM - Suspend-to-RAM with PLL B running\n");
> +		return 0;
> +	}
> +
>  	return 1;
>  }
>  
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index 79dfdbe..75d8b19 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
> @@ -68,15 +68,6 @@ tmp2	.req	r5
>  	beq	1b
>  	.endm
>  
> -/*
> - * Wait until PLLB has locked.
> - */
> -	.macro wait_pllblock
> -1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
> -	tst	tmp1, #AT91_PMC_LOCKB
> -	beq	1b
> -	.endm
> -
>  	.text
>  
>  /* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
> @@ -182,13 +173,6 @@ sdr_sr_done:
>  	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
>  	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
>  
> -	/* Save PLLB setting and disable it */
> -	ldr	tmp1, [pmc, #AT91_CKGR_PLLBR]
> -	str	tmp1, .saved_pllbr
> -
> -	mov	tmp1, #AT91_PMC_PLLCOUNT
> -	str	tmp1, [pmc, #AT91_CKGR_PLLBR]
> -
>  	/* Turn off the main oscillator */
>  	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
>  	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
> @@ -204,18 +188,6 @@ sdr_sr_done:
>  
>  	wait_moscrdy
>  
> -	/* Restore PLLB setting */
> -	ldr	tmp1, .saved_pllbr
> -	str	tmp1, [pmc, #AT91_CKGR_PLLBR]
> -
> -	tst	tmp1, #(AT91_PMC_MUL &  0xff0000)
> -	bne	1f
> -	tst	tmp1, #(AT91_PMC_MUL & ~0xff0000)
> -	beq	2f
> -1:
> -	wait_pllblock
> -2:
> -
>  	/* Restore PLLA setting */
>  	ldr	tmp1, .saved_pllar
>  	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
> @@ -294,9 +266,6 @@ ram_restored:
>  .saved_pllar:
>  	.word 0
>  
> -.saved_pllbr:
> -	.word 0
> -
>  .saved_sam9_lpr:
>  	.word 0
>  
> 


-- 
Nicolas Ferre

[PATCH 2/3] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode

[Sylvain Rochet]

Hello Nicolas,

On Tue, Mar 03, 2015 at 07:42:26PM +0100, Nicolas Ferre wrote:
> Le 05/02/2015 07:01, Wenyou Yang a ?crit :
> > From: Sylvain Rochet <sylvain.rochet@finsecur.com>
> > 
> > Assume USB PLL and PLL B are already stopped before entering sleep mode,
> > print a warning if this isn't the case.
> > 
> > Removed PLL B from slow clock code, all drivers are supposed to properly
> > unprepare clocks.
> > 
> > Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
> > Acked-by: Wenyou.Yang <wenyou.yang@atmel.com>
> 
> I keep this one for 4.1 as all the USB drivers are not converted yet.

I agree we should wait to prevent a regression, in case you missed that 
I sent a v7 of my USBA PM support a few weeks ago (ping ;-).

Sylvain

[PATCH 2/3] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode

[Nicolas Ferre]

Le 03/03/2015 23:50, Sylvain Rochet a ?crit :
> Hello Nicolas,
> 
> On Tue, Mar 03, 2015 at 07:42:26PM +0100, Nicolas Ferre wrote:
>> Le 05/02/2015 07:01, Wenyou Yang a ?crit :
>>> From: Sylvain Rochet <sylvain.rochet@finsecur.com>
>>>
>>> Assume USB PLL and PLL B are already stopped before entering sleep mode,
>>> print a warning if this isn't the case.
>>>
>>> Removed PLL B from slow clock code, all drivers are supposed to properly
>>> unprepare clocks.
>>>
>>> Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
>>> Acked-by: Wenyou.Yang <wenyou.yang@atmel.com>
>>
>> I keep this one for 4.1 as all the USB drivers are not converted yet.
> 
> I agree we should wait to prevent a regression, in case you missed that 
> I sent a v7 of my USBA PM support a few weeks ago (ping ;-).
> 

Sylvain, your series are in linux-next so I take this patch for 4.1 in
at91-4.1-cleanup with my:

Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

But... I remove the arch/arm/mach-at91/pm.c part of this patch as it is
not really needed and adds a too strong dependency on the PMC in an
unrelated file...

Bye,
-- 
Nicolas Ferre

[PATCH 3/3] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.

[Wenyou Yang]

From: Peter Rosin <peda@axentia.se>

The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.

Assume that the second controller has the same fault, but that is
untested.

Signed-off-by: Peter Rosin <peda@axentia.se>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
 arch/arm/mach-at91/pm_slowclock.S  |   43 +++++++++++++++++++++++++++++++-----
 include/soc/at91/at91sam9_ddrsdr.h |    2 +-
 2 files changed, 39 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 75d8b19..487ae1e 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -109,6 +109,16 @@ ddr_sr_enable:
 	cmp	memctrl, #AT91_MEMCTRL_DDRSDR
 	bne	sdr_sr_enable
 
+	/* LPDDR1 --> force DDR2 mode during self-refresh */
+	ldr	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+	str	tmp1, .saved_sam9_mdr
+	bic	tmp1, tmp1, #~AT91_DDRSDRC_MD
+	cmp	tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+	ldreq	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+	biceq	tmp1, tmp1, #AT91_DDRSDRC_MD
+	orreq	tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
+	streq	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+
 	/* prepare for DDRAM self-refresh mode */
 	ldr	tmp1, [sdramc, #AT91_DDRSDRC_LPR]
 	str	tmp1, .saved_sam9_lpr
@@ -117,14 +127,26 @@ ddr_sr_enable:
 
 	/* figure out if we use the second ram controller */
 	cmp	ramc1, #0
-	ldrne	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-	strne	tmp2, .saved_sam9_lpr1
-	bicne	tmp2, #AT91_DDRSDRC_LPCB
-	orrne	tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+	beq	ddr_no_2nd_ctrl
+
+	ldr	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+	str	tmp2, .saved_sam9_mdr1
+	bic	tmp2, tmp2, #~AT91_DDRSDRC_MD
+	cmp	tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+	ldreq	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+	biceq	tmp2, tmp2, #AT91_DDRSDRC_MD
+	orreq	tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
+	streq	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+
+	ldr	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+	str	tmp2, .saved_sam9_lpr1
+	bic	tmp2, #AT91_DDRSDRC_LPCB
+	orr	tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
 
 	/* Enable DDRAM self-refresh mode */
+	str	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ddr_no_2nd_ctrl:
 	str	tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-	strne	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
 
 	b	sdr_sr_done
 
@@ -236,12 +258,17 @@ sdr_sr_done:
 	 */
 	cmp	memctrl, #AT91_MEMCTRL_DDRSDR
 	bne	sdr_en_restore
+	/* Restore MDR in case of LPDDR1 */
+	ldr	tmp1, .saved_sam9_mdr
+	str	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
 	/* Restore LPR on AT91 with DDRAM */
 	ldr	tmp1, .saved_sam9_lpr
 	str	tmp1, [sdramc, #AT91_DDRSDRC_LPR]
 
 	/* if we use the second ram controller */
 	cmp	ramc1, #0
+	ldrne	tmp2, .saved_sam9_mdr1
+	strne	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
 	ldrne	tmp2, .saved_sam9_lpr1
 	strne	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
 
@@ -272,5 +299,11 @@ ram_restored:
 .saved_sam9_lpr1:
 	.word 0
 
+.saved_sam9_mdr:
+	.word 0
+
+.saved_sam9_mdr1:
+	.word 0
+
 ENTRY(at91_slow_clock_sz)
 	.word .-at91_slow_clock
diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h
index 0210797..dc10c52 100644
--- a/include/soc/at91/at91sam9_ddrsdr.h
+++ b/include/soc/at91/at91sam9_ddrsdr.h
@@ -92,7 +92,7 @@
 #define		AT91_DDRSDRC_UPD_MR	(3 << 20)	 /* Update load mode register and extended mode register */
 
 #define AT91_DDRSDRC_MDR	0x20	/* Memory Device Register */
-#define		AT91_DDRSDRC_MD		(3 << 0)		/* Memory Device Type */
+#define		AT91_DDRSDRC_MD		(7 << 0)	/* Memory Device Type */
 #define			AT91_DDRSDRC_MD_SDR		0
 #define			AT91_DDRSDRC_MD_LOW_POWER_SDR	1
 #define			AT91_DDRSDRC_MD_LOW_POWER_DDR	3
-- 
1.7.9.5

[PATCH 3/3] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.

[Nicolas Ferre]

Le 05/02/2015 07:02, Wenyou Yang a ?crit :
> From: Peter Rosin <peda@axentia.se>
> 
> The DDRSDR controller fails miserably to put LPDDR1 memories in
> self-refresh. Force the controller to think it has DDR2 memories
> during the self-refresh period, as the DDR2 self-refresh spec is
> equivalent to LPDDR1, and is correctly implemented in the
> controller.
> 
> Assume that the second controller has the same fault, but that is
> untested.
> 
> Signed-off-by: Peter Rosin <peda@axentia.se>
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

Stacked in at91-4.0-fixes.

Bye,


> ---
>  arch/arm/mach-at91/pm_slowclock.S  |   43 +++++++++++++++++++++++++++++++-----
>  include/soc/at91/at91sam9_ddrsdr.h |    2 +-
>  2 files changed, 39 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index 75d8b19..487ae1e 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
> @@ -109,6 +109,16 @@ ddr_sr_enable:
>  	cmp	memctrl, #AT91_MEMCTRL_DDRSDR
>  	bne	sdr_sr_enable
>  
> +	/* LPDDR1 --> force DDR2 mode during self-refresh */
> +	ldr	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
> +	str	tmp1, .saved_sam9_mdr
> +	bic	tmp1, tmp1, #~AT91_DDRSDRC_MD
> +	cmp	tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> +	ldreq	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
> +	biceq	tmp1, tmp1, #AT91_DDRSDRC_MD
> +	orreq	tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
> +	streq	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
> +
>  	/* prepare for DDRAM self-refresh mode */
>  	ldr	tmp1, [sdramc, #AT91_DDRSDRC_LPR]
>  	str	tmp1, .saved_sam9_lpr
> @@ -117,14 +127,26 @@ ddr_sr_enable:
>  
>  	/* figure out if we use the second ram controller */
>  	cmp	ramc1, #0
> -	ldrne	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> -	strne	tmp2, .saved_sam9_lpr1
> -	bicne	tmp2, #AT91_DDRSDRC_LPCB
> -	orrne	tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> +	beq	ddr_no_2nd_ctrl
> +
> +	ldr	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> +	str	tmp2, .saved_sam9_mdr1
> +	bic	tmp2, tmp2, #~AT91_DDRSDRC_MD
> +	cmp	tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> +	ldreq	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> +	biceq	tmp2, tmp2, #AT91_DDRSDRC_MD
> +	orreq	tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> +	streq	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> +
> +	ldr	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> +	str	tmp2, .saved_sam9_lpr1
> +	bic	tmp2, #AT91_DDRSDRC_LPCB
> +	orr	tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
>  
>  	/* Enable DDRAM self-refresh mode */
> +	str	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> +ddr_no_2nd_ctrl:
>  	str	tmp1, [sdramc, #AT91_DDRSDRC_LPR]
> -	strne	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
>  
>  	b	sdr_sr_done
>  
> @@ -236,12 +258,17 @@ sdr_sr_done:
>  	 */
>  	cmp	memctrl, #AT91_MEMCTRL_DDRSDR
>  	bne	sdr_en_restore
> +	/* Restore MDR in case of LPDDR1 */
> +	ldr	tmp1, .saved_sam9_mdr
> +	str	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
>  	/* Restore LPR on AT91 with DDRAM */
>  	ldr	tmp1, .saved_sam9_lpr
>  	str	tmp1, [sdramc, #AT91_DDRSDRC_LPR]
>  
>  	/* if we use the second ram controller */
>  	cmp	ramc1, #0
> +	ldrne	tmp2, .saved_sam9_mdr1
> +	strne	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
>  	ldrne	tmp2, .saved_sam9_lpr1
>  	strne	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
>  
> @@ -272,5 +299,11 @@ ram_restored:
>  .saved_sam9_lpr1:
>  	.word 0
>  
> +.saved_sam9_mdr:
> +	.word 0
> +
> +.saved_sam9_mdr1:
> +	.word 0
> +
>  ENTRY(at91_slow_clock_sz)
>  	.word .-at91_slow_clock
> diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h
> index 0210797..dc10c52 100644
> --- a/include/soc/at91/at91sam9_ddrsdr.h
> +++ b/include/soc/at91/at91sam9_ddrsdr.h
> @@ -92,7 +92,7 @@
>  #define		AT91_DDRSDRC_UPD_MR	(3 << 20)	 /* Update load mode register and extended mode register */
>  
>  #define AT91_DDRSDRC_MDR	0x20	/* Memory Device Register */
> -#define		AT91_DDRSDRC_MD		(3 << 0)		/* Memory Device Type */
> +#define		AT91_DDRSDRC_MD		(7 << 0)	/* Memory Device Type */
>  #define			AT91_DDRSDRC_MD_SDR		0
>  #define			AT91_DDRSDRC_MD_LOW_POWER_SDR	1
>  #define			AT91_DDRSDRC_MD_LOW_POWER_DDR	3
> 


-- 
Nicolas Ferre