[PATCH] ARM: advertise availability of v8 Crypto instructions

[linux@arm.linux.org.uk (Russell King - ARM Linux)]

On Wed, Mar 04, 2015 at 05:04:05PM +0000, Catalin Marinas wrote:
> On Wed, Mar 04, 2015 at 05:31:00PM +0100, Ard Biesheuvel wrote:
> > It doesn't really matter which architecture it is. I just want to be
> > reasonably sure that reading ID_ISAR5 isn't going to explode. If there
> > are other/better ways to guarantee that, I am happy to use those as
> > well. (I noticed that there is a v7-M specific definition of ID_ISAR5
> > in the source which I couldn't find any reference to in any of the
> > Cortex-M TRMs on the infocenter web site.)
> 
> The ARMv7-M reference manual only defines to ID_ISAR4. Maybe it will get
> a fifth register at some point but for now I don't think we should read
> it (I guess it was just copy/paste from the A profile).

I think you need to read carefully the requirements that are placed
upon non-implemented CPUID registers.

In DDI0406C, non-implemented CPUID registers are reserved, but must
behave as RAZ.  I would be very surprised if this were not true for
ARMv7-M.


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