From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Wed, 4 Mar 2015 17:23:53 +0000 Subject: [PATCH] ARM: advertise availability of v8 Crypto instructions In-Reply-To: <20150304170404.GZ28951@e104818-lin.cambridge.arm.com> References: <1425054991-29951-1-git-send-email-ard.biesheuvel@linaro.org> <20150304162049.GX28951@e104818-lin.cambridge.arm.com> <20150304170404.GZ28951@e104818-lin.cambridge.arm.com> Message-ID: <20150304172353.GC8656@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Mar 04, 2015 at 05:04:05PM +0000, Catalin Marinas wrote: > On Wed, Mar 04, 2015 at 05:31:00PM +0100, Ard Biesheuvel wrote: > > It doesn't really matter which architecture it is. I just want to be > > reasonably sure that reading ID_ISAR5 isn't going to explode. If there > > are other/better ways to guarantee that, I am happy to use those as > > well. (I noticed that there is a v7-M specific definition of ID_ISAR5 > > in the source which I couldn't find any reference to in any of the > > Cortex-M TRMs on the infocenter web site.) > > The ARMv7-M reference manual only defines to ID_ISAR4. Maybe it will get > a fifth register at some point but for now I don't think we should read > it (I guess it was just copy/paste from the A profile). I think you need to read carefully the requirements that are placed upon non-implemented CPUID registers. In DDI0406C, non-implemented CPUID registers are reserved, but must behave as RAZ. I would be very surprised if this were not true for ARMv7-M. -- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.