[PATCH 0/3] ARM: sun9i: Add support for PRCM on Allwinner A80 SoC

[PATCH 0/3] ARM: sun9i: Add support for PRCM on Allwinner A80 SoC

[Chen-Yu Tsai]

Hi everyone,

Some time ago I sent out an RFC series, which was not merged due
to lack of matching documentation for the SoC. A few weeks back I
sent out a request for the documents again. I have not received a
response. So I'm sending out the series now.

This series adds support for the Power Reset and Clock Management
module on Allwinner's A80 SoC. The PRCM manages clocks and resets
for the "special" block of peripherals, or the R/RTC block in
earlier SoCs. These peripherals include a standby processor core,
a timer block, a watchdog, pin controller, 1 wire interface, PS/2
interface, a UART, the RSB controller, a DMA controller, a consumer
IR receiver block, 2 I2C controllers, and 2 I2S controllers. We do
not have documents for all the peripherals. Support will be added
where possible.


Patch 1 adds support for the apbs (apb0 in earlier SoCs) gates.

Patch 2 adds sun9i-a80 support to the PRCM mfd driver

Patch 3 adds the clock and reset nodes for the PRCM to the A80 DTSI.


To Allwinner people:
If you have any related documents or comments, please send them out.


Regards,
ChenYu


Chen-Yu Tsai (3):
  clk: sunxi: sun6i-apb0: Add support for sun9i A80 apbs gates
  mfd: sun6i-prcm: Add support for PRCM found on Allwinner A80 SoC
  ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes

 Documentation/devicetree/bindings/clock/sunxi.txt  |  1 +
 .../devicetree/bindings/mfd/sun6i-prcm.txt         |  3 +-
 arch/arm/boot/dts/sun9i-a80.dtsi                   | 54 +++++++++++++++++++-
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c           |  6 +++
 drivers/mfd/sun6i-prcm.c                           | 58 ++++++++++++++++++++++
 5 files changed, 120 insertions(+), 2 deletions(-)

-- 
2.1.4

[PATCH 1/3] clk: sunxi: sun6i-apb0: Add support for sun9i A80 apbs gates

[Chen-Yu Tsai]

This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.

The gate bitmask is not complete. The lowest 7 bits seem to be the
same as found on the A31, judging by Allwinner's kernel sources and
what was enabled by the bootloader. Bits 17 and 18 are documented
in the SDK sources.

This still leaves some peripherals missing, such as the dma controller,
a second i2c controller, and 2 PS/2 controllers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c          | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 3f1dcd879af7..60c85071d022 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -54,6 +54,7 @@ Required properties:
 	"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
 	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+	"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
 	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
 	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index 64f3e46d383c..0039b7375a40 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -29,9 +29,15 @@ static const struct gates_data sun8i_a23_apb0_gates __initconst = {
 	.mask = {0x5D},
 };
 
+/* XXX This is an imcomplete mask due to a lack of documents */
+static const struct gates_data sun9i_a80_apbs_gates __initconst = {
+	.mask = {0x6007f},
+};
+
 static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
 	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
+	{ .compatible = "allwinner,sun9i-a80-apbs-gates-clk", .data = &sun9i_a80_apbs_gates },
 	{ /* sentinel */ }
 };
 
-- 
2.1.4

[PATCH 2/3] mfd: sun6i-prcm: Add support for PRCM found on Allwinner A80 SoC

[Chen-Yu Tsai]

This patch adds support for the PRCM on the A80 SoC. There is little
to no document for this at the moment. Only register offsets are
available. However with some testing, the clock and reset controls
seem to be the similar to the ones on the A31.

One thing that needs verifying is whether the apbs divider is the same
as the A31 or the A23. The lowest divider is different between those
2 implementations.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../devicetree/bindings/mfd/sun6i-prcm.txt         |  3 +-
 drivers/mfd/sun6i-prcm.c                           | 58 ++++++++++++++++++++++
 2 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
index 03c5a551da55..c100abfcb2a4 100644
--- a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
+++ b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
@@ -4,7 +4,8 @@ PRCM is an MFD device exposing several Power Management related devices
 (like clks and reset controllers).
 
 Required properties:
- - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm"
+ - compatible: "allwinner,sun6i-a31-prcm", "allwinner,sun8i-a23-prcm",
+	       "allwinner,sun9i-a80-prcm"
  - reg: The PRCM registers range
 
 The prcm node may contain several subdevices definitions:
diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
index 191173166d65..d067c77fb512 100644
--- a/drivers/mfd/sun6i-prcm.c
+++ b/drivers/mfd/sun6i-prcm.c
@@ -33,6 +33,22 @@ static const struct resource sun6i_a31_apb0_clk_res[] = {
 	},
 };
 
+static const struct resource sun9i_a80_cpus_clk_res[] = {
+	{
+		.start = 0x10,
+		.end = 0x13,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static const struct resource sun9i_a80_apbs_clk_res[] = {
+	{
+		.start = 0x1c,
+		.end = 0x1f,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
 static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
 	{
 		.start = 0x28,
@@ -111,6 +127,39 @@ static const struct mfd_cell sun8i_a23_prcm_subdevs[] = {
 	},
 };
 
+static const struct mfd_cell sun9i_a80_prcm_subdevs[] = {
+	{
+		.name = "sun6i-a31-ar100-clk",
+		.of_compatible = "allwinner,sun6i-a31-ar100-clk",
+		.num_resources = ARRAY_SIZE(sun9i_a80_cpus_clk_res),
+		.resources = sun9i_a80_cpus_clk_res,
+	},
+	{
+		.name = "sun8i-a23-apb0-clk",
+		.of_compatible = "allwinner,sun8i-a23-apb0-clk",
+		.num_resources = ARRAY_SIZE(sun9i_a80_apbs_clk_res),
+		.resources = sun9i_a80_apbs_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-gates-clk",
+		.of_compatible = "allwinner,sun9i-a80-apbs-gates-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
+		.resources = sun6i_a31_apb0_gates_clk_res,
+	},
+	{
+		.name = "sun6i-a31-ir-clk",
+		.of_compatible = "allwinner,sun4i-a10-mod0-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
+		.resources = sun6i_a31_ir_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-clock-reset",
+		.of_compatible = "allwinner,sun6i-a31-clock-reset",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
+		.resources = sun6i_a31_apb0_rstc_res,
+	},
+};
+
 static const struct prcm_data sun6i_a31_prcm_data = {
 	.nsubdevs = ARRAY_SIZE(sun6i_a31_prcm_subdevs),
 	.subdevs = sun6i_a31_prcm_subdevs,
@@ -121,6 +170,11 @@ static const struct prcm_data sun8i_a23_prcm_data = {
 	.subdevs = sun8i_a23_prcm_subdevs,
 };
 
+static const struct prcm_data sun9i_a80_prcm_data = {
+	.nsubdevs = ARRAY_SIZE(sun9i_a80_prcm_subdevs),
+	.subdevs = sun9i_a80_prcm_subdevs,
+};
+
 static const struct of_device_id sun6i_prcm_dt_ids[] = {
 	{
 		.compatible = "allwinner,sun6i-a31-prcm",
@@ -130,6 +184,10 @@ static const struct of_device_id sun6i_prcm_dt_ids[] = {
 		.compatible = "allwinner,sun8i-a23-prcm",
 		.data = &sun8i_a23_prcm_data,
 	},
+	{
+		.compatible = "allwinner,sun9i-a80-prcm",
+		.data = &sun9i_a80_prcm_data,
+	},
 	{ /* sentinel */ },
 };
 
-- 
2.1.4

[PATCH 3/3] ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes

[Chen-Yu Tsai]

This adds the PRCM clocks and reset controls to the A80 dtsi.

The list of apbs clock gates is incomplete. Tests show that bits 0~20
are mutable. We will need documents from Allwinner to complete the
support.

Also update clock and reset phandles for r_uart.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 54 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 2f7f82cc86ba..8db78d87bdb9 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -733,13 +733,65 @@
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		prcm at 08001400 {
+			compatible = "allwinner,sun9i-a80-prcm";
+			reg = <0x08001400 0x200>;
+
+			cpus_clk: cpus_clk {
+				compatible = "allwinner,sun6i-a31-ar100-clk";
+				#clock-cells = <0>;
+				clocks = <&osc32k>, <&osc24M>, <&pll4>;
+				clock-output-names = "cpus";
+			};
+
+			ahbs: ahbs_clk {
+				compatible = "fixed-factor-clock";
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+				clocks = <&cpus_clk>;
+				clock-output-names = "ahbs";
+			};
+
+			apbs: apbs_clk {
+				compatible = "allwinner,sun8i-a23-apb0-clk";
+				#clock-cells = <0>;
+				clocks = <&ahbs>;
+				clock-output-names = "apbs";
+			};
+
+			apbs_gates: apbs_gates_clk {
+				compatible = "allwinner,sun9i-a80-apbs-gates-clk";
+				#clock-cells = <1>;
+				clocks = <&apbs>;
+				clock-output-names = "apbs_pio", "apbs_ir",
+						"apbs_timer", "apbs_rsb",
+						"apbs_uart", "apbs_1wire",
+						"apbs_i2c", "apbs_i2s0",
+						"apbs_i2s1";
+			};
+
+			r_ir_clk: r_ir_clk {
+				#clock-cells = <0>;
+				compatible = "allwinner,sun4i-a10-mod0-clk";
+				clocks = <&osc32k>, <&osc24M>;
+				clock-output-names = "r_ir";
+			};
+
+			apbs_rst: apbs_rst {
+				compatible = "allwinner,sun6i-a31-clock-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		r_uart: serial at 08002800 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x08002800 0x400>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&osc24M>;
+			clocks = <&apbs_gates 4>;
+			resets = <&apbs_rst 4>;
 			status = "disabled";
 		};
 	};
-- 
2.1.4

[PATCH 0/3] ARM: sun9i: Add support for PRCM on Allwinner A80 SoC

[Maxime Ripard]

Hi Chen-Yu,

On Tue, Mar 03, 2015 at 10:21:57AM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> Some time ago I sent out an RFC series, which was not merged due
> to lack of matching documentation for the SoC. A few weeks back I
> sent out a request for the documents again. I have not received a
> response. So I'm sending out the series now.
> 
> This series adds support for the Power Reset and Clock Management
> module on Allwinner's A80 SoC. The PRCM manages clocks and resets
> for the "special" block of peripherals, or the R/RTC block in
> earlier SoCs. These peripherals include a standby processor core,
> a timer block, a watchdog, pin controller, 1 wire interface, PS/2
> interface, a UART, the RSB controller, a DMA controller, a consumer
> IR receiver block, 2 I2C controllers, and 2 I2S controllers. We do
> not have documents for all the peripherals. Support will be added
> where possible.
> 
> 
> Patch 1 adds support for the apbs (apb0 in earlier SoCs) gates.
> 
> Patch 2 adds sun9i-a80 support to the PRCM mfd driver
> 
> Patch 3 adds the clock and reset nodes for the PRCM to the A80 DTSI.

These three patches look fine to me. Have you seen that the new
bootloader code has some interesting infos about RSB and PRCM?

If so, does it match what you did so far?

> To Allwinner people:
> If you have any related documents or comments, please send them out.

Kevin, Shuge, your input would be greatly appreciated.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 0/3] ARM: sun9i: Add support for PRCM on Allwinner A80 SoC

[Chen-Yu Tsai]

Hi,

On Mon, Mar 9, 2015 at 1:32 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On Tue, Mar 03, 2015 at 10:21:57AM +0800, Chen-Yu Tsai wrote:
>> Hi everyone,
>>
>> Some time ago I sent out an RFC series, which was not merged due
>> to lack of matching documentation for the SoC. A few weeks back I
>> sent out a request for the documents again. I have not received a
>> response. So I'm sending out the series now.
>>
>> This series adds support for the Power Reset and Clock Management
>> module on Allwinner's A80 SoC. The PRCM manages clocks and resets
>> for the "special" block of peripherals, or the R/RTC block in
>> earlier SoCs. These peripherals include a standby processor core,
>> a timer block, a watchdog, pin controller, 1 wire interface, PS/2
>> interface, a UART, the RSB controller, a DMA controller, a consumer
>> IR receiver block, 2 I2C controllers, and 2 I2S controllers. We do
>> not have documents for all the peripherals. Support will be added
>> where possible.
>>
>>
>> Patch 1 adds support for the apbs (apb0 in earlier SoCs) gates.
>>
>> Patch 2 adds sun9i-a80 support to the PRCM mfd driver
>>
>> Patch 3 adds the clock and reset nodes for the PRCM to the A80 DTSI.
>
> These three patches look fine to me. Have you seen that the new
> bootloader code has some interesting infos about RSB and PRCM?
>
> If so, does it match what you did so far?

It does. Though that's the only stuff I found on PRCM in there.
Previously I used u-boot and kernel sources from the SDK as a
source of information.

ChenYu

>> To Allwinner people:
>> If you have any related documents or comments, please send them out.
>
> Kevin, Shuge, your input would be greatly appreciated.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[PATCH 2/3] mfd: sun6i-prcm: Add support for PRCM found on Allwinner A80 SoC

[Lee Jones]

On Tue, 03 Mar 2015, Chen-Yu Tsai wrote:

> This patch adds support for the PRCM on the A80 SoC. There is little
> to no document for this at the moment. Only register offsets are
> available. However with some testing, the clock and reset controls
> seem to be the similar to the ones on the A31.
> 
> One thing that needs verifying is whether the apbs divider is the same
> as the A31 or the A23. The lowest divider is different between those
> 2 implementations.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  .../devicetree/bindings/mfd/sun6i-prcm.txt         |  3 +-
>  drivers/mfd/sun6i-prcm.c                           | 58 ++++++++++++++++++++++
>  2 files changed, 60 insertions(+), 1 deletion(-)

Acked-by: Lee Jones <lee.jones@linaro.org>

> diff --git a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
> index 03c5a551da55..c100abfcb2a4 100644
> --- a/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
> +++ b/Documentation/devicetree/bindings/mfd/sun6i-prcm.txt
> @@ -4,7 +4,8 @@ PRCM is an MFD device exposing several Power Management related devices
>  (like clks and reset controllers).
>  
>  Required properties:
> - - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm"
> + - compatible: "allwinner,sun6i-a31-prcm", "allwinner,sun8i-a23-prcm",
> +	       "allwinner,sun9i-a80-prcm"
>   - reg: The PRCM registers range
>  
>  The prcm node may contain several subdevices definitions:
> diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
> index 191173166d65..d067c77fb512 100644
> --- a/drivers/mfd/sun6i-prcm.c
> +++ b/drivers/mfd/sun6i-prcm.c
> @@ -33,6 +33,22 @@ static const struct resource sun6i_a31_apb0_clk_res[] = {
>  	},
>  };
>  
> +static const struct resource sun9i_a80_cpus_clk_res[] = {
> +	{
> +		.start = 0x10,
> +		.end = 0x13,
> +		.flags = IORESOURCE_MEM,
> +	},
> +};
> +
> +static const struct resource sun9i_a80_apbs_clk_res[] = {
> +	{
> +		.start = 0x1c,
> +		.end = 0x1f,
> +		.flags = IORESOURCE_MEM,
> +	},
> +};
> +
>  static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
>  	{
>  		.start = 0x28,
> @@ -111,6 +127,39 @@ static const struct mfd_cell sun8i_a23_prcm_subdevs[] = {
>  	},
>  };
>  
> +static const struct mfd_cell sun9i_a80_prcm_subdevs[] = {
> +	{
> +		.name = "sun6i-a31-ar100-clk",
> +		.of_compatible = "allwinner,sun6i-a31-ar100-clk",
> +		.num_resources = ARRAY_SIZE(sun9i_a80_cpus_clk_res),
> +		.resources = sun9i_a80_cpus_clk_res,
> +	},
> +	{
> +		.name = "sun8i-a23-apb0-clk",
> +		.of_compatible = "allwinner,sun8i-a23-apb0-clk",
> +		.num_resources = ARRAY_SIZE(sun9i_a80_apbs_clk_res),
> +		.resources = sun9i_a80_apbs_clk_res,
> +	},
> +	{
> +		.name = "sun6i-a31-apb0-gates-clk",
> +		.of_compatible = "allwinner,sun9i-a80-apbs-gates-clk",
> +		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
> +		.resources = sun6i_a31_apb0_gates_clk_res,
> +	},
> +	{
> +		.name = "sun6i-a31-ir-clk",
> +		.of_compatible = "allwinner,sun4i-a10-mod0-clk",
> +		.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
> +		.resources = sun6i_a31_ir_clk_res,
> +	},
> +	{
> +		.name = "sun6i-a31-apb0-clock-reset",
> +		.of_compatible = "allwinner,sun6i-a31-clock-reset",
> +		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
> +		.resources = sun6i_a31_apb0_rstc_res,
> +	},
> +};
> +
>  static const struct prcm_data sun6i_a31_prcm_data = {
>  	.nsubdevs = ARRAY_SIZE(sun6i_a31_prcm_subdevs),
>  	.subdevs = sun6i_a31_prcm_subdevs,
> @@ -121,6 +170,11 @@ static const struct prcm_data sun8i_a23_prcm_data = {
>  	.subdevs = sun8i_a23_prcm_subdevs,
>  };
>  
> +static const struct prcm_data sun9i_a80_prcm_data = {
> +	.nsubdevs = ARRAY_SIZE(sun9i_a80_prcm_subdevs),
> +	.subdevs = sun9i_a80_prcm_subdevs,
> +};
> +
>  static const struct of_device_id sun6i_prcm_dt_ids[] = {
>  	{
>  		.compatible = "allwinner,sun6i-a31-prcm",
> @@ -130,6 +184,10 @@ static const struct of_device_id sun6i_prcm_dt_ids[] = {
>  		.compatible = "allwinner,sun8i-a23-prcm",
>  		.data = &sun8i_a23_prcm_data,
>  	},
> +	{
> +		.compatible = "allwinner,sun9i-a80-prcm",
> +		.data = &sun9i_a80_prcm_data,
> +	},
>  	{ /* sentinel */ },
>  };
>  

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
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[PATCH 0/3] ARM: sun9i: Add support for PRCM on Allwinner A80 SoC

[maxime.ripard]

Hi Kevin,

On Tue, Mar 10, 2015 at 09:02:21AM +0800, kevin at allwinnertech.com wrote:
> Dear All,
> 
> I have requested to release the document for the PRCM, but need my boss support.
> I will try my best to convince them, and provide the document ASAP.
> If any progress, I will update to you immediately.

Ok, thanks a lot!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 0/3] ARM: sun9i: Add support for PRCM on Allwinner A80 SoC

[maxime.ripard]

Hi Kevin,

On Mon, Mar 30, 2015 at 05:19:17PM +0800, kevin at allwinnertech.com wrote:
> Hi, Maxime,
> 
> We have add the PRCM module description to the A80 document.
> You can download it from the github: https://github.com/allwinner-zh/documents

Awesome, thanks a lot.

We'll look into it.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 0/3] ARM: sun9i: Add support for PRCM on Allwinner A80 SoC

[Chen-Yu Tsai]

Hi Kevin,

(Dropped a few people from CC.)

On Tue, Mar 31, 2015 at 5:50 AM, maxime.ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Kevin,
>
> On Mon, Mar 30, 2015 at 05:19:17PM +0800, kevin at allwinnertech.com wrote:
>> Hi, Maxime,
>>
>> We have add the PRCM module description to the A80 document.
>> You can download it from the github: https://github.com/allwinner-zh/documents
>
> Awesome, thanks a lot.
>
> We'll look into it.

I looked at the new PRCM description, which is very detailed.
I have some questions though:

1. There is a "PLL_AUDIO control". Is this a new PLL? Or just another
set of mapped
   registers for PLL_AUDIO in CCU? I assume it is the latter.

2. What is the source of "24 MHz" in the main CCU? The external 24 MHz
oscillator
   (HOSC) or the mux after HOSC and CLK16M_RC? (ref: page 331, the
PRCM block diagram)

Please help clarify them. Thank you.


Regards
ChenYu