* [PATCH 01/10] ARM: at91/pm: move the standby functions to pm.c
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-23 10:14 ` Nicolas Ferre
2015-03-16 22:44 ` [PATCH 02/10] ARM: at91/pm: move AT91_MEMCTRL_* to pm.h Alexandre Belloni
` (9 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
The standby functions are now only used in pm.c, move them there.
Also, they are not inlined as a pointer to those functions is passed to the
cpuidle driver.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-at91/pm.h | 92 -------------------------------------------------
2 files changed, 89 insertions(+), 92 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index f93a735ba327..5062699cbb12 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -222,6 +222,95 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
at91_cpuidle_device.dev.platform_data = at91_standby;
}
+/*
+ * The AT91RM9200 goes into self-refresh mode with this command, and will
+ * terminate self-refresh automatically on the next SDRAM access.
+ *
+ * Self-refresh mode is exited as soon as a memory access is made, but we don't
+ * know for sure when that happens. However, we need to restore the low-power
+ * mode if it was enabled before going idle. Restoring low-power mode while
+ * still in self-refresh is "not recommended", but seems to work.
+ */
+static void at91rm9200_standby(void)
+{
+ u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
+
+ asm volatile(
+ "b 1f\n\t"
+ ".align 5\n\t"
+ "1: mcr p15, 0, %0, c7, c10, 4\n\t"
+ " str %0, [%1, %2]\n\t"
+ " str %3, [%1, %4]\n\t"
+ " mcr p15, 0, %0, c7, c0, 4\n\t"
+ " str %5, [%1, %2]"
+ :
+ : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
+ "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
+ "r" (lpr));
+}
+
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
+ */
+static void at91_ddr_standby(void)
+{
+ /* Those two values allow us to delay self-refresh activation
+ * to the maximum. */
+ u32 lpr0, lpr1 = 0;
+ u32 saved_lpr0, saved_lpr1 = 0;
+
+ if (at91_ramc_base[1]) {
+ saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
+ lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
+ lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+ }
+
+ saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+ lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
+ lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+ /* self-refresh mode now */
+ at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
+ if (at91_ramc_base[1])
+ at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
+
+ cpu_do_idle();
+
+ at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
+ if (at91_ramc_base[1])
+ at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
+}
+
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
+ */
+static void at91sam9_sdram_standby(void)
+{
+ u32 lpr0, lpr1 = 0;
+ u32 saved_lpr0, saved_lpr1 = 0;
+
+ if (at91_ramc_base[1]) {
+ saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
+ lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
+ lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+ }
+
+ saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
+ lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
+ lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+
+ /* self-refresh mode now */
+ at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
+ if (at91_ramc_base[1])
+ at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
+
+ cpu_do_idle();
+
+ at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
+ if (at91_ramc_base[1])
+ at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
+}
+
static const struct of_device_id ramc_ids[] __initconst = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index dcacfa1ad3fa..3223967d3460 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -23,96 +23,4 @@
#define AT91_PM_SLOW_CLOCK 0x01
-/*
- * The AT91RM9200 goes into self-refresh mode with this command, and will
- * terminate self-refresh automatically on the next SDRAM access.
- *
- * Self-refresh mode is exited as soon as a memory access is made, but we don't
- * know for sure when that happens. However, we need to restore the low-power
- * mode if it was enabled before going idle. Restoring low-power mode while
- * still in self-refresh is "not recommended", but seems to work.
- */
-
-#ifndef __ASSEMBLY__
-static inline void at91rm9200_standby(void)
-{
- u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
-
- asm volatile(
- "b 1f\n\t"
- ".align 5\n\t"
- "1: mcr p15, 0, %0, c7, c10, 4\n\t"
- " str %0, [%1, %2]\n\t"
- " str %3, [%1, %4]\n\t"
- " mcr p15, 0, %0, c7, c0, 4\n\t"
- " str %5, [%1, %2]"
- :
- : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
- "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
- "r" (lpr));
-}
-
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91_ddr_standby(void)
-{
- /* Those two values allow us to delay self-refresh activation
- * to the maximum. */
- u32 lpr0, lpr1 = 0;
- u32 saved_lpr0, saved_lpr1 = 0;
-
- if (at91_ramc_base[1]) {
- saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
- lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
- lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
- }
-
- saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
- lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
- lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
-
- /* self-refresh mode now */
- at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
-
- cpu_do_idle();
-
- at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
-}
-
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91sam9_sdram_standby(void)
-{
- u32 lpr0, lpr1 = 0;
- u32 saved_lpr0, saved_lpr1 = 0;
-
- if (at91_ramc_base[1]) {
- saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
- lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
- lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
- }
-
- saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
- lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
- lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
-
- /* self-refresh mode now */
- at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
-
- cpu_do_idle();
-
- at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
-}
-
-#endif
#endif
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 01/10] ARM: at91/pm: move the standby functions to pm.c
2015-03-16 22:44 ` [PATCH 01/10] ARM: at91/pm: move the standby functions to pm.c Alexandre Belloni
@ 2015-03-23 10:14 ` Nicolas Ferre
0 siblings, 0 replies; 20+ messages in thread
From: Nicolas Ferre @ 2015-03-23 10:14 UTC (permalink / raw)
To: linux-arm-kernel
Le 16/03/2015 23:44, Alexandre Belloni a ?crit :
> The standby functions are now only used in pm.c, move them there.
>
> Also, they are not inlined as a pointer to those functions is passed to the
> cpuidle driver.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> arch/arm/mach-at91/pm.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-at91/pm.h | 92 -------------------------------------------------
> 2 files changed, 89 insertions(+), 92 deletions(-)
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index f93a735ba327..5062699cbb12 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -222,6 +222,95 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
> at91_cpuidle_device.dev.platform_data = at91_standby;
> }
>
> +/*
> + * The AT91RM9200 goes into self-refresh mode with this command, and will
> + * terminate self-refresh automatically on the next SDRAM access.
> + *
> + * Self-refresh mode is exited as soon as a memory access is made, but we don't
> + * know for sure when that happens. However, we need to restore the low-power
> + * mode if it was enabled before going idle. Restoring low-power mode while
> + * still in self-refresh is "not recommended", but seems to work.
> + */
> +static void at91rm9200_standby(void)
> +{
> + u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
> +
> + asm volatile(
> + "b 1f\n\t"
> + ".align 5\n\t"
> + "1: mcr p15, 0, %0, c7, c10, 4\n\t"
> + " str %0, [%1, %2]\n\t"
> + " str %3, [%1, %4]\n\t"
> + " mcr p15, 0, %0, c7, c0, 4\n\t"
> + " str %5, [%1, %2]"
> + :
> + : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
> + "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
> + "r" (lpr));
> +}
> +
> +/* We manage both DDRAM/SDRAM controllers, we need more than one value to
> + * remember.
> + */
> +static void at91_ddr_standby(void)
> +{
> + /* Those two values allow us to delay self-refresh activation
> + * to the maximum. */
> + u32 lpr0, lpr1 = 0;
> + u32 saved_lpr0, saved_lpr1 = 0;
> +
> + if (at91_ramc_base[1]) {
> + saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
> + lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
> + lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
> + }
> +
> + saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
> + lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
> + lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
> +
> + /* self-refresh mode now */
> + at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
> + if (at91_ramc_base[1])
> + at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
> +
> + cpu_do_idle();
> +
> + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
> + if (at91_ramc_base[1])
> + at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
> +}
> +
> +/* We manage both DDRAM/SDRAM controllers, we need more than one value to
> + * remember.
> + */
> +static void at91sam9_sdram_standby(void)
> +{
> + u32 lpr0, lpr1 = 0;
> + u32 saved_lpr0, saved_lpr1 = 0;
> +
> + if (at91_ramc_base[1]) {
> + saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
> + lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
> + lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
> + }
> +
> + saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
> + lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
> + lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
> +
> + /* self-refresh mode now */
> + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
> + if (at91_ramc_base[1])
> + at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
> +
> + cpu_do_idle();
> +
> + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
> + if (at91_ramc_base[1])
> + at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
> +}
> +
> static const struct of_device_id ramc_ids[] __initconst = {
> { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
> { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index dcacfa1ad3fa..3223967d3460 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -23,96 +23,4 @@
>
> #define AT91_PM_SLOW_CLOCK 0x01
>
> -/*
> - * The AT91RM9200 goes into self-refresh mode with this command, and will
> - * terminate self-refresh automatically on the next SDRAM access.
> - *
> - * Self-refresh mode is exited as soon as a memory access is made, but we don't
> - * know for sure when that happens. However, we need to restore the low-power
> - * mode if it was enabled before going idle. Restoring low-power mode while
> - * still in self-refresh is "not recommended", but seems to work.
> - */
> -
> -#ifndef __ASSEMBLY__
> -static inline void at91rm9200_standby(void)
> -{
> - u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
> -
> - asm volatile(
> - "b 1f\n\t"
> - ".align 5\n\t"
> - "1: mcr p15, 0, %0, c7, c10, 4\n\t"
> - " str %0, [%1, %2]\n\t"
> - " str %3, [%1, %4]\n\t"
> - " mcr p15, 0, %0, c7, c0, 4\n\t"
> - " str %5, [%1, %2]"
> - :
> - : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
> - "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
> - "r" (lpr));
> -}
> -
> -/* We manage both DDRAM/SDRAM controllers, we need more than one value to
> - * remember.
> - */
> -static inline void at91_ddr_standby(void)
> -{
> - /* Those two values allow us to delay self-refresh activation
> - * to the maximum. */
> - u32 lpr0, lpr1 = 0;
> - u32 saved_lpr0, saved_lpr1 = 0;
> -
> - if (at91_ramc_base[1]) {
> - saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
> - lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
> - lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
> - }
> -
> - saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
> - lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
> - lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
> -
> - /* self-refresh mode now */
> - at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
> - if (at91_ramc_base[1])
> - at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
> -
> - cpu_do_idle();
> -
> - at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
> - if (at91_ramc_base[1])
> - at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
> -}
> -
> -/* We manage both DDRAM/SDRAM controllers, we need more than one value to
> - * remember.
> - */
> -static inline void at91sam9_sdram_standby(void)
> -{
> - u32 lpr0, lpr1 = 0;
> - u32 saved_lpr0, saved_lpr1 = 0;
> -
> - if (at91_ramc_base[1]) {
> - saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
> - lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
> - lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
> - }
> -
> - saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
> - lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
> - lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
> -
> - /* self-refresh mode now */
> - at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
> - if (at91_ramc_base[1])
> - at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
> -
> - cpu_do_idle();
> -
> - at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
> - if (at91_ramc_base[1])
> - at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
> -}
> -
> -#endif
> #endif
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 02/10] ARM: at91/pm: move AT91_MEMCTRL_* to pm.h
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
2015-03-16 22:44 ` [PATCH 01/10] ARM: at91/pm: move the standby functions to pm.c Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-23 10:15 ` Nicolas Ferre
2015-03-16 22:44 ` [PATCH 03/10] ata: at91: use syscon to configure the smc Alexandre Belloni
` (8 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
the AT91_MEMCTRL_* defines are only used by the pm code, move them to pm.h
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/include/mach/at91_ramc.h | 4 ----
arch/arm/mach-at91/pm.h | 4 ++++
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
index e4492b151fee..493bc486e858 100644
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[];
.extern at91_ramc_base
#endif
-#define AT91_MEMCTRL_MC 0
-#define AT91_MEMCTRL_SDRAMC 1
-#define AT91_MEMCTRL_DDRSDR 2
-
#include <soc/at91/at91rm9200_sdramc.h>
#include <soc/at91/at91sam9_ddrsdr.h>
#include <soc/at91/at91sam9_sdramc.h>
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 3223967d3460..ecd875a91d52 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -15,6 +15,10 @@
#include <mach/at91_ramc.h>
+#define AT91_MEMCTRL_MC 0
+#define AT91_MEMCTRL_SDRAMC 1
+#define AT91_MEMCTRL_DDRSDR 2
+
#define AT91_PM_MEMTYPE_MASK 0x0f
#define AT91_PM_MODE_OFFSET 4
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 02/10] ARM: at91/pm: move AT91_MEMCTRL_* to pm.h
2015-03-16 22:44 ` [PATCH 02/10] ARM: at91/pm: move AT91_MEMCTRL_* to pm.h Alexandre Belloni
@ 2015-03-23 10:15 ` Nicolas Ferre
0 siblings, 0 replies; 20+ messages in thread
From: Nicolas Ferre @ 2015-03-23 10:15 UTC (permalink / raw)
To: linux-arm-kernel
Le 16/03/2015 23:44, Alexandre Belloni a ?crit :
> the AT91_MEMCTRL_* defines are only used by the pm code, move them to pm.h
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> arch/arm/mach-at91/include/mach/at91_ramc.h | 4 ----
> arch/arm/mach-at91/pm.h | 4 ++++
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
> index e4492b151fee..493bc486e858 100644
> --- a/arch/arm/mach-at91/include/mach/at91_ramc.h
> +++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
> @@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[];
> .extern at91_ramc_base
> #endif
>
> -#define AT91_MEMCTRL_MC 0
> -#define AT91_MEMCTRL_SDRAMC 1
> -#define AT91_MEMCTRL_DDRSDR 2
> -
> #include <soc/at91/at91rm9200_sdramc.h>
> #include <soc/at91/at91sam9_ddrsdr.h>
> #include <soc/at91/at91sam9_sdramc.h>
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index 3223967d3460..ecd875a91d52 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -15,6 +15,10 @@
>
> #include <mach/at91_ramc.h>
>
> +#define AT91_MEMCTRL_MC 0
> +#define AT91_MEMCTRL_SDRAMC 1
> +#define AT91_MEMCTRL_DDRSDR 2
> +
> #define AT91_PM_MEMTYPE_MASK 0x0f
>
> #define AT91_PM_MODE_OFFSET 4
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 03/10] ata: at91: use syscon to configure the smc
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
2015-03-16 22:44 ` [PATCH 01/10] ARM: at91/pm: move the standby functions to pm.c Alexandre Belloni
2015-03-16 22:44 ` [PATCH 02/10] ARM: at91/pm: move AT91_MEMCTRL_* to pm.h Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-23 10:11 ` Nicolas Ferre
2015-03-16 22:44 ` [PATCH 04/10] ARM: at91: drop sam9_smc.c Alexandre Belloni
` (7 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
Use syscon/regmap to configure the smc. This allows to avoid using
at91sam9_smc.h and to compile the driver in a multiplatform configuration.
The driver will still not probe until the proper DT bindings are added.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
drivers/ata/Kconfig | 1 -
drivers/ata/pata_at91.c | 92 ++++++++++++++++++++++++++++++++++++++-----------
2 files changed, 71 insertions(+), 22 deletions(-)
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 5f601553b9b0..a3a13605a9c4 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -835,7 +835,6 @@ config PATA_AT32
config PATA_AT91
tristate "PATA support for AT91SAM9260"
depends on ARM && SOC_AT91SAM9
- depends on !ARCH_MULTIPLATFORM
help
This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
diff --git a/drivers/ata/pata_at91.c b/drivers/ata/pata_at91.c
index 9e85937d36a9..ace0a4de3449 100644
--- a/drivers/ata/pata_at91.c
+++ b/drivers/ata/pata_at91.c
@@ -24,11 +24,13 @@
#include <linux/ata.h>
#include <linux/clk.h>
#include <linux/libata.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/atmel-smc.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/platform_data/atmel.h>
+#include <linux/regmap.h>
-#include <mach/at91sam9_smc.h>
#include <asm/gpio.h>
#define DRV_NAME "pata_at91"
@@ -57,6 +59,15 @@ struct smc_range {
int max;
};
+struct regmap *smc;
+
+struct at91sam9_smc_generic_fields {
+ struct regmap_field *setup;
+ struct regmap_field *pulse;
+ struct regmap_field *cycle;
+ struct regmap_field *mode;
+} fields;
+
/**
* adjust_smc_value - adjust value for one of SMC registers.
* @value: adjusted value
@@ -206,7 +217,6 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
{
int ret = 0;
int use_iordy;
- struct sam9_smc_config smc;
unsigned int t6z; /* data tristate time in ns */
unsigned int cycle; /* SMC Cycle width in MCK ticks */
unsigned int setup; /* SMC Setup width in MCK ticks */
@@ -244,19 +254,21 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
- /* SMC Setup Register */
- smc.nwe_setup = smc.nrd_setup = setup;
- smc.ncs_write_setup = smc.ncs_read_setup = 0;
- /* SMC Pulse Register */
- smc.nwe_pulse = smc.nrd_pulse = pulse;
- smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse;
- /* SMC Cycle Register */
- smc.write_cycle = smc.read_cycle = cycle;
- /* SMC Mode Register*/
- smc.tdf_cycles = tdf_cycles;
- smc.mode = info->mode;
-
- sam9_smc_configure(0, info->cs, &smc);
+ regmap_fields_write(fields.setup, info->cs,
+ AT91SAM9_SMC_NRDSETUP(setup) |
+ AT91SAM9_SMC_NWESETUP(setup) |
+ AT91SAM9_SMC_NCS_NRDSETUP(0) |
+ AT91SAM9_SMC_NCS_WRSETUP(0));
+ regmap_fields_write(fields.pulse, info->cs,
+ AT91SAM9_SMC_NRDPULSE(pulse) |
+ AT91SAM9_SMC_NWEPULSE(pulse) |
+ AT91SAM9_SMC_NCS_NRDPULSE(cs_pulse) |
+ AT91SAM9_SMC_NCS_WRPULSE(cs_pulse));
+ regmap_fields_write(fields.cycle, info->cs,
+ AT91SAM9_SMC_NRDCYCLE(cycle) |
+ AT91SAM9_SMC_NWECYCLE(cycle));
+ regmap_fields_write(fields.mode, info->cs, info->mode |
+ AT91_SMC_TDF_(tdf_cycles));
}
static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
@@ -280,21 +292,21 @@ static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
{
struct at91_ide_info *info = dev->link->ap->host->private_data;
unsigned int consumed;
+ unsigned int mode;
unsigned long flags;
- struct sam9_smc_config smc;
local_irq_save(flags);
- sam9_smc_read_mode(0, info->cs, &smc);
+ regmap_fields_read(fields.mode, info->cs, &mode);
/* set 16bit mode before writing data */
- smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16;
- sam9_smc_write_mode(0, info->cs, &smc);
+ regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
+ AT91_SMC_DBW_16);
consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
/* restore 8bit mode after data is written */
- smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8;
- sam9_smc_write_mode(0, info->cs, &smc);
+ regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
+ AT91_SMC_DBW_8);
local_irq_restore(flags);
return consumed;
@@ -312,6 +324,36 @@ static struct ata_port_operations pata_at91_port_ops = {
.cable_detect = ata_cable_40wire,
};
+static int at91sam9_smc_fields_init(struct device *dev)
+{
+ struct reg_field field = REG_FIELD(0, 0, 31);
+
+ field.id_size = 8;
+ field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ;
+
+ field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC);
+ fields.setup = devm_regmap_field_alloc(dev, smc, field);
+ if (IS_ERR(fields.setup))
+ return PTR_ERR(fields.setup);
+
+ field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC);
+ fields.pulse = devm_regmap_field_alloc(dev, smc, field);
+ if (IS_ERR(fields.pulse))
+ return PTR_ERR(fields.pulse);
+
+ field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC);
+ fields.cycle = devm_regmap_field_alloc(dev, smc, field);
+ if (IS_ERR(fields.cycle))
+ return PTR_ERR(fields.cycle);
+
+ field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC);
+ fields.mode = devm_regmap_field_alloc(dev, smc, field);
+ if (IS_ERR(fields.mode))
+ return PTR_ERR(fields.mode);
+
+ return 0;
+}
+
static int pata_at91_probe(struct platform_device *pdev)
{
struct at91_cf_data *board = dev_get_platdata(&pdev->dev);
@@ -341,6 +383,14 @@ static int pata_at91_probe(struct platform_device *pdev)
irq = board->irq_pin;
+ smc = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "atmel,smc");
+ if (IS_ERR(smc))
+ return PTR_ERR(smc);
+
+ ret = at91sam9_smc_fields_init(dev);
+ if (ret < 0)
+ return ret;
+
/* init ata host */
host = ata_host_alloc(dev, 1);
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 03/10] ata: at91: use syscon to configure the smc
2015-03-16 22:44 ` [PATCH 03/10] ata: at91: use syscon to configure the smc Alexandre Belloni
@ 2015-03-23 10:11 ` Nicolas Ferre
2015-03-23 16:38 ` Alexandre Belloni
0 siblings, 1 reply; 20+ messages in thread
From: Nicolas Ferre @ 2015-03-23 10:11 UTC (permalink / raw)
To: linux-arm-kernel
Le 16/03/2015 23:44, Alexandre Belloni a ?crit :
> Use syscon/regmap to configure the smc. This allows to avoid using
> at91sam9_smc.h and to compile the driver in a multiplatform configuration.
>
> The driver will still not probe until the proper DT bindings are added.
Alexandre, just for the record, can you describe the DT node that will
match this?
Is it one that will be added to
Documentation/devicetree/bindings/mfd/atmel-smc.txt?
...
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> drivers/ata/Kconfig | 1 -
> drivers/ata/pata_at91.c | 92 ++++++++++++++++++++++++++++++++++++++-----------
> 2 files changed, 71 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 5f601553b9b0..a3a13605a9c4 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -835,7 +835,6 @@ config PATA_AT32
> config PATA_AT91
> tristate "PATA support for AT91SAM9260"
> depends on ARM && SOC_AT91SAM9
> - depends on !ARCH_MULTIPLATFORM
> help
> This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
>
> diff --git a/drivers/ata/pata_at91.c b/drivers/ata/pata_at91.c
> index 9e85937d36a9..ace0a4de3449 100644
> --- a/drivers/ata/pata_at91.c
> +++ b/drivers/ata/pata_at91.c
> @@ -24,11 +24,13 @@
> #include <linux/ata.h>
> #include <linux/clk.h>
> #include <linux/libata.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mfd/syscon/atmel-smc.h>
> #include <linux/platform_device.h>
> #include <linux/ata_platform.h>
> #include <linux/platform_data/atmel.h>
> +#include <linux/regmap.h>
>
> -#include <mach/at91sam9_smc.h>
> #include <asm/gpio.h>
>
> #define DRV_NAME "pata_at91"
> @@ -57,6 +59,15 @@ struct smc_range {
> int max;
> };
>
> +struct regmap *smc;
> +
> +struct at91sam9_smc_generic_fields {
> + struct regmap_field *setup;
> + struct regmap_field *pulse;
> + struct regmap_field *cycle;
> + struct regmap_field *mode;
> +} fields;
> +
> /**
> * adjust_smc_value - adjust value for one of SMC registers.
> * @value: adjusted value
> @@ -206,7 +217,6 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
> {
> int ret = 0;
> int use_iordy;
> - struct sam9_smc_config smc;
> unsigned int t6z; /* data tristate time in ns */
> unsigned int cycle; /* SMC Cycle width in MCK ticks */
> unsigned int setup; /* SMC Setup width in MCK ticks */
> @@ -244,19 +254,21 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev,
>
> dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
>
> - /* SMC Setup Register */
> - smc.nwe_setup = smc.nrd_setup = setup;
> - smc.ncs_write_setup = smc.ncs_read_setup = 0;
> - /* SMC Pulse Register */
> - smc.nwe_pulse = smc.nrd_pulse = pulse;
> - smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse;
> - /* SMC Cycle Register */
> - smc.write_cycle = smc.read_cycle = cycle;
> - /* SMC Mode Register*/
> - smc.tdf_cycles = tdf_cycles;
> - smc.mode = info->mode;
> -
> - sam9_smc_configure(0, info->cs, &smc);
> + regmap_fields_write(fields.setup, info->cs,
> + AT91SAM9_SMC_NRDSETUP(setup) |
> + AT91SAM9_SMC_NWESETUP(setup) |
> + AT91SAM9_SMC_NCS_NRDSETUP(0) |
> + AT91SAM9_SMC_NCS_WRSETUP(0));
> + regmap_fields_write(fields.pulse, info->cs,
> + AT91SAM9_SMC_NRDPULSE(pulse) |
> + AT91SAM9_SMC_NWEPULSE(pulse) |
> + AT91SAM9_SMC_NCS_NRDPULSE(cs_pulse) |
> + AT91SAM9_SMC_NCS_WRPULSE(cs_pulse));
> + regmap_fields_write(fields.cycle, info->cs,
> + AT91SAM9_SMC_NRDCYCLE(cycle) |
> + AT91SAM9_SMC_NWECYCLE(cycle));
> + regmap_fields_write(fields.mode, info->cs, info->mode |
> + AT91_SMC_TDF_(tdf_cycles));
> }
>
> static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
> @@ -280,21 +292,21 @@ static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
> {
> struct at91_ide_info *info = dev->link->ap->host->private_data;
> unsigned int consumed;
> + unsigned int mode;
> unsigned long flags;
> - struct sam9_smc_config smc;
>
> local_irq_save(flags);
> - sam9_smc_read_mode(0, info->cs, &smc);
> + regmap_fields_read(fields.mode, info->cs, &mode);
>
> /* set 16bit mode before writing data */
> - smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16;
> - sam9_smc_write_mode(0, info->cs, &smc);
> + regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
> + AT91_SMC_DBW_16);
>
> consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
>
> /* restore 8bit mode after data is written */
> - smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8;
> - sam9_smc_write_mode(0, info->cs, &smc);
> + regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
> + AT91_SMC_DBW_8);
>
> local_irq_restore(flags);
> return consumed;
> @@ -312,6 +324,36 @@ static struct ata_port_operations pata_at91_port_ops = {
> .cable_detect = ata_cable_40wire,
> };
>
> +static int at91sam9_smc_fields_init(struct device *dev)
> +{
> + struct reg_field field = REG_FIELD(0, 0, 31);
> +
> + field.id_size = 8;
> + field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ;
> +
> + field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC);
> + fields.setup = devm_regmap_field_alloc(dev, smc, field);
> + if (IS_ERR(fields.setup))
> + return PTR_ERR(fields.setup);
> +
> + field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC);
> + fields.pulse = devm_regmap_field_alloc(dev, smc, field);
> + if (IS_ERR(fields.pulse))
> + return PTR_ERR(fields.pulse);
> +
> + field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC);
> + fields.cycle = devm_regmap_field_alloc(dev, smc, field);
> + if (IS_ERR(fields.cycle))
> + return PTR_ERR(fields.cycle);
> +
> + field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC);
> + fields.mode = devm_regmap_field_alloc(dev, smc, field);
> + if (IS_ERR(fields.mode))
> + return PTR_ERR(fields.mode);
> +
> + return 0;
> +}
> +
> static int pata_at91_probe(struct platform_device *pdev)
> {
> struct at91_cf_data *board = dev_get_platdata(&pdev->dev);
> @@ -341,6 +383,14 @@ static int pata_at91_probe(struct platform_device *pdev)
>
> irq = board->irq_pin;
>
> + smc = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "atmel,smc");
... yes, regarding this string "atmel,smc": what will it match?
Thanks, bye.
> + if (IS_ERR(smc))
> + return PTR_ERR(smc);
> +
> + ret = at91sam9_smc_fields_init(dev);
> + if (ret < 0)
> + return ret;
> +
> /* init ata host */
>
> host = ata_host_alloc(dev, 1);
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 03/10] ata: at91: use syscon to configure the smc
2015-03-23 10:11 ` Nicolas Ferre
@ 2015-03-23 16:38 ` Alexandre Belloni
0 siblings, 0 replies; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-23 16:38 UTC (permalink / raw)
To: linux-arm-kernel
On 23/03/2015 at 11:11:35 +0100, Nicolas Ferre wrote :
> Le 16/03/2015 23:44, Alexandre Belloni a ?crit :
> > Use syscon/regmap to configure the smc. This allows to avoid using
> > at91sam9_smc.h and to compile the driver in a multiplatform configuration.
> >
> > The driver will still not probe until the proper DT bindings are added.
>
> Alexandre, just for the record, can you describe the DT node that will
> match this?
> Is it one that will be added to
> Documentation/devicetree/bindings/mfd/atmel-smc.txt?
>
I believe it should be documented when the full binding will be defined.
This binding will include a mandatory property:
atmel,smc: phandle to the smc
and will look like:
atmel,smc = <&smc>;
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 04/10] ARM: at91: drop sam9_smc.c
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
` (2 preceding siblings ...)
2015-03-16 22:44 ` [PATCH 03/10] ata: at91: use syscon to configure the smc Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-16 22:44 ` [PATCH 05/10] mfd: syscon: Add Atmel MC (Memory Controller) registers definition Alexandre Belloni
` (6 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
sam9_smc.c has no users anymore, remove it along with both sam9_smc.h and
mach/at91sam9_smc.h
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Makefile | 2 -
arch/arm/mach-at91/include/mach/at91sam9_smc.h | 98 ------------------
arch/arm/mach-at91/sam9_smc.c | 136 -------------------------
arch/arm/mach-at91/sam9_smc.h | 11 --
4 files changed, 247 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9_smc.h
delete mode 100644 arch/arm/mach-at91/sam9_smc.c
delete mode 100644 arch/arm/mach-at91/sam9_smc.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 06a4cefd33a0..3586d977e99d 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -6,8 +6,6 @@ asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
obj-y := soc.o
-obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
-
# CPU-specific support
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
deleted file mode 100644
index ff54a0ce90e3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9_smc.h
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Static Memory Controllers (SMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9_SMC_H
-#define AT91SAM9_SMC_H
-
-#ifndef __ASSEMBLY__
-struct sam9_smc_config {
- /* Setup register */
- u8 ncs_read_setup;
- u8 nrd_setup;
- u8 ncs_write_setup;
- u8 nwe_setup;
-
- /* Pulse register */
- u8 ncs_read_pulse;
- u8 nrd_pulse;
- u8 ncs_write_pulse;
- u8 nwe_pulse;
-
- /* Cycle register */
- u16 read_cycle;
- u16 write_cycle;
-
- /* Mode register */
- u32 mode;
- u8 tdf_cycles:4;
-};
-
-extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
-extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
-extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
-extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
-#endif
-
-#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
-#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
-#define AT91_SMC_NWESETUP_(x) ((x) << 0)
-#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
-#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
-#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
-#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
-#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
-#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
-
-#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
-#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
-#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
-#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
-#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
-#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
-#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
-#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
-#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
-#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
-#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
-#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
-
-#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
-#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
-#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
-#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
-#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
-#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
-#define AT91_SMC_EXNWMODE_READY (3 << 4)
-#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
-#define AT91_SMC_BAT_SELECT (0 << 8)
-#define AT91_SMC_BAT_WRITE (1 << 8)
-#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
-#define AT91_SMC_DBW_8 (0 << 12)
-#define AT91_SMC_DBW_16 (1 << 12)
-#define AT91_SMC_DBW_32 (2 << 12)
-#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
-#define AT91_SMC_TDF_(x) ((x) << 16)
-#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
-#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
-#define AT91_SMC_PS (3 << 28) /* Page Size */
-#define AT91_SMC_PS_4 (0 << 28)
-#define AT91_SMC_PS_8 (1 << 28)
-#define AT91_SMC_PS_16 (2 << 28)
-#define AT91_SMC_PS_32 (3 << 28)
-
-#endif
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
deleted file mode 100644
index 826315af6d11..000000000000
--- a/arch/arm/mach-at91/sam9_smc.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/sam9_smc.c
- *
- * Copyright (C) 2008 Andrew Victor
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include <mach/at91sam9_smc.h>
-
-#include "sam9_smc.h"
-
-
-#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
-
-static void __iomem *smc_base_addr[2];
-
-static void sam9_smc_cs_write_mode(void __iomem *base,
- struct sam9_smc_config *config)
-{
- __raw_writel(config->mode
- | AT91_SMC_TDF_(config->tdf_cycles),
- base + AT91_SMC_MODE);
-}
-
-void sam9_smc_write_mode(int id, int cs,
- struct sam9_smc_config *config)
-{
- sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
-}
-EXPORT_SYMBOL_GPL(sam9_smc_write_mode);
-
-static void sam9_smc_cs_configure(void __iomem *base,
- struct sam9_smc_config *config)
-{
-
- /* Setup register */
- __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
- | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
- | AT91_SMC_NRDSETUP_(config->nrd_setup)
- | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
- base + AT91_SMC_SETUP);
-
- /* Pulse register */
- __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
- | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
- | AT91_SMC_NRDPULSE_(config->nrd_pulse)
- | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
- base + AT91_SMC_PULSE);
-
- /* Cycle register */
- __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
- | AT91_SMC_NRDCYCLE_(config->read_cycle),
- base + AT91_SMC_CYCLE);
-
- /* Mode register */
- sam9_smc_cs_write_mode(base, config);
-}
-
-void sam9_smc_configure(int id, int cs,
- struct sam9_smc_config *config)
-{
- sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
-}
-EXPORT_SYMBOL_GPL(sam9_smc_configure);
-
-static void sam9_smc_cs_read_mode(void __iomem *base,
- struct sam9_smc_config *config)
-{
- u32 val = __raw_readl(base + AT91_SMC_MODE);
-
- config->mode = (val & ~AT91_SMC_NWECYCLE);
- config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
-}
-
-void sam9_smc_read_mode(int id, int cs,
- struct sam9_smc_config *config)
-{
- sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
-}
-EXPORT_SYMBOL_GPL(sam9_smc_read_mode);
-
-static void sam9_smc_cs_read(void __iomem *base,
- struct sam9_smc_config *config)
-{
- u32 val;
-
- /* Setup register */
- val = __raw_readl(base + AT91_SMC_SETUP);
-
- config->nwe_setup = val & AT91_SMC_NWESETUP;
- config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
- config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
- config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
-
- /* Pulse register */
- val = __raw_readl(base + AT91_SMC_PULSE);
-
- config->nwe_pulse = val & AT91_SMC_NWEPULSE;
- config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
- config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
- config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
-
- /* Cycle register */
- val = __raw_readl(base + AT91_SMC_CYCLE);
-
- config->write_cycle = val & AT91_SMC_NWECYCLE;
- config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
-
- /* Mode register */
- sam9_smc_cs_read_mode(base, config);
-}
-
-void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
-{
- sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
-}
-
-void __init at91sam9_ioremap_smc(int id, u32 addr)
-{
- if (id > 1) {
- pr_warn("%s: id > 2\n", __func__);
- return;
- }
- smc_base_addr[id] = ioremap(addr, 512);
- if (!smc_base_addr[id])
- pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
-}
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
deleted file mode 100644
index 3e52dcd4a59f..000000000000
--- a/arch/arm/mach-at91/sam9_smc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/sam9_smc.
- *
- * Copyright (C) 2008 Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-extern void __init at91sam9_ioremap_smc(int id, u32 addr);
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 05/10] mfd: syscon: Add Atmel MC (Memory Controller) registers definition
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
` (3 preceding siblings ...)
2015-03-16 22:44 ` [PATCH 04/10] ARM: at91: drop sam9_smc.c Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-23 9:57 ` Nicolas Ferre
2015-03-23 12:31 ` Lee Jones
2015-03-16 22:44 ` [PATCH 06/10] ARM: at91: declare the at91rm9200 memory controller as a syscon Alexandre Belloni
` (5 subsequent siblings)
10 siblings, 2 replies; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Boris Brezillon <boris.brezillon@free-electrons.com>
The at91rm9200 SoC embeds a Memory Controller block which is used to
configure several aspects of the platform:
- AHB/APB Bus behavior
- SDRAM Controller
- EBI (External Bus Interface) and SMC (Static Memory Controller) config
Those registers might be accessed by different drivers, hence we need to
define it as a syscon device.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
include/linux/mfd/syscon/atmel-mc.h | 144 ++++++++++++++++++++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 include/linux/mfd/syscon/atmel-mc.h
diff --git a/include/linux/mfd/syscon/atmel-mc.h b/include/linux/mfd/syscon/atmel-mc.h
new file mode 100644
index 000000000000..cb7d9fe89e44
--- /dev/null
+++ b/include/linux/mfd/syscon/atmel-mc.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
+ * registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
+#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
+
+/* Memory Controller */
+#define AT91_MC_RCR 0x00
+#define AT91_MC_RCB BIT(0)
+
+#define AT91_MC_ASR 0x04
+#define AT91_MC_UNADD BIT(0)
+#define AT91_MC_MISADD BIT(1)
+#define AT91_MC_ABTSZ GENMASK(9, 8)
+#define AT91_MC_ABTSZ_BYTE (0 << 8)
+#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
+#define AT91_MC_ABTSZ_WORD (2 << 8)
+#define AT91_MC_ABTTYP GENMASK(11, 10)
+#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
+#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
+#define AT91_MC_ABTTYP_FETCH (2 << 10)
+#define AT91_MC_MST(n) BIT(16 + (n))
+#define AT91_MC_SVMST(n) BIT(24 + (n))
+
+#define AT91_MC_AASR 0x08
+
+#define AT91_MC_MPR 0x0c
+#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
+
+/* External Bus Interface (EBI) registers */
+#define AT91_MC_EBI_CSA 0x60
+#define AT91_MC_EBI_CS(n) BIT(x)
+#define AT91_MC_EBI_NUM_CS 8
+
+#define AT91_MC_EBI_CFGR 0x64
+#define AT91_MC_EBI_DBPUC BIT(0)
+
+/* Static Memory Controller (SMC) registers */
+#define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4))
+#define AT91_MC_SMC_NWS GENMASK(6, 0)
+#define AT91_MC_SMC_NWS_(x) ((x) << 0)
+#define AT91_MC_SMC_WSEN BIT(7)
+#define AT91_MC_SMC_TDF GENMASK(11, 8)
+#define AT91_MC_SMC_TDF_(x) ((x) << 8)
+#define AT91_MC_SMC_TDF_MAX 0xf
+#define AT91_MC_SMC_BAT BIT(12)
+#define AT91_MC_SMC_DBW GENMASK(14, 13)
+#define AT91_MC_SMC_DBW_16 (1 << 13)
+#define AT91_MC_SMC_DBW_8 (2 << 13)
+#define AT91_MC_SMC_DPR BIT(15)
+#define AT91_MC_SMC_ACSS GENMASK(17, 16)
+#define AT91_MC_SMC_ACSS_(x) ((x) << 16)
+#define AT91_MC_SMC_ACSS_MAX 3
+#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
+#define AT91_MC_SMC_RWSETUP_(x) ((x) << 24)
+#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
+#define AT91_MC_SMC_RWHOLD_(x) ((x) << 28)
+#define AT91_MC_SMC_RWHOLDSETUP_MAX 7
+
+/* SDRAM Controller registers */
+#define AT91_MC_SDRAMC_MR 0x90
+#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
+#define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0)
+#define AT91_MC_SDRAMC_MODE_NOP (1 << 0)
+#define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0)
+#define AT91_MC_SDRAMC_MODE_LMR (3 << 0)
+#define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
+#define AT91_MC_SDRAMC_DBW_16 BIT(4)
+
+#define AT91_MC_SDRAMC_TR 0x94
+#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)
+
+#define AT91_MC_SDRAMC_CR 0x98
+#define AT91_MC_SDRAMC_NC GENMASK(1, 0)
+#define AT91_MC_SDRAMC_NC_8 (0 << 0)
+#define AT91_MC_SDRAMC_NC_9 (1 << 0)
+#define AT91_MC_SDRAMC_NC_10 (2 << 0)
+#define AT91_MC_SDRAMC_NC_11 (3 << 0)
+#define AT91_MC_SDRAMC_NR GENMASK(3, 2)
+#define AT91_MC_SDRAMC_NR_11 (0 << 2)
+#define AT91_MC_SDRAMC_NR_12 (1 << 2)
+#define AT91_MC_SDRAMC_NR_13 (2 << 2)
+#define AT91_MC_SDRAMC_NB BIT(4)
+#define AT91_MC_SDRAMC_NB_2 (0 << 4)
+#define AT91_MC_SDRAMC_NB_4 (1 << 4)
+#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)
+#define AT91_MC_SDRAMC_CAS_2 (2 << 5)
+#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)
+#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)
+#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)
+#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)
+#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)
+#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)
+
+#define AT91_MC_SDRAMC_SRR 0x9c
+#define AT91_MC_SDRAMC_SRCB BIT(0)
+
+#define AT91_MC_SDRAMC_LPR 0xa0
+#define AT91_MC_SDRAMC_LPCB BIT(0)
+
+#define AT91_MC_SDRAMC_IER 0xa4
+#define AT91_MC_SDRAMC_IDR 0xa8
+#define AT91_MC_SDRAMC_IMR 0xac
+#define AT91_MC_SDRAMC_ISR 0xb0
+#define AT91_MC_SDRAMC_RES BIT(0)
+
+/* Burst Flash Controller register */
+#define AT91_MC_BFC_MR 0xc0
+#define AT91_MC_BFC_BFCOM GENMASK(1, 0)
+#define AT91_MC_BFC_BFCOM_DISABLED (0 << 0)
+#define AT91_MC_BFC_BFCOM_ASYNC (1 << 0)
+#define AT91_MC_BFC_BFCOM_BURST (2 << 0)
+#define AT91_MC_BFC_BFCC GENMASK(3, 2)
+#define AT91_MC_BFC_BFCC_MCK (1 << 2)
+#define AT91_MC_BFC_BFCC_DIV2 (2 << 2)
+#define AT91_MC_BFC_BFCC_DIV4 (3 << 2)
+#define AT91_MC_BFC_AVL GENMASK(7, 4)
+#define AT91_MC_BFC_PAGES GENMASK(10, 8)
+#define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8)
+#define AT91_MC_BFC_PAGES_16 (1 << 8)
+#define AT91_MC_BFC_PAGES_32 (2 << 8)
+#define AT91_MC_BFC_PAGES_64 (3 << 8)
+#define AT91_MC_BFC_PAGES_128 (4 << 8)
+#define AT91_MC_BFC_PAGES_256 (5 << 8)
+#define AT91_MC_BFC_PAGES_512 (6 << 8)
+#define AT91_MC_BFC_PAGES_1024 (7 << 8)
+#define AT91_MC_BFC_OEL GENMASK(13, 12)
+#define AT91_MC_BFC_BAAEN BIT(16)
+#define AT91_MC_BFC_BFOEH BIT(17)
+#define AT91_MC_BFC_MUXEN BIT(18)
+#define AT91_MC_BFC_RDYEN BIT(19)
+
+#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 05/10] mfd: syscon: Add Atmel MC (Memory Controller) registers definition
2015-03-16 22:44 ` [PATCH 05/10] mfd: syscon: Add Atmel MC (Memory Controller) registers definition Alexandre Belloni
@ 2015-03-23 9:57 ` Nicolas Ferre
2015-03-23 14:47 ` Lee Jones
2015-03-23 12:31 ` Lee Jones
1 sibling, 1 reply; 20+ messages in thread
From: Nicolas Ferre @ 2015-03-23 9:57 UTC (permalink / raw)
To: linux-arm-kernel
Le 16/03/2015 23:44, Alexandre Belloni a ?crit :
> From: Boris Brezillon <boris.brezillon@free-electrons.com>
>
> The at91rm9200 SoC embeds a Memory Controller block which is used to
> configure several aspects of the platform:
> - AHB/APB Bus behavior
> - SDRAM Controller
> - EBI (External Bus Interface) and SMC (Static Memory Controller) config
>
> Those registers might be accessed by different drivers, hence we need to
> define it as a syscon device.
>
> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Alexandre, don't you need to Ack this patch at least?
> ---
> include/linux/mfd/syscon/atmel-mc.h | 144 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 144 insertions(+)
> create mode 100644 include/linux/mfd/syscon/atmel-mc.h
>
> diff --git a/include/linux/mfd/syscon/atmel-mc.h b/include/linux/mfd/syscon/atmel-mc.h
> new file mode 100644
> index 000000000000..cb7d9fe89e44
> --- /dev/null
> +++ b/include/linux/mfd/syscon/atmel-mc.h
> @@ -0,0 +1,144 @@
> +/*
> + * Copyright (C) 2005 Ivan Kokshaysky
> + * Copyright (C) SAN People
> + *
> + * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
> + * registers.
> + * Based on AT91RM9200 datasheet revision E.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
> +#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
> +
> +/* Memory Controller */
> +#define AT91_MC_RCR 0x00
> +#define AT91_MC_RCB BIT(0)
> +
> +#define AT91_MC_ASR 0x04
> +#define AT91_MC_UNADD BIT(0)
> +#define AT91_MC_MISADD BIT(1)
> +#define AT91_MC_ABTSZ GENMASK(9, 8)
> +#define AT91_MC_ABTSZ_BYTE (0 << 8)
> +#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
> +#define AT91_MC_ABTSZ_WORD (2 << 8)
> +#define AT91_MC_ABTTYP GENMASK(11, 10)
> +#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
> +#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
> +#define AT91_MC_ABTTYP_FETCH (2 << 10)
> +#define AT91_MC_MST(n) BIT(16 + (n))
> +#define AT91_MC_SVMST(n) BIT(24 + (n))
> +
> +#define AT91_MC_AASR 0x08
> +
> +#define AT91_MC_MPR 0x0c
> +#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
> +
> +/* External Bus Interface (EBI) registers */
> +#define AT91_MC_EBI_CSA 0x60
> +#define AT91_MC_EBI_CS(n) BIT(x)
> +#define AT91_MC_EBI_NUM_CS 8
> +
> +#define AT91_MC_EBI_CFGR 0x64
> +#define AT91_MC_EBI_DBPUC BIT(0)
> +
> +/* Static Memory Controller (SMC) registers */
> +#define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4))
> +#define AT91_MC_SMC_NWS GENMASK(6, 0)
> +#define AT91_MC_SMC_NWS_(x) ((x) << 0)
> +#define AT91_MC_SMC_WSEN BIT(7)
> +#define AT91_MC_SMC_TDF GENMASK(11, 8)
> +#define AT91_MC_SMC_TDF_(x) ((x) << 8)
> +#define AT91_MC_SMC_TDF_MAX 0xf
> +#define AT91_MC_SMC_BAT BIT(12)
> +#define AT91_MC_SMC_DBW GENMASK(14, 13)
> +#define AT91_MC_SMC_DBW_16 (1 << 13)
> +#define AT91_MC_SMC_DBW_8 (2 << 13)
> +#define AT91_MC_SMC_DPR BIT(15)
> +#define AT91_MC_SMC_ACSS GENMASK(17, 16)
> +#define AT91_MC_SMC_ACSS_(x) ((x) << 16)
> +#define AT91_MC_SMC_ACSS_MAX 3
> +#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
> +#define AT91_MC_SMC_RWSETUP_(x) ((x) << 24)
> +#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
> +#define AT91_MC_SMC_RWHOLD_(x) ((x) << 28)
> +#define AT91_MC_SMC_RWHOLDSETUP_MAX 7
> +
> +/* SDRAM Controller registers */
> +#define AT91_MC_SDRAMC_MR 0x90
> +#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
> +#define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0)
> +#define AT91_MC_SDRAMC_MODE_NOP (1 << 0)
> +#define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0)
> +#define AT91_MC_SDRAMC_MODE_LMR (3 << 0)
> +#define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
> +#define AT91_MC_SDRAMC_DBW_16 BIT(4)
> +
> +#define AT91_MC_SDRAMC_TR 0x94
> +#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)
> +
> +#define AT91_MC_SDRAMC_CR 0x98
> +#define AT91_MC_SDRAMC_NC GENMASK(1, 0)
> +#define AT91_MC_SDRAMC_NC_8 (0 << 0)
> +#define AT91_MC_SDRAMC_NC_9 (1 << 0)
> +#define AT91_MC_SDRAMC_NC_10 (2 << 0)
> +#define AT91_MC_SDRAMC_NC_11 (3 << 0)
> +#define AT91_MC_SDRAMC_NR GENMASK(3, 2)
> +#define AT91_MC_SDRAMC_NR_11 (0 << 2)
> +#define AT91_MC_SDRAMC_NR_12 (1 << 2)
> +#define AT91_MC_SDRAMC_NR_13 (2 << 2)
> +#define AT91_MC_SDRAMC_NB BIT(4)
> +#define AT91_MC_SDRAMC_NB_2 (0 << 4)
> +#define AT91_MC_SDRAMC_NB_4 (1 << 4)
> +#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)
> +#define AT91_MC_SDRAMC_CAS_2 (2 << 5)
> +#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)
> +#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)
> +#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)
> +#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)
> +#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)
> +#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)
> +
> +#define AT91_MC_SDRAMC_SRR 0x9c
> +#define AT91_MC_SDRAMC_SRCB BIT(0)
> +
> +#define AT91_MC_SDRAMC_LPR 0xa0
> +#define AT91_MC_SDRAMC_LPCB BIT(0)
> +
> +#define AT91_MC_SDRAMC_IER 0xa4
> +#define AT91_MC_SDRAMC_IDR 0xa8
> +#define AT91_MC_SDRAMC_IMR 0xac
> +#define AT91_MC_SDRAMC_ISR 0xb0
> +#define AT91_MC_SDRAMC_RES BIT(0)
> +
> +/* Burst Flash Controller register */
> +#define AT91_MC_BFC_MR 0xc0
> +#define AT91_MC_BFC_BFCOM GENMASK(1, 0)
> +#define AT91_MC_BFC_BFCOM_DISABLED (0 << 0)
> +#define AT91_MC_BFC_BFCOM_ASYNC (1 << 0)
> +#define AT91_MC_BFC_BFCOM_BURST (2 << 0)
> +#define AT91_MC_BFC_BFCC GENMASK(3, 2)
> +#define AT91_MC_BFC_BFCC_MCK (1 << 2)
> +#define AT91_MC_BFC_BFCC_DIV2 (2 << 2)
> +#define AT91_MC_BFC_BFCC_DIV4 (3 << 2)
> +#define AT91_MC_BFC_AVL GENMASK(7, 4)
> +#define AT91_MC_BFC_PAGES GENMASK(10, 8)
> +#define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8)
> +#define AT91_MC_BFC_PAGES_16 (1 << 8)
> +#define AT91_MC_BFC_PAGES_32 (2 << 8)
> +#define AT91_MC_BFC_PAGES_64 (3 << 8)
> +#define AT91_MC_BFC_PAGES_128 (4 << 8)
> +#define AT91_MC_BFC_PAGES_256 (5 << 8)
> +#define AT91_MC_BFC_PAGES_512 (6 << 8)
> +#define AT91_MC_BFC_PAGES_1024 (7 << 8)
> +#define AT91_MC_BFC_OEL GENMASK(13, 12)
> +#define AT91_MC_BFC_BAAEN BIT(16)
> +#define AT91_MC_BFC_BFOEH BIT(17)
> +#define AT91_MC_BFC_MUXEN BIT(18)
> +#define AT91_MC_BFC_RDYEN BIT(19)
> +
> +#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
>
I'm not a big fan of the use of BIT/GENMASK macros in mix with the <<
operator, but I guess it can be done anyway, so I'm okay:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Bye,
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 05/10] mfd: syscon: Add Atmel MC (Memory Controller) registers definition
2015-03-23 9:57 ` Nicolas Ferre
@ 2015-03-23 14:47 ` Lee Jones
0 siblings, 0 replies; 20+ messages in thread
From: Lee Jones @ 2015-03-23 14:47 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 23 Mar 2015, Nicolas Ferre wrote:
> Le 16/03/2015 23:44, Alexandre Belloni a ?crit :
> > From: Boris Brezillon <boris.brezillon@free-electrons.com>
> >
> > The at91rm9200 SoC embeds a Memory Controller block which is used to
> > configure several aspects of the platform:
> > - AHB/APB Bus behavior
> > - SDRAM Controller
> > - EBI (External Bus Interface) and SMC (Static Memory Controller) config
> >
> > Those registers might be accessed by different drivers, hence we need to
> > define it as a syscon device.
> >
> > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
>
> Alexandre, don't you need to Ack this patch at least?
If he is submitting, he needs his SoB.
> > ---
> > include/linux/mfd/syscon/atmel-mc.h | 144 ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 144 insertions(+)
> > create mode 100644 include/linux/mfd/syscon/atmel-mc.h
> >
> > diff --git a/include/linux/mfd/syscon/atmel-mc.h b/include/linux/mfd/syscon/atmel-mc.h
> > new file mode 100644
> > index 000000000000..cb7d9fe89e44
> > --- /dev/null
> > +++ b/include/linux/mfd/syscon/atmel-mc.h
> > @@ -0,0 +1,144 @@
> > +/*
> > + * Copyright (C) 2005 Ivan Kokshaysky
> > + * Copyright (C) SAN People
> > + *
> > + * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
> > + * registers.
> > + * Based on AT91RM9200 datasheet revision E.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + */
> > +
> > +#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
> > +#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
> > +
> > +/* Memory Controller */
> > +#define AT91_MC_RCR 0x00
> > +#define AT91_MC_RCB BIT(0)
> > +
> > +#define AT91_MC_ASR 0x04
> > +#define AT91_MC_UNADD BIT(0)
> > +#define AT91_MC_MISADD BIT(1)
> > +#define AT91_MC_ABTSZ GENMASK(9, 8)
> > +#define AT91_MC_ABTSZ_BYTE (0 << 8)
> > +#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
> > +#define AT91_MC_ABTSZ_WORD (2 << 8)
> > +#define AT91_MC_ABTTYP GENMASK(11, 10)
> > +#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
> > +#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
> > +#define AT91_MC_ABTTYP_FETCH (2 << 10)
> > +#define AT91_MC_MST(n) BIT(16 + (n))
> > +#define AT91_MC_SVMST(n) BIT(24 + (n))
> > +
> > +#define AT91_MC_AASR 0x08
> > +
> > +#define AT91_MC_MPR 0x0c
> > +#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
> > +
> > +/* External Bus Interface (EBI) registers */
> > +#define AT91_MC_EBI_CSA 0x60
> > +#define AT91_MC_EBI_CS(n) BIT(x)
> > +#define AT91_MC_EBI_NUM_CS 8
> > +
> > +#define AT91_MC_EBI_CFGR 0x64
> > +#define AT91_MC_EBI_DBPUC BIT(0)
> > +
> > +/* Static Memory Controller (SMC) registers */
> > +#define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4))
> > +#define AT91_MC_SMC_NWS GENMASK(6, 0)
> > +#define AT91_MC_SMC_NWS_(x) ((x) << 0)
> > +#define AT91_MC_SMC_WSEN BIT(7)
> > +#define AT91_MC_SMC_TDF GENMASK(11, 8)
> > +#define AT91_MC_SMC_TDF_(x) ((x) << 8)
> > +#define AT91_MC_SMC_TDF_MAX 0xf
> > +#define AT91_MC_SMC_BAT BIT(12)
> > +#define AT91_MC_SMC_DBW GENMASK(14, 13)
> > +#define AT91_MC_SMC_DBW_16 (1 << 13)
> > +#define AT91_MC_SMC_DBW_8 (2 << 13)
> > +#define AT91_MC_SMC_DPR BIT(15)
> > +#define AT91_MC_SMC_ACSS GENMASK(17, 16)
> > +#define AT91_MC_SMC_ACSS_(x) ((x) << 16)
> > +#define AT91_MC_SMC_ACSS_MAX 3
> > +#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
> > +#define AT91_MC_SMC_RWSETUP_(x) ((x) << 24)
> > +#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
> > +#define AT91_MC_SMC_RWHOLD_(x) ((x) << 28)
> > +#define AT91_MC_SMC_RWHOLDSETUP_MAX 7
> > +
> > +/* SDRAM Controller registers */
> > +#define AT91_MC_SDRAMC_MR 0x90
> > +#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
> > +#define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0)
> > +#define AT91_MC_SDRAMC_MODE_NOP (1 << 0)
> > +#define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0)
> > +#define AT91_MC_SDRAMC_MODE_LMR (3 << 0)
> > +#define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
> > +#define AT91_MC_SDRAMC_DBW_16 BIT(4)
> > +
> > +#define AT91_MC_SDRAMC_TR 0x94
> > +#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)
> > +
> > +#define AT91_MC_SDRAMC_CR 0x98
> > +#define AT91_MC_SDRAMC_NC GENMASK(1, 0)
> > +#define AT91_MC_SDRAMC_NC_8 (0 << 0)
> > +#define AT91_MC_SDRAMC_NC_9 (1 << 0)
> > +#define AT91_MC_SDRAMC_NC_10 (2 << 0)
> > +#define AT91_MC_SDRAMC_NC_11 (3 << 0)
> > +#define AT91_MC_SDRAMC_NR GENMASK(3, 2)
> > +#define AT91_MC_SDRAMC_NR_11 (0 << 2)
> > +#define AT91_MC_SDRAMC_NR_12 (1 << 2)
> > +#define AT91_MC_SDRAMC_NR_13 (2 << 2)
> > +#define AT91_MC_SDRAMC_NB BIT(4)
> > +#define AT91_MC_SDRAMC_NB_2 (0 << 4)
> > +#define AT91_MC_SDRAMC_NB_4 (1 << 4)
> > +#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)
> > +#define AT91_MC_SDRAMC_CAS_2 (2 << 5)
> > +#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)
> > +#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)
> > +#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)
> > +#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)
> > +#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)
> > +#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)
> > +
> > +#define AT91_MC_SDRAMC_SRR 0x9c
> > +#define AT91_MC_SDRAMC_SRCB BIT(0)
> > +
> > +#define AT91_MC_SDRAMC_LPR 0xa0
> > +#define AT91_MC_SDRAMC_LPCB BIT(0)
> > +
> > +#define AT91_MC_SDRAMC_IER 0xa4
> > +#define AT91_MC_SDRAMC_IDR 0xa8
> > +#define AT91_MC_SDRAMC_IMR 0xac
> > +#define AT91_MC_SDRAMC_ISR 0xb0
> > +#define AT91_MC_SDRAMC_RES BIT(0)
> > +
> > +/* Burst Flash Controller register */
> > +#define AT91_MC_BFC_MR 0xc0
> > +#define AT91_MC_BFC_BFCOM GENMASK(1, 0)
> > +#define AT91_MC_BFC_BFCOM_DISABLED (0 << 0)
> > +#define AT91_MC_BFC_BFCOM_ASYNC (1 << 0)
> > +#define AT91_MC_BFC_BFCOM_BURST (2 << 0)
> > +#define AT91_MC_BFC_BFCC GENMASK(3, 2)
> > +#define AT91_MC_BFC_BFCC_MCK (1 << 2)
> > +#define AT91_MC_BFC_BFCC_DIV2 (2 << 2)
> > +#define AT91_MC_BFC_BFCC_DIV4 (3 << 2)
> > +#define AT91_MC_BFC_AVL GENMASK(7, 4)
> > +#define AT91_MC_BFC_PAGES GENMASK(10, 8)
> > +#define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8)
> > +#define AT91_MC_BFC_PAGES_16 (1 << 8)
> > +#define AT91_MC_BFC_PAGES_32 (2 << 8)
> > +#define AT91_MC_BFC_PAGES_64 (3 << 8)
> > +#define AT91_MC_BFC_PAGES_128 (4 << 8)
> > +#define AT91_MC_BFC_PAGES_256 (5 << 8)
> > +#define AT91_MC_BFC_PAGES_512 (6 << 8)
> > +#define AT91_MC_BFC_PAGES_1024 (7 << 8)
> > +#define AT91_MC_BFC_OEL GENMASK(13, 12)
> > +#define AT91_MC_BFC_BAAEN BIT(16)
> > +#define AT91_MC_BFC_BFOEH BIT(17)
> > +#define AT91_MC_BFC_MUXEN BIT(18)
> > +#define AT91_MC_BFC_RDYEN BIT(19)
> > +
> > +#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
> >
>
> I'm not a big fan of the use of BIT/GENMASK macros in mix with the <<
> operator, but I guess it can be done anyway, so I'm okay:
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Please ensure Nicolas' Ack is applied to your next submission.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 05/10] mfd: syscon: Add Atmel MC (Memory Controller) registers definition
2015-03-16 22:44 ` [PATCH 05/10] mfd: syscon: Add Atmel MC (Memory Controller) registers definition Alexandre Belloni
2015-03-23 9:57 ` Nicolas Ferre
@ 2015-03-23 12:31 ` Lee Jones
1 sibling, 0 replies; 20+ messages in thread
From: Lee Jones @ 2015-03-23 12:31 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 16 Mar 2015, Alexandre Belloni wrote:
> From: Boris Brezillon <boris.brezillon@free-electrons.com>
>
> The at91rm9200 SoC embeds a Memory Controller block which is used to
> configure several aspects of the platform:
> - AHB/APB Bus behavior
> - SDRAM Controller
> - EBI (External Bus Interface) and SMC (Static Memory Controller) config
>
> Those registers might be accessed by different drivers, hence we need to
> define it as a syscon device.
>
> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> ---
> include/linux/mfd/syscon/atmel-mc.h | 144 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 144 insertions(+)
> create mode 100644 include/linux/mfd/syscon/atmel-mc.h
>
> diff --git a/include/linux/mfd/syscon/atmel-mc.h b/include/linux/mfd/syscon/atmel-mc.h
> new file mode 100644
> index 000000000000..cb7d9fe89e44
> --- /dev/null
> +++ b/include/linux/mfd/syscon/atmel-mc.h
> @@ -0,0 +1,144 @@
> +/*
> + * Copyright (C) 2005 Ivan Kokshaysky
> + * Copyright (C) SAN People
> + *
> + * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
> + * registers.
> + * Based on AT91RM9200 datasheet revision E.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
> +#define _LINUX_MFD_SYSCON_ATMEL_MC_H_
> +
> +/* Memory Controller */
> +#define AT91_MC_RCR 0x00
> +#define AT91_MC_RCB BIT(0)
> +
> +#define AT91_MC_ASR 0x04
> +#define AT91_MC_UNADD BIT(0)
> +#define AT91_MC_MISADD BIT(1)
> +#define AT91_MC_ABTSZ GENMASK(9, 8)
> +#define AT91_MC_ABTSZ_BYTE (0 << 8)
> +#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
> +#define AT91_MC_ABTSZ_WORD (2 << 8)
> +#define AT91_MC_ABTTYP GENMASK(11, 10)
> +#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
> +#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
> +#define AT91_MC_ABTTYP_FETCH (2 << 10)
> +#define AT91_MC_MST(n) BIT(16 + (n))
> +#define AT91_MC_SVMST(n) BIT(24 + (n))
> +
> +#define AT91_MC_AASR 0x08
> +
> +#define AT91_MC_MPR 0x0c
> +#define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
> +
> +/* External Bus Interface (EBI) registers */
> +#define AT91_MC_EBI_CSA 0x60
> +#define AT91_MC_EBI_CS(n) BIT(x)
> +#define AT91_MC_EBI_NUM_CS 8
> +
> +#define AT91_MC_EBI_CFGR 0x64
> +#define AT91_MC_EBI_DBPUC BIT(0)
> +
> +/* Static Memory Controller (SMC) registers */
> +#define AT91_MC_SMC_CSR(n) (0x70 + ((n) * 4))
Nit: Tab here.
> +#define AT91_MC_SMC_NWS GENMASK(6, 0)
> +#define AT91_MC_SMC_NWS_(x) ((x) << 0)
> +#define AT91_MC_SMC_WSEN BIT(7)
> +#define AT91_MC_SMC_TDF GENMASK(11, 8)
> +#define AT91_MC_SMC_TDF_(x) ((x) << 8)
> +#define AT91_MC_SMC_TDF_MAX 0xf
> +#define AT91_MC_SMC_BAT BIT(12)
> +#define AT91_MC_SMC_DBW GENMASK(14, 13)
> +#define AT91_MC_SMC_DBW_16 (1 << 13)
> +#define AT91_MC_SMC_DBW_8 (2 << 13)
> +#define AT91_MC_SMC_DPR BIT(15)
> +#define AT91_MC_SMC_ACSS GENMASK(17, 16)
> +#define AT91_MC_SMC_ACSS_(x) ((x) << 16)
> +#define AT91_MC_SMC_ACSS_MAX 3
> +#define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
> +#define AT91_MC_SMC_RWSETUP_(x) ((x) << 24)
> +#define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
> +#define AT91_MC_SMC_RWHOLD_(x) ((x) << 28)
> +#define AT91_MC_SMC_RWHOLDSETUP_MAX 7
> +
> +/* SDRAM Controller registers */
> +#define AT91_MC_SDRAMC_MR 0x90
> +#define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
> +#define AT91_MC_SDRAMC_MODE_NORMAL (0 << 0)
> +#define AT91_MC_SDRAMC_MODE_NOP (1 << 0)
> +#define AT91_MC_SDRAMC_MODE_PRECHARGE (2 << 0)
> +#define AT91_MC_SDRAMC_MODE_LMR (3 << 0)
> +#define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
> +#define AT91_MC_SDRAMC_DBW_16 BIT(4)
> +
> +#define AT91_MC_SDRAMC_TR 0x94
> +#define AT91_MC_SDRAMC_COUNT GENMASK(11, 0)
> +
> +#define AT91_MC_SDRAMC_CR 0x98
> +#define AT91_MC_SDRAMC_NC GENMASK(1, 0)
> +#define AT91_MC_SDRAMC_NC_8 (0 << 0)
> +#define AT91_MC_SDRAMC_NC_9 (1 << 0)
> +#define AT91_MC_SDRAMC_NC_10 (2 << 0)
> +#define AT91_MC_SDRAMC_NC_11 (3 << 0)
> +#define AT91_MC_SDRAMC_NR GENMASK(3, 2)
> +#define AT91_MC_SDRAMC_NR_11 (0 << 2)
> +#define AT91_MC_SDRAMC_NR_12 (1 << 2)
> +#define AT91_MC_SDRAMC_NR_13 (2 << 2)
> +#define AT91_MC_SDRAMC_NB BIT(4)
Nit: Tab here.
> +#define AT91_MC_SDRAMC_NB_2 (0 << 4)
> +#define AT91_MC_SDRAMC_NB_4 (1 << 4)
> +#define AT91_MC_SDRAMC_CAS GENMASK(6, 5)
> +#define AT91_MC_SDRAMC_CAS_2 (2 << 5)
> +#define AT91_MC_SDRAMC_TWR GENMASK(10, 7)
> +#define AT91_MC_SDRAMC_TRC GENMASK(14, 11)
> +#define AT91_MC_SDRAMC_TRP GENMASK(18, 15)
> +#define AT91_MC_SDRAMC_TRCD GENMASK(22, 19)
> +#define AT91_MC_SDRAMC_TRAS GENMASK(26, 23)
> +#define AT91_MC_SDRAMC_TXSR GENMASK(30, 27)
> +
> +#define AT91_MC_SDRAMC_SRR 0x9c
> +#define AT91_MC_SDRAMC_SRCB BIT(0)
> +
> +#define AT91_MC_SDRAMC_LPR 0xa0
> +#define AT91_MC_SDRAMC_LPCB BIT(0)
> +
> +#define AT91_MC_SDRAMC_IER 0xa4
> +#define AT91_MC_SDRAMC_IDR 0xa8
> +#define AT91_MC_SDRAMC_IMR 0xac
> +#define AT91_MC_SDRAMC_ISR 0xb0
> +#define AT91_MC_SDRAMC_RES BIT(0)
> +
> +/* Burst Flash Controller register */
> +#define AT91_MC_BFC_MR 0xc0
> +#define AT91_MC_BFC_BFCOM GENMASK(1, 0)
> +#define AT91_MC_BFC_BFCOM_DISABLED (0 << 0)
> +#define AT91_MC_BFC_BFCOM_ASYNC (1 << 0)
> +#define AT91_MC_BFC_BFCOM_BURST (2 << 0)
> +#define AT91_MC_BFC_BFCC GENMASK(3, 2)
> +#define AT91_MC_BFC_BFCC_MCK (1 << 2)
> +#define AT91_MC_BFC_BFCC_DIV2 (2 << 2)
> +#define AT91_MC_BFC_BFCC_DIV4 (3 << 2)
> +#define AT91_MC_BFC_AVL GENMASK(7, 4)
> +#define AT91_MC_BFC_PAGES GENMASK(10, 8)
> +#define AT91_MC_BFC_PAGES_NO_PAGE (0 << 8)
> +#define AT91_MC_BFC_PAGES_16 (1 << 8)
> +#define AT91_MC_BFC_PAGES_32 (2 << 8)
> +#define AT91_MC_BFC_PAGES_64 (3 << 8)
> +#define AT91_MC_BFC_PAGES_128 (4 << 8)
> +#define AT91_MC_BFC_PAGES_256 (5 << 8)
> +#define AT91_MC_BFC_PAGES_512 (6 << 8)
> +#define AT91_MC_BFC_PAGES_1024 (7 << 8)
> +#define AT91_MC_BFC_OEL GENMASK(13, 12)
> +#define AT91_MC_BFC_BAAEN BIT(16)
> +#define AT91_MC_BFC_BFOEH BIT(17)
> +#define AT91_MC_BFC_MUXEN BIT(18)
> +#define AT91_MC_BFC_RDYEN BIT(19)
> +
> +#endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */
Once fixed, you can apply my:
Acked-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 06/10] ARM: at91: declare the at91rm9200 memory controller as a syscon
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
` (4 preceding siblings ...)
2015-03-16 22:44 ` [PATCH 05/10] mfd: syscon: Add Atmel MC (Memory Controller) registers definition Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-16 22:44 ` [PATCH 07/10] pcmcia: at91_cf: Use syscon to configure the MC/smc Alexandre Belloni
` (4 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
The at91rm9200 memory controller is not simply an SDRAM controller. It also
controls the EBI (External Bus Interface), the SMC (Static Memory Controller)and
the Burst Flash Controller.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
Documentation/devicetree/bindings/arm/atmel-at91.txt | 2 +-
arch/arm/boot/dts/at91rm9200.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 2e99b5b57350..424ac8cbfa08 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -98,7 +98,7 @@ Example:
};
RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91rm9200-sdramc",
+- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 4fb333bd1f85..6d0fa9b87f46 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -92,7 +92,7 @@
};
ramc0: ramc at ffffff00 {
- compatible = "atmel,at91rm9200-sdramc";
+ compatible = "atmel,at91rm9200-sdramc", "syscon";
reg = <0xffffff00 0x100>;
};
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 07/10] pcmcia: at91_cf: Use syscon to configure the MC/smc
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
` (5 preceding siblings ...)
2015-03-16 22:44 ` [PATCH 06/10] ARM: at91: declare the at91rm9200 memory controller as a syscon Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-16 22:44 ` [PATCH 08/10] ARM: at91/pm: use the atmel-mc syscon defines Alexandre Belloni
` (3 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
Use syscon/regmap to configure the smc part of the memory controller. This
allows to avoid using mach/at91rm9200_mc.h and mach/at91_ramc.h and to compile
the driver in a multiplatform configuration.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
drivers/pcmcia/Kconfig | 1 -
drivers/pcmcia/at91_cf.c | 25 ++++++++++++++-----------
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index 075d5cd4c5ab..56ff3dc1235e 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -280,7 +280,6 @@ config AT91_CF
tristate "AT91 CompactFlash Controller"
depends on PCI
depends on PCMCIA && ARCH_AT91
- depends on !ARCH_MULTIPLATFORM
help
Say Y here to support the CompactFlash controller on AT91 chips.
Or choose M to compile the driver as a module named "at91_cf".
diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c
index e7775a41ae5d..87147bcd1655 100644
--- a/drivers/pcmcia/at91_cf.c
+++ b/drivers/pcmcia/at91_cf.c
@@ -20,16 +20,15 @@
#include <linux/platform_data/atmel.h>
#include <linux/io.h>
#include <linux/sizes.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/atmel-mc.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
+#include <linux/regmap.h>
#include <pcmcia/ss.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-
-
/*
* A0..A10 work in each range; A23 indicates I/O space; A25 is CFRNW;
* some other bit in {A24,A22..A11} is nREG to flag memory access
@@ -40,6 +39,8 @@
#define CF_IO_PHYS (1 << 23)
#define CF_MEM_PHYS (0x017ff800)
+struct regmap *mc;
+
/*--------------------------------------------------------------------------*/
struct at91_cf_socket {
@@ -155,10 +156,7 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
/*
* Use 16 bit accesses unless/until we need 8-bit i/o space.
- */
- csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
-
- /*
+ *
* NOTE: this CF controller ignores IOIS16, so we can't really do
* MAP_AUTOSZ. The 16bit mode allows single byte access on either
* D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many
@@ -169,13 +167,14 @@ static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
* CF 3.0 spec table 35 also giving the D8-D15 option.
*/
if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) {
- csr |= AT91_SMC_DBW_8;
+ csr = AT91_MC_SMC_DBW_8;
dev_dbg(&cf->pdev->dev, "8bit i/o bus\n");
} else {
- csr |= AT91_SMC_DBW_16;
+ csr = AT91_MC_SMC_DBW_16;
dev_dbg(&cf->pdev->dev, "16bit i/o bus\n");
}
- at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr);
+ regmap_update_bits(mc, AT91_MC_SMC_CSR(cf->board->chipselect),
+ AT91_MC_SMC_DBW, csr);
io->start = cf->socket.io_offset;
io->stop = io->start + SZ_2K - 1;
@@ -236,6 +235,10 @@ static int at91_cf_dt_init(struct platform_device *pdev)
pdev->dev.platform_data = board;
+ mc = syscon_regmap_lookup_by_compatible("atmel,at91rm9200-sdramc");
+ if (IS_ERR(mc))
+ return PTR_ERR(mc);
+
return 0;
}
#else
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 08/10] ARM: at91/pm: use the atmel-mc syscon defines
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
` (6 preceding siblings ...)
2015-03-16 22:44 ` [PATCH 07/10] pcmcia: at91_cf: Use syscon to configure the MC/smc Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-16 22:44 ` [PATCH 09/10] ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h Alexandre Belloni
` (2 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
Use the defines from atmel-mc.h instead of at91rm9200_sdramc.h
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/include/mach/at91_ramc.h | 2 +-
arch/arm/mach-at91/pm.c | 8 ++++----
arch/arm/mach-at91/pm_suspend.S | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
index 493bc486e858..39547496d4b0 100644
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -21,7 +21,7 @@ extern void __iomem *at91_ramc_base[];
.extern at91_ramc_base
#endif
-#include <soc/at91/at91rm9200_sdramc.h>
+#include <linux/mfd/syscon/atmel-mc.h>
#include <soc/at91/at91sam9_ddrsdr.h>
#include <soc/at91/at91sam9_sdramc.h>
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5062699cbb12..1e184767c3be 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -233,7 +233,7 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
*/
static void at91rm9200_standby(void)
{
- u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
+ u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
asm volatile(
"b 1f\n\t"
@@ -244,8 +244,8 @@ static void at91rm9200_standby(void)
" mcr p15, 0, %0, c7, c0, 4\n\t"
" str %5, [%1, %2]"
:
- : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
- "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
+ : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
+ "r" (1), "r" (AT91_MC_SDRAMC_SRR),
"r" (lpr));
}
@@ -414,7 +414,7 @@ void __init at91rm9200_pm_init(void)
/*
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
*/
- at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
+ at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
at91_pm_data.memctrl = AT91_MEMCTRL_MC;
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index bd22b2c8a051..fda4e0164ed7 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -216,7 +216,7 @@ ENTRY(at91_sramc_self_refresh)
/* Active SDRAM self-refresh mode */
mov r3, #1
- str r3, [r2, #AT91RM9200_SDRAMC_SRR]
+ str r3, [r2, #AT91_MC_SDRAMC_SRR]
b exit_sramc_sf
ddrc_sf:
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 09/10] ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
` (7 preceding siblings ...)
2015-03-16 22:44 ` [PATCH 08/10] ARM: at91/pm: use the atmel-mc syscon defines Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-23 10:01 ` Nicolas Ferre
2015-03-16 22:44 ` [PATCH 10/10] ARM: at91: remove at91rm9200_sdramc.h Alexandre Belloni
2015-03-23 10:14 ` [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Nicolas Ferre
10 siblings, 1 reply; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
mach/at91_ramc.h and mach/at91rm9200_mc.h are necessary anymore, remove them.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Makefile | 3 -
arch/arm/mach-at91/include/mach/at91_ramc.h | 28 ------
arch/arm/mach-at91/include/mach/at91rm9200_mc.h | 116 ------------------------
arch/arm/mach-at91/pm.h | 14 ++-
arch/arm/mach-at91/pm_suspend.S | 1 -
5 files changed, 13 insertions(+), 149 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/at91_ramc.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91rm9200_mc.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 3586d977e99d..fa4393ab3e7b 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,9 +1,6 @@
#
# Makefile for the linux kernel.
#
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-
obj-y := soc.o
# CPU-specific support
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
deleted file mode 100644
index 39547496d4b0..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Header file for the Atmel RAM Controller
- *
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2 only
- */
-
-#ifndef __AT91_RAMC_H__
-#define __AT91_RAMC_H__
-
-#ifndef __ASSEMBLY__
-extern void __iomem *at91_ramc_base[];
-
-#define at91_ramc_read(id, field) \
- __raw_readl(at91_ramc_base[id] + field)
-
-#define at91_ramc_write(id, field, value) \
- __raw_writel(value, at91_ramc_base[id] + field)
-#else
-.extern at91_ramc_base
-#endif
-
-#include <linux/mfd/syscon/atmel-mc.h>
-#include <soc/at91/at91sam9_ddrsdr.h>
-#include <soc/at91/at91sam9_sdramc.h>
-
-#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
deleted file mode 100644
index aeaadfb452af..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200_mc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_MC_H
-#define AT91RM9200_MC_H
-
-/* Memory Controller */
-#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
-#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
-
-#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
-#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
-#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
-#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
-#define AT91_MC_ABTSZ_BYTE (0 << 8)
-#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
-#define AT91_MC_ABTSZ_WORD (2 << 8)
-#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
-#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
-#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
-#define AT91_MC_ABTTYP_FETCH (2 << 10)
-#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
-#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
-#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
-#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
-#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
-#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
-#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
-#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
-
-#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
-
-#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
-#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
-#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
-#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
-#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
-
-/* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
-#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
-#define AT91_EBI_CS0A_SMC (0 << 0)
-#define AT91_EBI_CS0A_BFC (1 << 0)
-#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_EBI_CS1A_SMC (0 << 1)
-#define AT91_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
-#define AT91_EBI_CS3A_SMC (0 << 3)
-#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
-#define AT91_EBI_CS4A_SMC (0 << 4)
-#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
-#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
-#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
-
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
-#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
-#define AT91_SMC_NWS_(x) ((x) << 0)
-#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
-#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
-#define AT91_SMC_TDF_(x) ((x) << 8)
-#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
-#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
-#define AT91_SMC_DBW_16 (1 << 13)
-#define AT91_SMC_DBW_8 (2 << 13)
-#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
-#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
-#define AT91_SMC_ACSS_STD (0 << 16)
-#define AT91_SMC_ACSS_1 (1 << 16)
-#define AT91_SMC_ACSS_2 (2 << 16)
-#define AT91_SMC_ACSS_3 (3 << 16)
-#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
-#define AT91_SMC_RWSETUP_(x) ((x) << 24)
-#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
-#define AT91_SMC_RWHOLD_(x) ((x) << 28)
-
-/* Burst Flash Controller register */
-#define AT91_BFC_MR 0xc0 /* Mode Register */
-#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
-#define AT91_BFC_BFCOM_DISABLED (0 << 0)
-#define AT91_BFC_BFCOM_ASYNC (1 << 0)
-#define AT91_BFC_BFCOM_BURST (2 << 0)
-#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
-#define AT91_BFC_BFCC_MCK (1 << 2)
-#define AT91_BFC_BFCC_DIV2 (2 << 2)
-#define AT91_BFC_BFCC_DIV4 (3 << 2)
-#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
-#define AT91_BFC_PAGES (7 << 8) /* Page Size */
-#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
-#define AT91_BFC_PAGES_16 (1 << 8)
-#define AT91_BFC_PAGES_32 (2 << 8)
-#define AT91_BFC_PAGES_64 (3 << 8)
-#define AT91_BFC_PAGES_128 (4 << 8)
-#define AT91_BFC_PAGES_256 (5 << 8)
-#define AT91_BFC_PAGES_512 (6 << 8)
-#define AT91_BFC_PAGES_1024 (7 << 8)
-#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
-#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
-#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
-#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
-#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
-
-#endif
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index ecd875a91d52..3fcf8810f14e 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -13,7 +13,19 @@
#include <asm/proc-fns.h>
-#include <mach/at91_ramc.h>
+#include <linux/mfd/syscon/atmel-mc.h>
+#include <soc/at91/at91sam9_ddrsdr.h>
+#include <soc/at91/at91sam9_sdramc.h>
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_ramc_base[];
+
+#define at91_ramc_read(id, field) \
+ __raw_readl(at91_ramc_base[id] + field)
+
+#define at91_ramc_write(id, field, value) \
+ __raw_writel(value, at91_ramc_base[id] + field)
+#endif
#define AT91_MEMCTRL_MC 0
#define AT91_MEMCTRL_SDRAMC 1
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index fda4e0164ed7..0d95f488b47a 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -13,7 +13,6 @@
*/
#include <linux/linkage.h>
#include <linux/clk/at91_pmc.h>
-#include <mach/at91_ramc.h>
#include "pm.h"
#define SRAMC_SELF_FRESH_ACTIVE 0x01
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 09/10] ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h
2015-03-16 22:44 ` [PATCH 09/10] ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h Alexandre Belloni
@ 2015-03-23 10:01 ` Nicolas Ferre
0 siblings, 0 replies; 20+ messages in thread
From: Nicolas Ferre @ 2015-03-23 10:01 UTC (permalink / raw)
To: linux-arm-kernel
Le 16/03/2015 23:44, Alexandre Belloni a ?crit :
> mach/at91_ramc.h and mach/at91rm9200_mc.h are necessary anymore, remove them.
s/are/aren't/ ?
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> arch/arm/mach-at91/Makefile | 3 -
> arch/arm/mach-at91/include/mach/at91_ramc.h | 28 ------
> arch/arm/mach-at91/include/mach/at91rm9200_mc.h | 116 ------------------------
> arch/arm/mach-at91/pm.h | 14 ++-
> arch/arm/mach-at91/pm_suspend.S | 1 -
> 5 files changed, 13 insertions(+), 149 deletions(-)
> delete mode 100644 arch/arm/mach-at91/include/mach/at91_ramc.h
> delete mode 100644 arch/arm/mach-at91/include/mach/at91rm9200_mc.h
>
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 3586d977e99d..fa4393ab3e7b 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -1,9 +1,6 @@
> #
> # Makefile for the linux kernel.
> #
> -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
> -asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
> -
> obj-y := soc.o
>
> # CPU-specific support
> diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
> deleted file mode 100644
> index 39547496d4b0..000000000000
> --- a/arch/arm/mach-at91/include/mach/at91_ramc.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/*
> - * Header file for the Atmel RAM Controller
> - *
> - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> - *
> - * Under GPLv2 only
> - */
> -
> -#ifndef __AT91_RAMC_H__
> -#define __AT91_RAMC_H__
> -
> -#ifndef __ASSEMBLY__
> -extern void __iomem *at91_ramc_base[];
> -
> -#define at91_ramc_read(id, field) \
> - __raw_readl(at91_ramc_base[id] + field)
> -
> -#define at91_ramc_write(id, field, value) \
> - __raw_writel(value, at91_ramc_base[id] + field)
> -#else
> -.extern at91_ramc_base
> -#endif
> -
> -#include <linux/mfd/syscon/atmel-mc.h>
> -#include <soc/at91/at91sam9_ddrsdr.h>
> -#include <soc/at91/at91sam9_sdramc.h>
> -
> -#endif /* __AT91_RAMC_H__ */
> diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
> deleted file mode 100644
> index aeaadfb452af..000000000000
> --- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
> +++ /dev/null
> @@ -1,116 +0,0 @@
> -/*
> - * arch/arm/mach-at91/include/mach/at91rm9200_mc.h
> - *
> - * Copyright (C) 2005 Ivan Kokshaysky
> - * Copyright (C) SAN People
> - *
> - * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
> - * Based on AT91RM9200 datasheet revision E.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - */
> -
> -#ifndef AT91RM9200_MC_H
> -#define AT91RM9200_MC_H
> -
> -/* Memory Controller */
> -#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
> -#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
> -
> -#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
> -#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
> -#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
> -#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
> -#define AT91_MC_ABTSZ_BYTE (0 << 8)
> -#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
> -#define AT91_MC_ABTSZ_WORD (2 << 8)
> -#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
> -#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
> -#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
> -#define AT91_MC_ABTTYP_FETCH (2 << 10)
> -#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
> -#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
> -#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
> -#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
> -#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
> -#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
> -#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
> -#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
> -
> -#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
> -
> -#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
> -#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
> -#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
> -#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
> -#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
> -
> -/* External Bus Interface (EBI) registers */
> -#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
> -#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
> -#define AT91_EBI_CS0A_SMC (0 << 0)
> -#define AT91_EBI_CS0A_BFC (1 << 0)
> -#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
> -#define AT91_EBI_CS1A_SMC (0 << 1)
> -#define AT91_EBI_CS1A_SDRAMC (1 << 1)
> -#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
> -#define AT91_EBI_CS3A_SMC (0 << 3)
> -#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
> -#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
> -#define AT91_EBI_CS4A_SMC (0 << 4)
> -#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
> -#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
> -#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
> -
> -/* Static Memory Controller (SMC) registers */
> -#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
> -#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
> -#define AT91_SMC_NWS_(x) ((x) << 0)
> -#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
> -#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
> -#define AT91_SMC_TDF_(x) ((x) << 8)
> -#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
> -#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
> -#define AT91_SMC_DBW_16 (1 << 13)
> -#define AT91_SMC_DBW_8 (2 << 13)
> -#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
> -#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
> -#define AT91_SMC_ACSS_STD (0 << 16)
> -#define AT91_SMC_ACSS_1 (1 << 16)
> -#define AT91_SMC_ACSS_2 (2 << 16)
> -#define AT91_SMC_ACSS_3 (3 << 16)
> -#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
> -#define AT91_SMC_RWSETUP_(x) ((x) << 24)
> -#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
> -#define AT91_SMC_RWHOLD_(x) ((x) << 28)
> -
> -/* Burst Flash Controller register */
> -#define AT91_BFC_MR 0xc0 /* Mode Register */
> -#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
> -#define AT91_BFC_BFCOM_DISABLED (0 << 0)
> -#define AT91_BFC_BFCOM_ASYNC (1 << 0)
> -#define AT91_BFC_BFCOM_BURST (2 << 0)
> -#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
> -#define AT91_BFC_BFCC_MCK (1 << 2)
> -#define AT91_BFC_BFCC_DIV2 (2 << 2)
> -#define AT91_BFC_BFCC_DIV4 (3 << 2)
> -#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
> -#define AT91_BFC_PAGES (7 << 8) /* Page Size */
> -#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
> -#define AT91_BFC_PAGES_16 (1 << 8)
> -#define AT91_BFC_PAGES_32 (2 << 8)
> -#define AT91_BFC_PAGES_64 (3 << 8)
> -#define AT91_BFC_PAGES_128 (4 << 8)
> -#define AT91_BFC_PAGES_256 (5 << 8)
> -#define AT91_BFC_PAGES_512 (6 << 8)
> -#define AT91_BFC_PAGES_1024 (7 << 8)
> -#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
> -#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
> -#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
> -#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
> -#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
> -
> -#endif
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index ecd875a91d52..3fcf8810f14e 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -13,7 +13,19 @@
>
> #include <asm/proc-fns.h>
>
> -#include <mach/at91_ramc.h>
> +#include <linux/mfd/syscon/atmel-mc.h>
> +#include <soc/at91/at91sam9_ddrsdr.h>
> +#include <soc/at91/at91sam9_sdramc.h>
> +
> +#ifndef __ASSEMBLY__
> +extern void __iomem *at91_ramc_base[];
> +
> +#define at91_ramc_read(id, field) \
> + __raw_readl(at91_ramc_base[id] + field)
> +
> +#define at91_ramc_write(id, field, value) \
> + __raw_writel(value, at91_ramc_base[id] + field)
> +#endif
>
> #define AT91_MEMCTRL_MC 0
> #define AT91_MEMCTRL_SDRAMC 1
> diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
> index fda4e0164ed7..0d95f488b47a 100644
> --- a/arch/arm/mach-at91/pm_suspend.S
> +++ b/arch/arm/mach-at91/pm_suspend.S
> @@ -13,7 +13,6 @@
> */
> #include <linux/linkage.h>
> #include <linux/clk/at91_pmc.h>
> -#include <mach/at91_ramc.h>
> #include "pm.h"
>
> #define SRAMC_SELF_FRESH_ACTIVE 0x01
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 10/10] ARM: at91: remove at91rm9200_sdramc.h
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
` (8 preceding siblings ...)
2015-03-16 22:44 ` [PATCH 09/10] ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h Alexandre Belloni
@ 2015-03-16 22:44 ` Alexandre Belloni
2015-03-23 10:14 ` [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Nicolas Ferre
10 siblings, 0 replies; 20+ messages in thread
From: Alexandre Belloni @ 2015-03-16 22:44 UTC (permalink / raw)
To: linux-arm-kernel
include/soc/at91/at91rm9200_sdramc.h is replaced by
include/linux/mfd/syscon/atmel-smc.h as this is actually a syscon device.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
include/soc/at91/at91rm9200_sdramc.h | 63 ------------------------------------
1 file changed, 63 deletions(-)
delete mode 100644 include/soc/at91/at91rm9200_sdramc.h
diff --git a/include/soc/at91/at91rm9200_sdramc.h b/include/soc/at91/at91rm9200_sdramc.h
deleted file mode 100644
index aa047f458f1b..000000000000
--- a/include/soc/at91/at91rm9200_sdramc.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Memory Controllers (SDRAMC only) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_SDRAMC_H
-#define AT91RM9200_SDRAMC_H
-
-/* SDRAM Controller registers */
-#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
-#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
-#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
-#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
-#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
-#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
-#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
-#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
-#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
-#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
-
-#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
-#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
-
-#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
-#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
-#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
-#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
-#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
-#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
-#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
-#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
-#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
-#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
-#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
-#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
-#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
-#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
-#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
-#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
-#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
-#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
-#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
-#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
-#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
-
-#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
-#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
-#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
-#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
-#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
-#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
-
-#endif
--
2.1.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 00/10] ARM: at91 cleanups for 4.1 #2
2015-03-16 22:44 [PATCH 00/10] ARM: at91 cleanups for 4.1 #2 Alexandre Belloni
` (9 preceding siblings ...)
2015-03-16 22:44 ` [PATCH 10/10] ARM: at91: remove at91rm9200_sdramc.h Alexandre Belloni
@ 2015-03-23 10:14 ` Nicolas Ferre
10 siblings, 0 replies; 20+ messages in thread
From: Nicolas Ferre @ 2015-03-23 10:14 UTC (permalink / raw)
To: linux-arm-kernel
Le 16/03/2015 23:44, Alexandre Belloni a ?crit :
> Hi,
>
> This patch set finishes the clean up of the mach-at91 directory.
>
> It fixed the remaining two drivers (at91_cf and pata_at91) so that they compile
> in a multiplatform configuration.
>
> Then it removes the uneeded headers.
>
>
> Alexandre Belloni (9):
> ARM: at91/pm: move the standby functions to pm.c
> ARM: at91/pm: move AT91_MEMCTRL_* to pm.h
Ok, I only take the first 2 patches of this series for now.
The rest looks good as well, but I need more insight and the review from
Lee to go forward.
Thanks, bye.
> ata: at91: use syscon to configure the smc
> ARM: at91: drop sam9_smc.c
> ARM: at91: declare the at91rm9200 memory controller as a syscon
> pcmcia: at91_cf: Use syscon to configure the MC/smc
> ARM: at91/pm: use the atmel-mc syscon defines
> ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h
> ARM: at91: remove at91rm9200_sdramc.h
>
> Boris Brezillon (1):
> mfd: syscon: Add Atmel MC (Memory Controller) registers definition
>
> .../devicetree/bindings/arm/atmel-at91.txt | 2 +-
> arch/arm/boot/dts/at91rm9200.dtsi | 2 +-
> arch/arm/mach-at91/Makefile | 5 -
> arch/arm/mach-at91/include/mach/at91_ramc.h | 32 -----
> arch/arm/mach-at91/include/mach/at91rm9200_mc.h | 116 -----------------
> arch/arm/mach-at91/include/mach/at91sam9_smc.h | 98 --------------
> arch/arm/mach-at91/pm.c | 91 ++++++++++++-
> arch/arm/mach-at91/pm.h | 110 +++-------------
> arch/arm/mach-at91/pm_suspend.S | 3 +-
> arch/arm/mach-at91/sam9_smc.c | 136 -------------------
> arch/arm/mach-at91/sam9_smc.h | 11 --
> drivers/ata/Kconfig | 1 -
> drivers/ata/pata_at91.c | 92 ++++++++++---
> drivers/pcmcia/Kconfig | 1 -
> drivers/pcmcia/at91_cf.c | 25 ++--
> include/linux/mfd/syscon/atmel-mc.h | 144 +++++++++++++++++++++
> include/soc/at91/at91rm9200_sdramc.h | 63 ---------
> 17 files changed, 339 insertions(+), 593 deletions(-)
> delete mode 100644 arch/arm/mach-at91/include/mach/at91_ramc.h
> delete mode 100644 arch/arm/mach-at91/include/mach/at91rm9200_mc.h
> delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9_smc.h
> delete mode 100644 arch/arm/mach-at91/sam9_smc.c
> delete mode 100644 arch/arm/mach-at91/sam9_smc.h
> create mode 100644 include/linux/mfd/syscon/atmel-mc.h
> delete mode 100644 include/soc/at91/at91rm9200_sdramc.h
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 20+ messages in thread