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From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/3] clk: sunxi: Add muxable AHB clock to fix hstimer issues
Date: Wed, 25 Mar 2015 14:53:09 -0700	[thread overview]
Message-ID: <20150325215309.GN23664@lukather> (raw)
In-Reply-To: <CAGb2v66e=ssx=gPMVkc=u0WbhtwCHgbR2Vg3Q3wNTSsBZniaMA@mail.gmail.com>

On Wed, Mar 25, 2015 at 01:13:46PM -0700, Chen-Yu Tsai wrote:
> On Wed, Mar 25, 2015 at 11:51 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Wed, Mar 25, 2015 at 01:22:06AM +0800, Chen-Yu Tsai wrote:
> >> Hi everyone,
> >>
> >> This is v2 of the sun5i muxable AHB clock series.
> >>
> >> Changes since v1:
> >>
> >>   - Dropped patches 1~3 that are merged
> >>   - Extend comments to clarify what the "base factor clock" refers to,
> >>     and what the divs clocks outputs should be.
> >>
> >>
> >> This series adds support for the muxable ahb clock on sun5/7i. The mux
> >> has inputs such as the axi clock, the cpu clock on sun5i, and pll6 with
> >> various dividers. The goal is to have ahb muxed to pll6, which should
> >> be a fixed rate albeit configurable clock. This fixes issues with
> >> cpufreq changing the cpu frequency, which would affect the hstimer
> >> clocked from ahb.
> >>
> >> Patch 1 makes divs clocks explicitly specify in the driver which output
> >> is the base factor clock, instead of always putting it in last. This is
> >> done to ensure DT bindings compatibility when we add outputs.
> >>
> >> Patch 2 adds the new pll6/4 output, which is used on sun7i as an input
> >> to ahb mux.
> >>
> >> Patch 3 updates the dtsi files with the new drivers.
> >>
> >> The series is also available at
> >>
> >>     https://github.com/wens/linux/commits/sun5i-ahb-v2
> >
> > Applied all three. I think it would be great to convert the later SoCs
> > to that too, just to make sure we have the same policy on all SoCs.
> 
> For sun6i this is already doable. We just move the assignment from the
> dmaengine node to the clock node.

Yep.

> For sun8i the default divider results in 300 MHz for AHB, which might
> be too fast.

I guess you're talking about AHB1? APB2 should be muxed to PLL6 as
well.

> And we can't do clock rate assignment yet. The clock drivers need
> to be split out.

Why?

> For sun9i it is already the default.

Perfect.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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  reply	other threads:[~2015-03-25 21:53 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-24 17:22 [PATCH v2 0/3] clk: sunxi: Add muxable AHB clock to fix hstimer issues Chen-Yu Tsai
2015-03-24 17:22 ` [PATCH v2 1/3] clk: sunxi: Make divs clocks specify which output is the base factor clock Chen-Yu Tsai
2015-03-24 17:22 ` [PATCH v2 2/3] clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6 Chen-Yu Tsai
2015-03-24 17:22 ` [PATCH v2 3/3] ARM: dts: sunxi: Update ahb clocks for sun5i and sun7i Chen-Yu Tsai
2015-03-25 18:51 ` [PATCH v2 0/3] clk: sunxi: Add muxable AHB clock to fix hstimer issues Maxime Ripard
2015-03-25 20:13   ` Chen-Yu Tsai
2015-03-25 21:53     ` Maxime Ripard [this message]
2015-03-25 22:04       ` Chen-Yu Tsai
2015-03-30 21:58         ` Maxime Ripard

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