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From: robert.richter@caviumnetworks.com (Robert Richter)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] arm64: gicv3: its: Increase FORCE_MAX_ZONEORDER for Cavium ThunderX
Date: Tue, 12 May 2015 18:20:49 +0200	[thread overview]
Message-ID: <20150512162049.GP10428@rric.localhost> (raw)
In-Reply-To: <20150512123056.GA2062@arm.com>

Will,

On 12.05.15 13:30:57, Will Deacon wrote:
> On Mon, May 11, 2015 at 10:14:38AM +0100, Robert Richter wrote:
> > On 05.05.15 11:53:29, Will Deacon wrote:
> > > On Sun, May 03, 2015 at 09:49:32PM +0100, Robert Richter wrote:
> > > > From: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
> > > > 
> > > > In case of ARCH_THUNDER, there is a need to allocate the GICv3 ITS table
> > > > which is bigger than the allowed max order. So we are forcing it only in
> > > > case of 4KB page size.
> > > 
> > > Does this problem disappear if the ITS driver uses dma_alloc_coherent
> > > instead? That would also allow us to remove the __flush_dcache_area abuse
> > > from the driver.
> > 
> > __get_free_pages() is also used internally in dma_alloc_coherent().
> > 
> > There is another case if the device brings dma mem with it. I am not
> > sure if it would be possible to assign some phys memory via devicetree
> > to the interrupt controller and then assign that range for its table
> > allocation.
> > 
> > Another option would be to allocate a hugepage. This would require
> > setting up hugepages during boottime. I need to figure out whether
> > that could work.

For allocation of 16MB cont. phys mem of a defconfig kernel (4KB
default pagesize) I see this different approaches:

 * set FORCE_MAX_ZONEORDER to 13 as default,

 * set FORCE_MAX_ZONEORDER to 13 if ARM_GIC_V3 is set,

 * set FORCE_MAX_ZONEORDER to 13 if ARCH_THUNDER is set (this patch),

 * use hugepages if enabled (defconfig has the following options
   enable: CGROUP_HUGETLB, TRANSPARENT_HUGEPAGE, HUGETLBFS, this might
   work with current default kernel without changing defconfig
   options),

 * use devicetree to reserve mem for gicv3 (need to check ACPI).

Do you see any direction?

> > What about on the remaining 3 patches?
> 
> Marc would be the best guy to review those, but he's on holiday for a couple
> of weeks at the moment.

Thanks for the note and your comments.

-Robert

  reply	other threads:[~2015-05-12 16:20 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-03 20:49 [PATCH 0/4] arm64: gicv3: its: Fixes and updates for ThunderX Robert Richter
2015-05-03 20:49 ` [PATCH 1/4] arm64: gicv3: its: Encode domain number in PCI stream id Robert Richter
2015-05-20 12:11   ` Marc Zyngier
2015-05-20 12:48     ` Robert Richter
2015-05-22  8:26       ` Marc Zyngier
2015-05-22 22:57         ` Chalamarla, Tirumalesh
2015-05-25 10:38           ` Marc Zyngier
2015-05-03 20:49 ` [PATCH 2/4] arm64: gicv3: its: Add range check for number of allocated pages Robert Richter
2015-05-20 12:14   ` Marc Zyngier
2015-05-03 20:49 ` [PATCH 3/4] arm64: gicv3: its: Read typer register outside the loop Robert Richter
2015-05-20 12:15   ` Marc Zyngier
2015-05-03 20:49 ` [PATCH 4/4] arm64: gicv3: its: Increase FORCE_MAX_ZONEORDER for Cavium ThunderX Robert Richter
2015-05-05 10:53   ` Will Deacon
2015-05-11  9:14     ` Robert Richter
2015-05-12 12:30       ` Will Deacon
2015-05-12 16:20         ` Robert Richter [this message]
2015-05-12 17:24           ` Will Deacon
2015-05-12 17:46             ` Robert Richter
2015-05-20 12:22             ` Marc Zyngier
2015-05-20 12:31               ` Robert Richter
2015-05-20 16:48                 ` Catalin Marinas
2015-05-21  8:35                   ` Marc Zyngier
2015-05-21 12:13                     ` Robert Richter

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